ON MAC4DCNT4 Triacs silicon bidirectional thyristor Datasheet

MAC4DCM, MAC4DCN
Preferred Device
Triacs
Silicon Bidirectional Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
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Features
•
•
•
•
•
•
•
•
•
Small Size Surface Mount DPAK Package
Passivated Die for Reliability and Uniformity
Blocking Voltage to 800 V
On−State Current Rating of 4.0 A RMS at 108°C
High Immunity to dv/dt − 500 V/s at 125°C
High Immunity to di/dt − 6.0 A/ms at 125°C
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
Pb−Free Packages are Available
TRIACS
4.0 AMPERES RMS
600 − 800 VOLTS
MT2
G
MARKING
DIAGRAMS
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Peak Repetitive Off−State Voltage
(Note 1) (TJ = −40 to 125°C, Sine Wave,
50 to 60 Hz, Gate Open)
MAC4DCM
MAC4DCN
VDRM,
VRRM
On−State RMS Current
(Full Cycle Sine Wave, 60 Hz,
TC = 108°C)
IT(RMS)
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
TJ = 125°C)
Circuit Fusing Consideration
(t = 8.3 msec)
Peak Gate Power
(Pulse Width ≤ 10 sec, TC = 108°C)
Average Gate Power
(t = 8.3 msec, TC = 108°C)
4
Value
Unit
V
4.0
YWW
AC
4DCxG
3
DPAK−3
CASE 369D
STYLE 6
A
1
40
A
I2t
6.6
A2sec
PGM
0.5
W
PG(AV)
0.1
W
IGM
Peak Gate Voltage
(Pulse Width ≤ 10 sec, TC = 108°C)
VGM
5.0
V
Operating Junction Temperature Range
TJ
−40 to 125
°C
Storage Temperature Range
Tstg
−40 to 150
°C
0.5
A
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.
May, 2006 − Rev. 6
DPAK
CASE 369C
STYLE 6
4
Peak Gate Current
(Pulse Width ≤ 10 sec, TC = 108°C)
© Semiconductor Components Industries, LLC, 2006
1 2
600
800
ITSM
MT1
1
2
YWW
AC
4DCxG
3
Y
WW
AC4DCx
G
= Year
= Work Week
= Device Code
x= M or N
= Pb−Free Package
PIN ASSIGNMENT
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MAC4DCM/D
MAC4DCM, MAC4DCN
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, − Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering Purposes (Note 3)
Symbol
Max
Unit
RJC
RJA
RJA
3.5
88
80
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
−
−
−
−
0.01
2.0
−
1.3
1.6
8.0
8.0
8.0
12
18
22
35
35
35
0.5
0.5
0.5
0.8
0.8
0.8
1.3
1.3
1.3
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
IDRM,
IRRM
TJ = 25°C
TJ = 125°C
mA
ON CHARACTERISTICS
Peak On−State Voltage (Note 4) (ITM = ± 6.0 A)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IGT
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
VGT
Gate Non−Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+); MT2(+), G(−); MT2(−), G(−)
TJ = 125°C
VGD
0.2
0.4
−
V
Holding Current (VD = 12 V, Gate Open, Initiating Current = ± 200 mA)
IH
6.0
22
35
mA
Latching Current (VD = 12 V, IG = 35 mA)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IL
−
−
−
30
50
20
60
80
60
6.0
8.4
−
A/ms
500
1700
−
V/s
V
mA
V
mA
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
(VD = 400 V, ITM = 4.0 A, Commutating dv/dt = 18 V/sec,
Gate Open, TJ = 125°C, f = 250 Hz, CL = 5.0 F, LL = 20 mH, No Snubber)
(See Figure 16)
di/dt(c)
Critical Rate of Rise of Off−State Voltage
dv/dt
(VD = 0.67 X Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
3. 1/8″ from case for 10 seconds.
4. Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%.
ORDERING INFORMATION
Package Type
Package
Shipping †
MAC4DCM−001
DPAK−3
369D
75 Units / Rail
MAC4DCM−1G
DPAK−3
(Pb−Free)
369D
75 Units / Rail
Device
MAC4DCMT4
DPAK
369C
2500 / Tape & Reel
MAC4DCMT4G
DPAK
(Pb−Free)
369C
2500 / Tape & Reel
MAC4DCN−001
DPAK−3
369D
75 Units / Rail
MAC4DCN−1G
DPAK−3
(Pb−Free)
369D
75 Units / Rail
DPAK
369C
2500 / Tape & Reel
DPAK
(Pb−Free)
369C
2500 / Tape & Reel
MAC4DCNT4
MAC4DCNT4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MAC4DCM, MAC4DCN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VDRM
Peak Repetitive Forward Off−State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off−State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On−State Voltage
IH
VTM
on state
IH
IRRM at VRRM
off state
IH
Holding Current
Quadrant 3
MainTerminal 2 −
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
Quadrant III
Quadrant 1
MainTerminal 2 +
(−) MT2
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
+ Voltage
IDRM at VDRM
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)
MAC4DCM, MAC4DCN
125
= 30°
120
60°
90°
115
α
α
110
120°
= CONDUCTION ANGLE
180°
dc
I T, INSTANTANEOUS ON−STATE CURRENT (AMPS)
105
0
0.5
1.0
1.5
2.5
2.0
3.0
3.5
α
120°
α
4.0
90°
= CONDUCTION ANGLE
3.0
2.0
60°
= 30°
1.0
0
0
1.0
3.0
2.0
4.0
IT(RMS), RMS ON−STATE CURRENT (AMPS)
IT(RMS), RMS ON−STATE CURRENT (AMPS)
Figure 1. RMS Current Derating
Figure 2. On−State Power Dissipation
r(t) , TRANSIENT RESISTANCE (NORMALIZED)
TYPICAL @ TJ = 25°C
MAXIMUM @ TJ = 125°C
10
MAXIMUM @ TJ = 25°C
1.0
0.1
1.0
2.0
0.1
ZJC(t) = RJC(t)Sr(t)
0.01
5.0
4.0
3.0
1.0
0.1
1.0
10
100
1000
10 k
VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
t, TIME (ms)
Figure 3. On−State Characteristics
Figure 4. Transient Thermal Response
1.2
VGT, GATE TRIGGER VOLTAGE(VOLTS)
60
I GT, GATE TRIGGER CURRENT (mA)
dc
180°
5.0
4.0
100
0
6.0
50
40
30
Q3
Q2
20
Q1
10
0
−50
1.0
0.8
Q1
Q2
Q3
0.6
0.4
0.2
0
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Gate Trigger Current versus
Junction Temperature
Figure 6. Typical Gate Trigger Voltage versus
Junction Temperature
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4
60
120
50
100
IL, LATCHING CURRENT (mA)
IH , HOLDING CURRENT (mA)
MAC4DCM, MAC4DCN
MT2 POSITIVE
40
30
20
MT2 NEGATIVE
10
Q2
80
60
Q1
40
Q3
20
0
0
−50
−25
0
25
50
75
125
100
−50
−25
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Holding Current versus
Junction Temperature
Figure 8. Typical Latching Current versus
Junction Temperature
15 K
10 K
TJ = 125°C
TJ = 125°C
VPK = 400 V
6.0 K
STATIC dv/dt (V/ s)
STATIC dv/dt (V/ s)
8.0 K
VPK = 400 V
600 V
4.0 K
125
100
800 V
10 K
600 V
800 V
5.0 K
2.0 K
0
0
100
1000
10 K
100
Figure 9. Exponential Static dv/dt versus
Gate−MT1 Resistance, MT2(+)
Figure 10. Exponential Static dv/dt versus
Gate−MT1 Resistance, MT2(−)
14 K
TJ = 100°C
12 K
GATE OPEN
GATE OPEN
STATIC dv/dt (V/ s)
STATIC dv/dt (V/ s)
8.0 K
6.0 K
110°C
4.0 K
0
10 K
RG−MT1, GATE−MT1 RESISTANCE (OHMS)
10 K
2.0 K
1000
RG−MT1, GATE−MT1 RESISTANCE (OHMS)
125°C
TJ = 100°C
10 K
8.0 K
110°C
6.0 K
125°C
4.0 K
2.0 K
0
400
500
600
700
800
400
500
600
700
VPK, PEAK VOLTAGE (VOLTS)
VPK, PEAK VOLTAGE (VOLTS)
Figure 11. Exponential Static dv/dt versus
Peak Voltage, MT2(+)
Figure 12. Exponential Static dv/dt versus
Peak Voltage, MT2(−)
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5
800
MAC4DCM, MAC4DCN
10 K
14 K
STATIC dv/dt (V/ s)
VPK = 400 V
6.0 K
600 V
4.0 K
800 V
2.0 K
GATE OPEN
VPK = 400 V
10 K
8.0 K
600 V
6.0 K
800 V
4.0 K
2.0 K
0
0
100
105
110
115
120
125
105
100
110
115
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Typical Exponential Static dv/dt
versus Junction Temperature, MT2(+)
Figure 14. Typical Exponential Static dv/dt
versus Junction Temperature, MT2(−)
100
dv/dt(c), CRITICAL RATE OF RISE OF
COMMUTATING VOLTAGE (V/ s)
VPK = 400 V
TJ = 125°C
75°C
100°C
10
f=
tw
1
2 tw
(di/dt)c =
VDRM
6f ITM
1000
1.0
0
5.0
10
15
20
25
30
35
di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 15. Critical Rate of Rise of
Commutating Voltage
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
CHARGE
1N4007
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON-POLAR
CL
TRIGGER CONTROL
STATIC dv/dt (V/ s)
12 K
GATE OPEN
8.0 K
−
+
200 V
MT2
1N914 51 G
MT1
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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6
125
MAC4DCM, MAC4DCN
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
MAC4DCM, MAC4DCN
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
STYLE 6:
PIN 1.
2.
3.
4.
T
MT1
MT2
GATE
MT2
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MAC4DCM/D
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