NCP1501 Dual Mode PWM/Linear Buck Converter The NCP1501 is a dual mode regulator that operates either as a PWM Buck Converter or as a Low Drop Out Linear Regulator. If a synchronization signal is present, the NCP1501 operates as a current mode PWM converter with synchronous rectification. The synchronization signal allows the user to control the location of the spurious frequency noise generated by a PWM converter. Linear mode is active when a synchronization signal is not present. The NCP1501 configuration allows an efficient high power operation and low noise during system sleep modes. http://onsemi.com MARKING DIAGRAM 8 Micro8 (MSOP−8) DM SUFFIX CASE 846A 8 Features • • • • • • • • • • • • • • Synchronous Rectification for Higher Efficiency in PWM Mode Linear Mode Operation for Low Noise Output at Low Loads Integrated MOSFETs and Feedback Circuits Cycle−by−Cycle Peak Current Limit of 800 mA (typ) Automatic Switching Between PWM and Linear Mode Operating Frequency Range of 500 to 1000 kHz Optimized for Ceramic Capacitors and Low Profile Inductors Thermal Limit Protection Built−in Slope Compensation for Current Mode PWM Converter Fixed Output Voltages of 1.05 V, 1.35 V, 1.57 V, 1.8 V Shutdown Current Consumption of 0.2 A Internal Soft Start Transistor Count: 3500 Pb−Free Package is Available Typical Applications • • • • • L 10 10 H COUT 1 1501= Device Code A = Assembly Location Y = Year W = Work Week PIN CONNECTIONS SHD 1 8 CB0 SYN 2 7 CB1 VO 3 6 GND LX 4 5 Vin (Top View) ORDERING INFORMATION Cellular Phones PDAs Pagers Supplies for DSP Cores Portable Applications Vout 1 1501 AYW Device NCP1501DMR2 NCP1501DMR2G 1 SHD CB0 8 2 SYN CB1 7 3 VO GND 6 4 LX Vin 5 Package Shipping† Micro8 4000/Tape & Reel Micro8 (Pb−Free) 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Vbat NCP1501 10 CIN Figure 1. Typical Applications Circuit Semiconductor Components Industries, LLC, 2004 March, 2004 − Rev. 7 1 Publication Order Number: NCP1501/D NCP1501 PIN FUNCTION DESCRIPTIONS Pin # Symbol Pin Description 1 SHD Enable Pin for the NCP1501. This pin is active high. Internal pull down resistor forces the part off if the pin is not connected on the board. 2 SYN External Synchronization Signal Pin. The device will operate in PWM mode if a clock signal is present. The pin must be pulled low to enter LDO mode. Internal pull down resistor on pin. 3 VO Feedback for the NCP1501. An internal MOSFET is connected across VO and LX for LDO mode. 4 LX Connection for the pass devices to the inductor. 5 Vin Input voltage to the NCP1501. 6 GND Ground Connection for the device. 7 CB1 Voltage Selection Bit. Internal pull up resistor on pin. 8 CB0 Voltage Selection Bit. Internal pull down resistor on pin. MAXIMUM RATINGS Rating Symbol Value Unit Maximum Voltage All Pins Vmax 5.5 V Maximum operating Voltage All Pins Vmax 5.2 V Thermal Resistance, Junction−to−Air RJA 240 °C/W TA −30 to +85 °C VESD > 2500 > 100 V Moisture Sensitivity MSL Level 1 Storage Temperature Range Tstg −55 to +150 °C Junction Operating Temperature Range TJ −30 to +125 °C Operating Ambient Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A ELECTRICAL CHARACTERISTICS (Vin = 3.6 V, VO = 1.57 V, TA = 25°C, Fsyn = 600 kHz 50% Duty Cycle square wave for PWM mode; TA = −30 to 85°C for Min/Max values, unless otherwise noted.) Symbol Min Typ Max Unit Quiescent Current of Switching Mode, Iout = 0 mA Iq PWM − 124 500 A Quiescent Current of LDO Mode, Iout = 0 mA Iq LDO − 32 65 A Iq Off − 0.2 1.0 A Vin 2.7 − 5.2 V Vsync −0.3 − VCC+0.3 V Characteristic VCC Pin Quiescent Current, SHD Low Input Voltage Range Sync Pin Input Voltage Frequency Operational Range Fsync 500 − 1000 kHz Minimum Synchronization Pulse Width Dcsync(min) − 30 − % Maximum Synchronization Pulse Width Dcsync(max) − 70 − % SYNC “H” Voltage Threshold Vsync(H) − 920 1200 mV SYNC “L” Voltage Threshold Vsync(L) 400 830 − mV SYNC “H” Input Current, Vsync = 3.6 V Isync(H) − 1.8 − A SYNC “L” Input Current, Vsync = 0 V Isync(L) −0.5 0.005 − A http://onsemi.com 2 NCP1501 ELECTRICAL CHARACTERISTICS (continued) (Vin = 3.6 V, VO = 1.57 V, TA = 25°C, Fsyn = 600 kHz 50% Duty Cycle square wave for PWM mode; TA = −30 to 85°C for Min/Max values, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit VCB −0.3 − VCC+0.3 V CB0,1 “H” Voltage Threshold VCB(H) − 910 1200 mV CB0,1 “L” Voltage Threshold VCB(L) 400 850 − mV CB0,1 “H” Input Current, CBx = 3.6 V ICB(H) − 1.8 − A CB0,1 “L” Input Current, CBx = 0 V ICB(L) −0.5 0 − A VSHD −0.3 − VCC+0.3 V SHD “H” Voltage Threshold VSHD(H) − 920 1200 mV SHD “L” Voltage Threshold VSHD(L) 400 850 − mV SHD “H” Input Current, SHD = 3.6 V ISHD(H) − 1.8 − A SHD “L” Input Current, SHD = 0 V ISHD(L) −0.5 0 − A Input Voltage Vfb −0.3 − VCC+0.3 V Input Current, Vfb = 1.8 V Ifb − 8.5 − A Switching P−FET Current Limit Ilim − 800 − mA Duty Cycle DC − − 100 % Minimum On Time Ton(min) − 100 − RDS(on) Switching N−FET P−FET RDS(on) Output Level Selection Pins Input Voltage Shutdown Pin Input Voltage Feedback Pin PWM Mode Characteristics Switching P−FET and N−FET Leakage Current Ileak nsec Ohms − − 0.7 0.6 − − − 0.01 10 A Output Over Voltage Threshold VO − 3.0 − % Output Voltage Accuracy, Vout(set) = 1.05 V CB0 = L, CB1 = L Output Voltage Accuracy, Vout(set) = 1.35 V CB0 = L, CB1 = H Output Voltage Accuracy, Vout(set) = 1.57 V CB0 = H, CB1 = H Output Voltage Accuracy, Vout(set) = 1.80 V CB0 = H CB1 = L Vout 1.018 1.309 1.523 1.740 1.050 1.350 1.570 1.800 1.082 1.391 1.617 1.860 V Load Transient Response, 10 to 100 mA Load Step Vout − 40 − mV Line Transient Response, Iout = 100 mA, 3.0 to 3.6 Vin Line Step Vout − ±5 − mVpp LDO Mode Characteristics RDS(on) LDO FET (Inductor Switch), LX to Vout Dropout Voltage (Limited by Vin(min) = 2.5 V and Vout(max) = 1.8 V) Output Voltage Accuracy, Vout(set) = 1.05 V CB0 = L, CB1 = L Output Voltage Accuracy, Vout(set) = 1.35 V CB0 = L, CB1 = H Output Voltage Accuracy, Vout(set) = 1.57 V CB0 = H, CB1 = H Output Voltage Accuracy, Vout(set) = 1.80 V CB0 = H CB1 = L RDS(on) − 7.0 − Ohms Vin − Vout − 0.7 − V Vout 1.018 1.309 1.523 1.740 1.050 1.350 1.570 1.800 1.082 1.391 1.617 1.860 V TSD − 160 − °C TSDhys − 25 − °C Thermal Shutdown Thermal Shutdown Hysteresis http://onsemi.com 3 NCP1501 SHD VCC Input Voltage Reference Out + − C1 ILimit PWM SYN Sync Detection and Timing Block S Q Mode Select + − + Slope Compensation Out LX R Q − + − PWM Comparator − SoftStart Thermal Shutdown Out L − + OVP Comparator Out Linear Control Block Vref + 5% VO C2 + − Error Amplifier Vref CB0 Output Voltage Program MUX CB1 Ground Component C1, C2 L Value Manufacturer 10 F, 6.3 V 10 H Output Voltage TDK, C2012X5R0J106M (0805 size) TDK, LLF4017−100 (Iout = 300 mA) Coilcraft, LPO4812−103MX (Iout = 300 mA) Coilcraft, 0805PS−103M (Iout = 150 mA) TDK, NLC252018T−100 (Iout = 100 mA) Figure 2. Typical Circuit with the Internal Schematic http://onsemi.com 4 NCP1501 DETAILED OPERATING DESCRIPTION has a pull down resistor to force the part into LDO mode when a clock signal is not present. To place the NCP1501 in LDO mode, the user must set the Synchronization pin low. The LDO mode guarantees an output in excess of 50 mA. Pins CB0 and CB1 control the output voltage selection. The four voltages are 1.05 V, 1.35 V, 1.57 V, 1.8 V. CB0 contains a pull down resistor and CB1 contains a pull up resistor internal to the NCP1501. The resistors force the output of the converter to 1.35 V if the pins are floating connections to the external circuit. The Shutdown Pin enables the operation of the device. The Shutdown Pin has an internal pull down resistor to force the NCP1501 into the off mode if this pin is floating due to the external circuit. During Startup, the NCP1501 has a soft start function to limit fast dV/dt and eliminate overshoot on the output. The Buck regulator is a synchronous rectifier PWM regulator with integrated MOSFETs. This regulator has an LDO function for low power modes to conserve power and lower ripple voltage associated with PFM mode. The NCP1501 does not contain an internal oscillator for the switching mode. The Dual PWM/LDO mode is an exclusive Patent Pending circuit. The PWM clock is generated via an external clock signal on the Synchronization pin. The operating frequency range for the PWM is 500 kHz to 1000 kHz. The output current of the PWM is typically 100 mA with a guarantee of over 300 mA for the 2.7 to 5.2 input voltage range. If a synchronization pulse is not present, the NCP1501 changes into the LDO mode. The LDO function assures the user of an extremely low output ripple voltage and greatly reduced quiescent current when the users system is in a sleep mode. Internally to the NCP1501, the Synchronization pin LX Vbat Cin 10 L1 10 H Q1 Vout Q3 Ilim FB EA DC/DC CONTROL Sync SHD CB0 CB1 Q2 LDO CONTROL Cout 10 Figure 3. Block Diagram and Circuit Schematic of the NCP1501 The output voltage accuracy in the PWM mode is well within 3% of the nominal set value. An over voltage protection circuit is present in the PWM mode to limit the positive voltage spike due to fast load transient conditions. The PWM also has the ability to go to 100% duty cycle for transient conditions and low input to output voltage differentials. In PWM mode, each switching cycle has a guaranteed on−time of 100 ns. The NCP1501 has two protection circuits that can eliminate the cycle. When tripped, the over voltage protection or the thermal shutdown overrides the gate drive of the high side MOSFET. The external components required are an input and an output 10 0F ceramic capacitor and a 10 H inductor. PWM Mode During normal operation, a synchronization pulse acts as the clock for the DC/DC controller. The rising edge of the clock pulls the gate of Q1 low allowing the inductor to charge. When the current through Q1 reaches either the current limit or feedback voltage reaches its limit, Q1 will turn off and Q2 will turn on. Q2 replaces the free wheeling diode typically associated with Buck Converters. Q2 will turn off when either a rising edge sync pulse is present or all the stored energy is depleted from the inductor. Q3 remains off during this mode. http://onsemi.com 5 NCP1501 L1 Load 10 H Q1 Sync Set R3 OCP Vbat R1 C1 10 En Ramp R2 S + − R Q En COMP I PFET Vref + 5% C2 10 Latch ERROR AMP + − − + Q2 R4 Vref OVP COMP Figure 4. PWM Circuit Schematic LDO Mode LDO Control Circuitry will turn on Q3 as a bypass circuit to the inductor. Q1 is the controlling pass device of the LDO that regulates the input to output voltage dropout. The LDO can source an output current in excess of 50 mA. When the synchronization pulse is not present, the NCP1501 operates as an LDO. The DC/DC Control Circuitry will relinquish control of Q1 and turn off Q2. The L1 Load 10 H Q1 Switch/Invert Sync Set Vbat In C1 10 En Ramp Q3 Out En ERROR AMP R3 C2 10 − + Vref Figure 5. LDO Circuit Schematic http://onsemi.com 6 R4 NCP1501 Internal CLK Signal Voltage Output Selection Vin The output voltage selection is accomplished via two external pins: CB0 and CB1. If CB0 and CB1 pins are left floating by the external circuit, the output voltage will default to 1.35 V. The corresponding voltages are as follows. 0 NCP1501 CB0 CB1 Vout (V) 0 0 1.05 0 1 1.35 1 1 1.57 1 0 1.80 External SYNC Signal 3.0 0 0 TIME 10 Figure 6. Transition Waveforms from LDO to PWM Mode Vin SHD 1.8 V 1.57 V 1.35 V 1.05 V VO CB0 CB1 Figure 7. Power Up and Power Down Sequence Thermal Shutdown PWM latch and the regulator control circuitry cannot be re−enabled until the die temperature drops by this amount. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended as a substitute for proper heatsinking. The NCP1501 is contained in the Micro−8 package. Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the PWM latch is reset and the linear regulator control circuitry is disabled. The thermal shutdown circuit is designed with 25°C of hysteresis. This means that the http://onsemi.com 7 NCP1501 3.6040 Vin 3.6000 3.5960 400 m IPFET 200 m 0.00 400 m IL 300 m 200 m 400 m INFET 100 m −200 m 1.573 VO 1.570 1.567 3.70 VLX 1.35 −1.00 198.0 201.0 204.0 207.0 TIME () Figure 8. Waveforms During Normal Operation http://onsemi.com 8 210.0 213.0 NCP1501 APPLICATIONS INFORMATION of 30% to 70%. The rising edge of the signal from the synchronization pin acts as the oscillator signal to set the latch and reset the ramp compensation signal. An Over Voltage Protection circuit ensures the output will respond properly to fast transients from large to small loads. The NCP1501 allows the PWM mode to enter a 100% duty cycle for fast load transient conditions and low input to output voltage differentials. The LDO mode is effective during low load conditions by lowering the quiescent current and reducing the output ripple voltage associated with PWM converters entering PFM mode. NCP1501 enters the LDO mode when a synchronization signal is not present. It is recommended to pull the synchronization signal low for LDO mode. NCP1501 is a dual mode PWM or LDO step down converter. This dual mode takes advantage of the best of each mode. There are three required external components: an input and output capacitor and an inductor. The PWM mode allows high efficiency for larger loads. A typical efficiency for an input of 3.6 V and an output of 1.8 V and 100 mA is over 90%. Low RDSon and synchronous rectification contained within the device contributes to the very high efficiency. As with other synchronous rectification devices, the NCP1501 does not require an external diode to supplement the NFET during switching on or off. A synchronization pin allows the user to define the frequency noise spikes of the PWM. The duty cycle of the synchronization signal must be within the range CB0 8 2 SYN CB1 7 3 VO GND 6 4 LX Vin 5 1 SHD Vout 10 H L 10 Cin, Cout: 10 F Ceramic, C2012X5R0J106M (TDK) L: 10 H, LLF4017−100 (TDK) Vbat NCP1501 Cout Cin 10 Figure 9. Typical Operating Schematic 2.5 2 1.8 2 1.6 ISYN (A) ISHD (A) 1.4 1.5 1 1.2 1 0.8 0.6 VCC = 3.6 V TA = 25°C 0.5 VCC = 3.6 V TA = 25°C 0.4 0.2 0 0 0 1 2 3 4 5 0 1 2 3 VSHD (V) VSYN (V) Figure 10. Input Current versus Voltage for the Shutdown Pin Figure 11. Input Current versus Voltage for the Synchronization Pin http://onsemi.com 9 4 NCP1501 2.5 8 7 2 6 IFB (A) ICB (A) 5 1.5 1 4 3 2 VCC = 3.6 V TA = 25°C PWM Mode 1 VCC = 3.6 V TA = 25°C 0.5 0 0 −1 0 1 2 3 4 0 0.5 1 1.5 2 VCB (V) VFB (V) Figure 12. Input Current versus Voltage for the CB Pins Figure 13. Input Current versus Voltage for the Feedback Pin 0.93 1.6 0.92 0.90 1.5 Vout (V) VCB(threshold) (V) 1.55 Vth High 0.91 0.89 TA = 25°C LDO Mode 0.88 VCC = 3.6 V TA = 25°C LDO Mode 1.45 1.4 0.87 0.86 1.35 0.85 Vth Low 0.84 2 1.3 3 4 5 6 0 0.2 0.4 0.6 0.8 1.0 1.2 VCC (V) VCB (V) Figure 14. VCC Input Voltage versus CB Threshold Figure 15. Transition Level of CB Pins 1.4 0.93 0.92 1.8 VSHD High 0.90 Vout (V) VCB(threshold) (V) 0.91 0.89 TA = 25°C LDO Mode 0.88 VSHD Decreasing VSHD Increasing 0.87 0.86 VSHD Low TA = 25°C LDO Mode 0 0.85 0.84 2 3 4 5 0 6 0.2 0.4 0.6 0.8 1.0 1.2 VCC (V) VCB (V) Figure 16. Input Voltage versus Shutdown Voltage Figure 17. Output Voltage versus Shutdown Pin Voltage http://onsemi.com 10 1.4 NCP1501 2.0 2.0 1.80 Vout 1.6 1.57 Vout 1.6 1.57 Vout 1.4 1.35 Vout 1.4 1.35 Vout 1.2 1.05 Vout 1.0 0.6 0.6 0.4 0.4 0.2 0.2 0 1 2 3 4 5 0 6 1.05 Vout 1.0 0.8 0 1 2 3 4 5 6 Vin (V) Vout (V) Figure 18. Output Voltage versus PWM Input Voltage Figure 19. Input Voltage versus Output Voltage 95 92 EFFICIENCY (%) 90 EFFICIENCY (%) 1.2 0.8 0 1.8 Vout 85 1.57 1.35 80 VCC = 3.6 V 1.05 Freq = 600 kHz TA = 25°C 75 91 1.80 Vout 90 1.57 Vout 89 1.35 Vout 88 87 86 1.05 Vout 85 Vin = 3.6 V Iout = 100 mA 84 See Figure 9 for Circuit 83 70 0 50 100 150 200 250 300 500 600 700 800 900 1000 Iout, OUTPUT CURRENT (mA) FREQUENCY (kHz) Figure 20. Efficiency versus Output Current Figure 21. Efficiency versus Frequency 1200 94 Vin = 3.6 V Vout = 1.8 V PWM Freq = 600 kHz 1000 LDO 92 EFFICIENCY (%) Iin, INPUT CURRENT (A) 1.80 Vout 1.8 Vin (V) Vout (V) 1.8 800 PWM 600 400 200 90 1.8 Vout 88 1.57 1.35 86 Iout = 100 mA Freq = 600 kHz TA = 25°C 84 1.05 82 0 0 200 400 600 800 1000 2.7 3.2 3.7 4.2 4.7 Iout, OUTPUT CURRENT (A) Vin, INPUT VOLTAGE (V) Figure 22. Input Current versus Output Current Comparison for PWM and LDO Mode Figure 23. Efficiency versus Input Voltage http://onsemi.com 11 5.2 NCP1501 SYNC SYNC Vout Vout Vin = 3.6 V Vin = 3.6 V Vout = 1.8 V Iout = 10 mA Vout = 1.8 V Iout = 10 mA LX LX Figure 24. Transition from LDO to PWM Mode Figure 25. Transition from PWM to LDO Mode Vout Vout Vin Vin Vout = 1.8 V Iout = 10 mA Freq = 600 kHz Vout = 1.8 V Iout = 10 mA Freq = 600 kHz Figure 26. Line Transient from 3.0 to 3.6 V Figure 27. Line Transient from 3.6 to 3.0 V Iout Vout Vin = 3.6 V Vout = 1.8 V Iout = 10 mA Freq = 600 kHz Vout Iout Vin = 3.6 V Vout = 1.8 V Iout = 10 mA Freq = 600 kHz Figure 28. Load Transient from 10 to 100 mA Figure 29. Load Transient from 100 to 10 mA http://onsemi.com 12 NCP1501 200 1.0 m 900 800 Vin = 3.6 V Vout = 1.57 V Load = 15 F = 600 kHz 805.4 V 700 Vin = 3.6 V Vout = 1.57 V Load = 15 F = 1.0 MHz 180 160 140 600 120 500 100 400 80 300 60 200 40 100 20 10 n 129.3 V 2.0 n Start 0 Hz 1.0 MHz Stop 10 MHz Start 0 Hz Figure 30. Vrms versus Frequency 800 Stop 10 MHz Figure 31. Vrms versus Frequency 200 1.0 m 900 1.0 MHz Vin = 3.6 V Vout = 1.57 V Load = 15 F = 600 kHz 854.3 nV Hz Vin = 3.6 V Vout = 1.57 V Load = 15 F = 1.0 MHz 180 160 700 140 600 120 500 100 400 80 300 60 200 40 100 20 130.3 nV Hz 2.0 n 10 n Start 0 Hz 1.0 MHz Stop 10 MHz Start 0 Hz Figure 32. Noise versus Frequency 1.0 MHz Stop 10 MHz Figure 33. VRMS versus Frequency http://onsemi.com 13 NCP1501 PACKAGE DIMENSIONS Micro8 (MSOP−8) DM SUFFIX CASE 846A−02 ISSUE F −A− −B− K PIN 1 ID NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. G D 8 PL 0.08 (0.003) M T B S A DIM A B C D G H J K L S SEATING −T− PLANE 0.038 (0.0015) C L J H MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 −−− 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 −−− 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm inches Micro8 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 14 For additional information, please contact your local Sales Representative. NCP1501/D