ON MC74ACT373DTG Octal transparent latch with 3−state output Datasheet

MC74AC373, MC74ACT373
Octal Transparent Latch
with 3−State Outputs
The MC74AC373/74ACT373 consists of eight latches with 3−state
outputs for bus organized system applications. The flip−flops appear
transparent to the data when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup time is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
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Features
•
•
•
•
•
PDIP−20
N SUFFIX
CASE 738
Eight Latches in a Single Package
3−State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
′ACT373 Has TTL Compatible Inputs
Pb−Free Packages are Available
1
VCC
O7
D7
D6
O6
O5
D5
D4
O4
LE
20
19
18
17
16
15
14
13
12
11
SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
2
3
4
5
6
7
8
9
10
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1
Figure 1. Pinout: 20−Lead Packages Conductors
SOEIAJ−20
M SUFFIX
CASE 967
(Top View)
1
PIN ASSIGNMENT
PIN
FUNCTION
D0−D7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O0−O7
3−State Latch Outputs
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
D0 D1 D2 D3 D4 D5 D6 D7
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC74AC373/D
MC74AC373, MC74ACT373
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight D−type
latches with 3−state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2−state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
H
L
L
L
X
H
H
L
X
L
H
X
Z
L
H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
D0
D1
D
D2
D
G
O
D3
D
G
O
D4
D
G
O
D5
D
G
O
D6
D
G
O
D7
D
G
O
D
G
O
LE
OE
NOTE:
This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
G
O
MC74AC373, MC74ACT373
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
−65 to +150
°C
IIN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
tr, tf
Parameter
Supply Voltage
Min
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−
−
140
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
Unit
V
V
ns/V
ns/V
°C
TA
Operating Ambient Temperature Range
−40
25
85
°C
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC373, MC74ACT373
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to +85°C
Typ
VIH
VIL
VOH
VOL
Unit
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
Maximum Low Level
Output Voltage
IOUT = −50 mA
V
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 mA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
IOZ
Maximum
3−State
Current
5.5
−
±0.5
±5.0
mA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V
Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
mA
VIN = VCC or GND
IOLD
†Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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4
MC74AC373, MC74ACT373
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
Symbol
Parameter
VCC*
(V)
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Dn to On
3.3
5.0
1.5
1.5
10
7.0
13.5
9.5
1.5
1.5
15
10.5
ns
3−5
tPHL
Propagation Delay
Dn to On
3.3
5.0
1.5
1.5
9.5
7.0
13
9.5
1.5
1.5
14.5
10.5
ns
3−5
tPLH
Propagation Delay
LE to On
3.3
5.0
1.5
1.5
10
7.5
13.5
9.5
1.5
1.5
15
10.5
ns
3−6
tPHL
Propagation Delay
LE to On
3.3
5.0
1.5
1.5
9.5
7.0
12.5
9.5
1.5
1.5
14
10.5
ns
3−6
tPZH
Output Enable Time
3.3
5.0
1.5
1.5
9.0
7.0
11.5
8.5
1.0
1.0
13
9.5
ns
3−7
tPZL
Output Enable Time
3.3
5.0
1.5
1.5
8.5
6.5
11.5
8.5
1.0
1.0
13
9.5
ns
3−8
tPHZ
Output Disable Time
3.3
5.0
1.5
1.5
10
8.0
12.5
11
1.0
1.0
14.5
12.5
ns
3−7
tPLZ
Output Disable Time
3.3
5.0
1.5
1.5
8.0
6.5
11.5
8.5
1.0
1.0
12.5
10
ns
3−8
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to LE
3.3
5.0
3.5
2.0
5.5
4.0
6.0
4.5
ns
3−9
th
Hold Time, HIGH or LOW
Dn to LE
3.3
5.0
−3.0
−1.5
1.0
1.0
1.0
1.0
ns
3−9
tw
LE Pulse Width, HIGH
3.3
5.0
4.0
2.0
5.5
4.0
6.0
4.5
ns
3−6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC373, MC74ACT373
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to +85°C
Typ
Unit
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
Maximum
3-State
Current
5.5
−
±0.5
±5.0
mA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
mA
VIN = VCC or GND
VOL
IIN
DICCT
IOZ
IOLD
IOHD
ICC
Maximum Low Level
Output Voltage
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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6
V
V
IOUT = −50 mA
*VIN = VIL or VIH
IOH −24 mA
−24 mA
IOUT = 50 mA
MC74AC373, MC74ACT373
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
Symbol
Parameter
VCC*
(V)
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Dn to On
5.0
2.5
8.5
10
1.5
11.5
ns
3−5
tPHL
Propagation Delay
Dn to On
5.0
2.0
8.0
10
1.5
11.5
ns
3−5
tPLH
Propagation Delay
LE to On
5.0
2.5
8.5
11
2.0
11.5
ns
3−6
tPHL
Propagation Delay
LE to On
5.0
2.0
8.0
10
1.5
11.5
ns
3−6
tPZH
Output Enable Time
5.0
2.0
8.0
9.5
1.5
10.5
ns
3−7
tPZL
Output Enable Time
5.0
2.0
7.5
9.0
1.5
10.5
ns
3−8
tPHZ
Output Disable Time
5.0
2.5
9.0
11
2.5
12.5
ns
3−7
5.0
1.5
7.5
8.5
1.0
10
ns
3−8
tPLZ
Output Disable Time
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
Symbol
Parameter
VCC*
(V)
Typ
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to LE
5.0
3.0
7.0
8.0
ns
3−9
th
Hold Time, HIGH or LOW
Dn to LE
5.0
0
0
1.0
ns
3−9
5.0
2.0
7.0
8.0
ns
3−6
tw
LE Pulse Width, HIGH
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
pF
VCC = 5.0 V
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7
MC74AC373, MC74ACT373
ORDERING INFORMATION
Device
Package
MC74AC373N
PDIP−20
MC74AC373NG
PDIP−20
(Pb−Free)
MC74ACT373N
PDIP−20
MC74ACT373NG
PDIP−20
(Pb−Free)
MC74AC373DW
SOIC−20
MC74AC373DWG
SOIC−20
(Pb−Free)
MC74AC373DWR2
SOIC−20
MC74AC373DWR2G
SOIC−20
(Pb−Free)
MC74ACT373DW
SOIC−20
MC74ACT373DWG
SOIC−20
(Pb−Free)
MC74ACT373DWR2
SOIC−20
MC74ACT373DWR2G
SOIC−20
(Pb−Free)
MC74AC373DT
TSSOP−20*
MC74AC373DTG
TSSOP−20*
MC74AC373DTR2
TSSOP−20*
MC74AC373DTR2G
TSSOP−20*
MC74ACT373DT
TSSOP−20*
MC74ACT373DTG
TSSOP−20*
MC74ACT373DTR2
TSSOP−20*
MC74ACT373DTR2G
TSSOP−20*
MC74AC373MEL
SOEIAJ−20
MC74AC373MELG
SOEIAJ−20
(Pb−Free)
MC74ACT373MEL
SOEIAJ−20
MC74ACT373MELG
SOEIAJ−20
(Pb−Free)
Shipping †
18 Units / Rail
38 Units / Rail
1000 / Tape & Reel
38 Units / Rail
1000 / Tape & Reel
75 Units / Rail
2500 / Tape & Reel
75 Units / Rail
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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8
MC74AC373, MC74ACT373
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
20
20
20
20
AC
373
ALYWG
G
AC373
AWLYYWWG
MC74AC373N
AWLYYWWG
SOEIAJ−20
1
74AC373
AWLYWWG
1
1
1
20
20
20
20
ACT
373
ALYWG
G
ACT373
AWLYYWWG
MC74ACT373N
AWLYYWWG
1
1
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
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9
74ACT373
AWLYWWG
1
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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10
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
6.40
6.60
0.252
0.260
B
4.30
4.50
0.169
0.177
−−−
−−− 0.047
C
1.20
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
−W−
H
0.27
0.37
0.011
0.015
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
MC74AC373, MC74ACT373
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
20
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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12
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