Hitachi HM51S4270DLJ-7 262,144-word x 16-bit dynamic ram Datasheet

HM514170D, HM514270D Series
HM51S4170D, HM51S4270D Series
262,144-word × 16-bit Dynamic RAM
ADE-203-672 (Z)
Preliminary
Rev. 0.0
Oct. 18, 1996
Description
The Hitachi HM51(S)4170D, HM51(S)4270D Series are CMOS dynamic RAM organized as 262,144-word ×
16-bit. HM51(S)4170D, HM51(S)4270D Series have realized higher density, higher performance and various
functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies.
The HM51(S)4170D, HM51(S)4270D Series offer fast page mode as a high speed access mode. They have
the package variations of standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII.
Internal refresh timer enables HM51S4170D, HM51S4270D Series self refresh operation.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 60 ns/70 ns/80 ns (max)
• Low power dissipation
 Active mode: 825 mW/660 mW/578 mW (max) (HM51(S)4170D Series)
825 mW/770 mW/688 mW (max) (HM51(S)4270D Series)
 Standby mode: 11 mW (max)
1.1 mW (max) (L-version)
• Fast page mode capability
• Refresh cycles
 1024 refresh cycles: 16 ms (HM51(S)4170D Series)
128 ms (L-version) (HM51(S)4170DL Series)
 512 refresh cycles: 8 ms (HM51(S)4270D Series)
128 ms (L-version) (HM51(S)4270DL Series)
• 2 variations of refresh
 RAS-only refresh
 CAS-before-RAS refresh
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
HM51(S)4170D Series, HM51(S)4270D Series
• 2 WE-byte control
• Self refresh operation (HM51S4170D, HM51S4270D)
• Battery backup operation (L-version)
Ordering Information
Type No.
Access time
Package
HM514170DJ-6
HM514170DJ-7
HM514170DJ-8
60 ns
70 ns
80 ns
400-mil 40-pin plastic SOJ (CP-40D)
HM514170DLJ-6
HM514170DLJ-7
HM514170DLJ-8
60 ns
70 ns
80 ns
HM514270DJ-6
HM514270DJ-7
HM514270DJ-8
60 ns
70 ns
80 ns
HM514270DLJ-6
HM514270DLJ-7
HM514270DLJ-8
60 ns
70 ns
80 ns
HM51S4170DJ-6
HM51S4170DJ-7
HM51S4170DJ-8
60 ns
70 ns
80 ns
HM51S4170DLJ-6
HM51S4170DLJ-7
HM51S4170DLJ-8
60 ns
70 ns
80 ns
HM51S4270DJ-6
HM51S4270DJ-7
HM51S4270DJ-8
60 ns
70 ns
80 ns
HM51S4270DLJ-6
HM51S4270DLJ-7
HM51S4270DLJ-8
60 ns
70 ns
80 ns
HM514170DTT-6
HM514170DTT-7
HM514170DTT-8
60 ns
70 ns
80 ns
HM514170DLTT-6
HM514170DLTT-7
HM514170DLTT-8
60 ns
70 ns
80 ns
HM514270DTT-6
HM514270DTT-7
HM514270DTT-8
60 ns
70 ns
80 ns
HM514270DLTT-6
HM514270DLTT-7
HM514270DLTT-8
60 ns
70 ns
80 ns
2
400 mil 44-pin plastic TSOP II (TTP-44/40DB)
HM51(S)4170D Series, HM51(S)4270D Series
Ordering Information (cont)
Type No.
Access time
Package
HM51S4170DTT-6
HM51S4170DTT-7
HM51S4170DTT-8
60 ns
70 ns
80 ns
400 mil 44-pin plastic TSOP II (TTP-44/40DB)
HM51S4170DLTT-6
HM51S4170DLTT-7
HM51S4170DLTT-8
60 ns
70 ns
80 ns
HM51S4270DTT-6
HM51S4270DTT-7
HM51S4270DTT-8
60 ns
70 ns
80 ns
HM51S4270DLTT-6
HM51S4270DLTT-7
HM51S4270DLTT-8
60 ns
70 ns
80 ns
3
HM51(S)4170D Series, HM51(S)4270D Series
Pin Arrangement
HM514170DJ/DLJ Series
HM51S4170DJ/DLJ Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
LWE
UWE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
(Top view)
HM514170DTT/DLTT Series
HM51S4170DTT/DLTT Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
LWE
UWE
RAS
A9
A0
A1
A2
A3
VCC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
(Top view)
Pin Description
Pin name
Function
A0 to A9
Address input
— Refresh address A0 to A9
— Row address
A0 to A9
— Column address A0 to A7
I/O0 to I/O15 Data input/output
RAS
Row address strobe
CAS
Column address strobe
UWE / LWE
Read/write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
4
HM51(S)4170D Series, HM51(S)4270D Series
Pin Arrangement
HM514270DJ/DLJ Series
HM51S4270DJ/DLJ Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
LWE
UWE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
(Top view)
HM514270DTT/DLTT Series
HM51S4270DTT/DLTT Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
LWE
UWE
RAS
NC
A0
A1
A2
A3
VCC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
(Top view)
Pin Description
Pin name
Function
A0 to A8
Address input
— Refresh address A0 to A8
— Row address
A0 to A8
— Column address A0 to A8
I/O0 to I/O15 Data input/output
RAS
Row address strobe
CAS
Column address strobe
UWE / LWE
Read/write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
5
HM51(S)4170D Series, HM51(S)4270D Series
Block Diagram
I/O4
I/O4
buffer
I/O3
I/O2
I/O1
I/O0
I/O15
I/O14
I/O13
I/O12
I/O3
buffer
I/O2
buffer
I/O1
buffer
I/O0
buffer
I/O15
buffer
I/O14
buffer
I/O13
buffer
I/O12
buffer
I/O11
buffer
I/O11
I/O5
I/O5
buffer
I/O6
I/O6
buffer
I/O9
buffer
I/O9
I/O7
I/O7
buffer
I/O8
buffer
I/O8
Row Row
driver driver
256 k memory array mat
I/O bus & column decoder
Row
driver
256 k memory array mat
Row
driver
Selector
256 k memory array mat
256 k memory array mat
I/O bus & column decoder
256 k memory array mat
Row Row
driver driver
Row
driver
Selector
I/O bus & column decoder
256 k memory array mat
Selector
256 k memory array mat
I/O bus & column decoder
256 k memory array Mat
Selector
I/O10 I/O10
buffer
Row
driver
CAS
UWE
RAS
Row decoder & Peripheral circuit
LWE
256 k memory array mat
I/O bus & column decoder
Row
driver
Column address buffer
CA0 to CA7: HM51(S)4170D
CA0 to CA8: HM51(S)4270D
Address A0 to A9: HM51(S)4170D
Address A0 to A8: HM51(S)4270D
6
256 k memory array mat
256 k memory array mat
Row address buffer
RA0 to RA9: HM51(S)4170D
RA0 to RA8: HM51(S)4270D
Row Row
driver driver
256 k memory array mat
Row
driver
I/O bus & column decoder
Row
driver
I/O bus & column decoder
256 k memory array mat
I/O bus & column decoder
256 k memory array mat
256 k memory array mat
Row Row
driver driver
Row
driver
256 k memory array mat
OE
HM51(S)4170D Series, HM51(S)4270D Series
Operation Mode
The HM51(S)4170D, HM51(S)4270D series has the following 11 operation modes.
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5. RAS-only refresh cycle
6. CAS-before-RAS refresh cycle
7. Self refresh cycle (HM51S4170D, HM51S4270D)
8. Fast page mode read cycle
9. Fast page mode early write cycle
10. Fast page mode delayed write cycle
11. Fast page mode read-modify-write cycle
Inputs
RAS
CAS
UWE
LWE
Output
Operation
H
H
D
D
Open
Standby
H
L
H
H
Valid
Standby
L
L
H
L
L
H
L*
2
2
Valid
Read cycle
L*
2
Open
Early write cycle
L*
2
Undefined
Delayed write cycle
L
L
L*
L
L
H to L
H to L
Valid
Read-modify-write cycle
L
H
D
D
Open
RAS-only refresh cycle
H to L
L
D
D
Open
CAS-before-RAS refresh cycle
Self refresh cycle
L
H to L
H
L
H to L
H
L*
2
2
L
H to L
L*
L
H to L
H to L
Valid
Fast page mode read cycle
L*
2
Open
Fast page mode early write cycle
L*
2
Undefined
Fast page mode delayed write cycle
Valid
Fast page mode read modify-write cycle
H to L
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t WCS ≥ 0 ns Early write cycle
t WCS < 0 ns Delay write cycle
3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of UWE
and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However write
OPERATION and output High-Z control are done independently by each UWE, LWE.
7
HM51(S)4170D Series, HM51(S)4270D Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V SS
VT
–1.0 to +7.0
V
Supply voltage relative to VSS
VCC
–1.0 to +7.0
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature range
Topr
0 to +70
°C
Storage temperature range
Tstg
–55 to +125
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage
VSS
0
0
0
V
2
VCC
4.5
5.0
5.5
V
1, 2
Input high voltage
VIH
2.4
—
6.5
V
1
Input low voltage
VIL
–1.0
—
0.8
V
1
Notes: 1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
8
HM51(S)4170D Series, HM51(S)4270D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*5 (HM51(S)4170D Series)
HM514170D, HM51S4170D
-6
Parameter
1,
Operating current* *
2
Standby current
-7
-8
Symbol
Min
Max Min
Max Min
Max Unit Test conditions
I CC1
—
135
—
120
—
105
mA RAS, CAS cycling, t RC = min
I CC2
—
2
—
2
—
2
mA TTL interface, RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA CMOS interface
RAS, CAS, UWE, LWE, OE
≥ V CC – 0.2 V
Dout = High-Z
Standby current
(L-version)
I CC2
—
200
—
200
—
200
µA
RAS-only refresh current*2
I CC3
—
135
—
120
—
100
mA t RC = min
CAS-before-RAS refresh I CC6
current* 2
—
135
—
120
—
100
mA t RC = min
Fast page mode current*1, *3
I CC7
—
150
—
120
—
100
mA t PC = min
I CC10
—
300
—
300
—
300
µA
Self-refresh mode current I CC11
(HM51S4170D)
—
1
—
1
—
1
mA CMOS interface
RAS, CAS ≤ 0.2 V,
Dout = High-Z
Self-refresh mode current I CC11
(HM51S4170DL)
—
200
—
200
—
200
µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
I LI
–10
10
–10
10
–10
10
µA
0 V ≤ Vin ≤ 6.5 V
Output leakage current
I LO
–10
10
–10
10
–10
10
µA
0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage
VOH
2.4
VCC
2.4
VCC
2.4
VCC
V
High Iout = –5.0 mA
Output low voltage
VOL
0
0.4
0
0.4
0
0.4
V
Low Iout = 4.2 mA
4
Battery backup current*
(Standby with CBR
refresh) (L-version)
CMOS interface
RAS, CAS, OE, UWE,
LWE ≥ V CC – 0.2 V
Dout = High-Z
Standby: CMOS interface
Dout = High-Z
CBR refresh: tRC = 125 µs
t RAS ≤ 1 µs, CAS = VIL
LWE, UWE, OE = VIH
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ V CC – 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL.
5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with
the same voltage.
9
HM51(S)4170D Series, HM51(S)4270D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*5 (HM51(S)4270D Series)
HM514270D, HM51S4270D
-6
Parameter
1,
Operating current* *
2
Standby current
-7
-8
Symbol
Min
Max Min
Max Min
Max Unit Test conditions
I CC1
—
150
—
140
—
125
mA RAS, CAS cycling, t RC = min
I CC2
—
2
—
2
—
2
mA TTL interface, RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA CMOS interface
RAS, CAS, UWE, LWE, OE
≥ V CC – 0.2 V
Dout = High-Z
Standby current
(L-version)
I CC2
—
200
—
200
—
200
µA
RAS-only refresh current*2
I CC3
—
140
—
130
—
110
mA t RC = min
CAS-before-RAS refresh I CC6
current* 2
—
140
—
130
—
110
mA t RC = min
Fast page mode current*1, *3
I CC7
—
150
—
130
—
120
mA t PC = min
I CC10
—
300
—
300
—
300
µA
Self-refresh mode current I CC11
(HM51S4270D)
—
1
—
1
—
1
mA CMOS interface
RAS, CAS ≤ 0.2 V,
Dout = High-Z
Self-refresh mode current I CC11
(HM51S4270DL)
—
200
—
200
—
200
µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
I LI
–10
10
–10
10
–10
10
µA
0 V ≤ Vin ≤ 6.5 V
Output leakage current
I LO
–10
10
–10
10
–10
10
µA
0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage
VOH
2.4
VCC
2.4
VCC
2.4
VCC
V
High Iout = –5.0 mA
Output low voltage
VOL
0
0.4
0
0.4
0
0.4
V
Low Iout = 4.2 mA
4
Battery backup current*
(Standby with CBR
refresh) (L-version)
CMOS interface
RAS, CAS, OE, UWE,
LWE ≥ V CC – 0.2 V
Dout = High-Z
Standby: CMOS interface
Dout = High-Z
CBR refresh: tRC = 250 µs
t RAS ≤ 1 µs, CAS = VIL
LWE, UWE, OE = VIH
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ V CC – 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL.
5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with
the same voltage.
10
HM51(S)4170D Series, HM51(S)4270D Series
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
7
pF
1
Output capacitance (Data-in, Data-out)
CI/O
—
10
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *14, *15, *17, *18
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.4 V
Input levels: 0 V, 3 V
Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
11
HM51(S)4170D Series, HM51(S)4270D Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Random read or write cycle time
t RC
110
—
130
—
150
—
ns
RAS precharge time
t RP
40
—
50
—
60
—
ns
RAS pulse width
t RAS
60
10000
70
10000
80
10000
ns
CAS pulse width
t CAS
15
10000
20
10000
20
10000
ns
Row address setup time
t ASR
0
—
0
—
0
—
ns
Row address hold time
t RAH
10
—
10
—
10
—
ns
Column address setup time
t ASC
0
—
0
—
0
—
ns
Column address hold time
t CAH
15
—
15
—
15
—
ns
RAS to CAS delay time
t RCD
20
45
20
50
20
60
ns
8
RAS to column address delay time
t RAD
15
30
15
35
15
40
ns
9
RAS hold time
t RSH
15
—
20
—
20
—
ns
CAS hold time
t CSH
60
—
70
—
80
—
ns
CAS to RAS precharge time
t CRP
10
—
15
—
15
—
ns
OE to Din delay time
t ODD
15
—
20
—
20
—
ns
OE delay time from Din
t DZO
0
—
0
—
0
—
ns
CAS setup time from Din
t DZC
0
—
0
—
0
—
ns
Transition time (rise and fall)
tT
3
50
3
50
3
50
ns
12
Notes
22
7
HM51(S)4170D Series, HM51(S)4270D Series
Read Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
60
—
70
—
80
ns
2, 3
Access time from CAS
t CAC
—
15
—
20
—
20
ns
3, 4, 13
Access time from address
t AA
—
30
—
35
—
40
ns
3, 5, 13
Access time from OE
t OAC
—
15
—
20
—
20
ns
3, 22
Read command setup time
t RCS
0
—
0
—
0
—
ns
20
Read command hold time to CAS
t RCH
0
—
0
—
0
—
ns
16, 19
Read command hold time to RAS
t RRH
0
—
0
—
0
—
ns
16, 19
Column address to RAS lead time
t RAL
30
—
35
—
40
—
ns
Output buffer turn-off time
t OFF1
0
15
0
15
0
15
ns
6
Output buffer turn-off to OE
t OFF2
0
15
0
15
0
15
ns
6
CAS to Din delay time
t CDD
15
—
15
—
15
—
ns
Write Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write command setup time
t WCS
0
—
0
—
0
—
ns
10, 19
Write command hold time
t WCH
15
—
15
—
15
—
ns
20
Write command pulse width
t WP
10
—
10
—
10
—
ns
21
Write command to RAS lead time
t RWL
15
—
20
—
20
—
ns
21
Write command to CAS lead time
t CWL
15
—
20
—
20
—
ns
21
Data-in setup time
t DS
0
—
0
—
0
—
ns
11, 21
Data-in hold time
t DH
15
—
15
—
15
—
ns
11, 21
CAS to OE delay time
t COD
—
0
—
0
—
0
ns
22
13
HM51(S)4170D Series, HM51(S)4270D Series
Read-Modify-Write Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read-modify-write cycle time
t RWC
150
—
180
—
200
—
ns
RAS to WE delay time
t RWD
80
—
95
—
105
—
ns
10,19
CAS to WE delay time
t CWD
35
—
45
—
45
—
ns
10,19
Column address to WE delay time
t AWD
50
—
60
—
65
—
ns
10, 19
OE hold time from WE
t OEH
15
—
20
—
20
—
ns
21
Refresh Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
Parameter
Symbol
-7
-8
Min
Max
Min
Max
Min
Max
Unit
Notes
CAS setup time (CBR refresh cycle) t CSR
10
—
10
—
10
—
ns
19
CAS hold time (CBR refresh cycle)
t CHR
10
—
10
—
10
—
ns
20
RAS precharge to CAS hold time
t RPC
10
—
10
—
10
—
ns
19
CAS precharge time in normal mode t CPN
10
—
10
—
10
—
ns
Fast Page Mode Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
-7
-8
Parameter
Symbol Min Max
Min Max
Min Max
Unit Notes
Fast page mode cycle time
t PC
40
—
45
—
50
—
ns
Fast page mode CAS precharge time
t CP
10
—
10
—
10
—
ns
Fast page mode RAS pulse width
t RASC
—
100000 —
100000 —
100000 ns
12
Access time from CAS precharge
t ACP
—
35
—
40
—
45
ns
3, 13
RAS hold time from CAS precharge
t RHCP
35
—
40
—
45
—
ns
14
HM51(S)4170D Series, HM51(S)4270D Series
Fast Page Mode Read-Modify-Write Cycle
HM514170D, HM51S4170D
HM514270D, HM51S4270D
-6
Parameter
Symbol
-7
-8
Min
Max
Min
Max
Min
Max
Unit
Notes
CAS precharge to UWE, LWE delay t CPW
time
55
—
65
—
70
—
ns
21
Fast page mode read-modify-write
cycle time
80
—
95
—
100
—
ns
t PCM
Refresh (HM51(S)4170D Series)
Parameter
Symbol
Max
Unit
Notes
Refresh period
t REF
16
ms
1024 cycles
Refresh period (L-version)
t REF
128
ms
1024 cycles
Parameter
Symbol
Max
Unit
Notes
Refresh period
t REF
8
ms
512 cycles
Refresh period (L-version)
t REF
128
ms
512 cycles
Refresh (HM51(S)4270D Series)
Self Refresh Mode
HM51S4170D, HM51S4270D
-6
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
RAS pulse width (self refresh)
t RASS
100
—
100
—
100
—
µs
23, 24,
25, 26
RAS precharge time (self refresh)
t RPS
110
—
130
—
150
—
ns
CAS hold time (self refresh)
t CHS
–50
—
–50
—
–50
—
ns
15
HM51(S)4170D Series, HM51(S)4270D Series
Notes: 1. AC measurements assume t T = 5 ns. VIH = 3.0 V, VIL = 0.0 V.
2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V IH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC .
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA .
10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥
t CWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge
in a delayed write or a read-modify-write cycle.
12. t RASC defines RAS pulse width in fast page mode cycles.
13. Access time is determined by the longest among tAA, t CAC and t ACP.
14. After power up pause for 100 µs, then DRAM initialization requires a minimum of eight RAS-only
refresh or eight CAS-before-RAS refresh cycles. If the user will implement CAS-before-RAS timing
in their system, then the eight initialization cycles MUST be CAS-before-RAS cycles.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
16. Either t RCH or tRRH must be satisfied for a read cycle.
17. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
18. A word of data can be written only when UWE and LWE go low at the same time. This implies that
early write cycles cannot be combined with delayed write cycles in the same cycles because all
data is latched at the fall of the first WE. In other words, staggering the WE signals in one cycle is
not permitted.
19. t RCH, t RRH, t WCS , t RWD, t CWD and t AWD are determined by the earlier falling edge of UWE and LWE.
20. t WCH and t RCS are determined by the later rising edge of UWE or LWE.
21. t WP, t RWL, t CWL, t OEH, t DS, t DH and tCPW should be satisfied by both UWE and LWE.
22. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH (min)/VIL (max) level.
23. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. If t RASS > 100 µs, then RAS precharge time
should use t RPS instead of tRP.
24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering into
self refresh mode.
16
HM51(S)4170D Series, HM51(S)4270D Series
25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 or 512
cycles (1024 cycles: HM51S4170D Series, 512 cycles: HM51S4270D Series) of distributed CBR
refresh with 15.6 µs interval should be executed within 16 or 8 ms (16 ms: HM51S4270D Series,
8 ms: HM51S4270D Series) immediately after exiting from and before entering into the self refresh
mode.
26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
27. XXX: H or L (H: V IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V IH or VIL.
17
HM51(S)4170D Series, HM51(S)4270D Series
Notes concerning 2WE control
Please do not separate the UWE/LWE operation timing intentionally. However skew between UWE/LWE
are allowed under the following conditions.
(1) Each of the UWE/LWE should satisfy the timing specifications individually.
(2) Different operation mode for upper/lower byte is not allowed; such as following.
RAS
CAS
Delayed write
LWE
Early write
UWE
(3) Closely separated upper/lower byte control is not allowed, unless the condition (tCP ≤ tUL) is satisfied.
RAS
LWE
UWE
t UL
18
HM51(S)4170D Series, HM51(S)4270D Series
Timing Waveforms *27
Read Cycle
t RC
t RAS
RAS
tT
t RP
t RSH
t CRP
t CAS
t RCD
t CSH
CAS
t ASR
t RAD
t RAL
t CAH
t RAH t ASC
Address
Column
Row
t RCH
t RCS
UWE
t RRH
LWE
t CAC
t OFF1
t AA
High-Z
Dout
Dout
t RAC
t DZC
Din
t OFF2
t OAC
t CDD
High-Z
t ODD
t DZO
OE
19
HM51(S)4170D Series, HM51(S)4270D Series
Early Write Cycle
t RC
t RAS
t RP
RAS
tT
t RSH
t RCD
t CAS
t CSH
CAS
t ASR
t RAH
Address
t ASC
Row
t CAH
Column
t WCH
t WCS
UWE
LWE
t DS
Din
Dout
20
t DH
Din
High-Z
t CRP
HM51(S)4170D Series, HM51(S)4270D Series
Delayed Write Cycle
t RC
t RAS
t RP
RAS
t CSH
t CRP
tT
t RCD
t RSH
t CAS
CAS
t RAH
Address
t CWL
t RWL
t ASC
t ASR
t CAH
Column
Row
t RCS
t WP
UWE
LWE
t DH
#*
t DS
Din
Din
t OEH
t DZC
t ODD
t DZO
Dout
High-Z
*Invalid Dout
t COD
t OFF2
OE
* Do not enable Dout during delayed write cycle.
21
HM51(S)4170D Series, HM51(S)4270D Series
Read-Modify-Write Cycle
t RWC
tT
t RP
RAS
t CRP
t RCD
CAS
t RAD
t ASR
t ASC
t RAH
Address
t CAH
Column
Row
t CWL
t RCS
t CWD
t RWL
t AWD
t WP
UWE
t AA
LWE
t RWD
t CAC
t RAC
t DS
t DZC
High-Z
Din
High-Z
Din
Dout
Dout
t DH
t OAC
t OFF2
t DZO
OE
22
t ODD
t OEH
HM51(S)4170D Series, HM51(S)4270D Series
RAS-Only Refresh Cycle
t RC
t RP
t RAS
RAS
tT
t CRP
t CRP
t RPC
CAS
t RAH
t ASR
Address
Dout
Row
High-Z
23
HM51(S)4170D Series, HM51(S)4270D Series
CAS-Before-RAS Refresh Cycle
t RC
t RP
t RC
t RAS *
t RP
t RAS *
t RP
RAS
tT
,
,
t RPC
t CPN
t CSR
t RPC
t CHR
t CPN
t CRP
t CSR
t CHR
)"
CAS
Address
t OFF1
Dout
High-Z
> tRAS (max).
* Do not extend tRAS _
Untested self refresh mode may be
activated and loss of data may be
resulted (HM514270D, HM514270D)
24
HM51(S)4170D Series, HM51(S)4270D Series
Fast Page Mode Read Cycle
t RASC
t RP
t RHCP
RAS
tT
t CAS
t RCD
t CRP
t RSH
t PC
t CSH
t CP
t CAS
t CAS
t CP
CAS
t RAD
t ASR
Address
t CAH
t RAH t ASC
Row
t ASC
t ASC
t CAH
Column
Column
Column
t RRH
t RCS
t RCS
t RCH
t RCH
t RCS
t RAL
t CAH
t RCH
UWE
LWE
t CDD
t DZC
Din
t DZC
High-Z
High-Z
t ODD
t CAC
t CAC
t AA
t RAC
High-Z
t CAC
t AA
t ACP
t ACP
t OFF1
Dout
t DZO
High-Z
t AA
t OFF1
Dout
t CDD
t CDD
t DZC
t OFF1
t DZO
Dout
t OAC
t ODD
Dout
t ODD
t DZO
t OFF2
t OFF2
t OAC
t OFF2
OE
t OAC
25
HM51(S)4170D Series, HM51(S)4270D Series
Fast Page Mode Early Write Cycle
t RASC
t RP
RAS
t CSH
tT
t CAS
t RCD
t RSH
t PC
t CP
t CAS
t CP
t CAS
CAS
t ASR
Address
t RAH
t ASC
Row
t CAH
Column
t WCS
t WCH
t ASC
t CAH
t ASC
Column
Column
t WCS
t CAH
t WCH
t WCS
t WCH
UWE
LWE
t DS
Din
Dout
26
Din
t DS
t DS
t DH
t DH
t DH
Din
High-Z
Din
t CRP
HM51(S)4170D Series, HM51(S)4270D Series
Fast Page Mode Delayed Write Cycle
t RASC
t RP
RAS
t CSH
t RSH
t PC
tT
t CAS
t RCD
t CP
t CP
t CAS
t CAS
t CRP
CAS
t ASC
t ASR
t RAH
Address
Row
t CAH
t CAH
Column
t ASC
t CWL
t ASC
Column
t CAH
Column
t CWL
t CWL
t RCS
t WP
t RWL
t WP
t WP
UWE
LWE
t DH
t DS
Din
t DH
t RCS
t DS
Din
Din
t RCS
t DH
t DS
Din
t OEH
High-Z
Dout
t ODD
OE
27
HM51(S)4170D Series, HM51(S)4270D Series
Fast Page Mode Read-Modify-Write Cycle
t RP
t RASC
RAS
t RCD
t PCM
tT
CAS
t RAD
t RAH
Address
t ACP
t CAH
t ASR
t CRP
t CP
t CP
Row
t CAH
t CAH
tASC
t ASC
t ASC
Column
Column
t RCS
t AWD
t CWD
t CWL
t RWD
t WP
Column
t AWD
t CWL
t CWD
t RCS
t WP
t CPW
t RCS
t CPW
t CWL
t AWD
t RWL
t CWD
t WP
UWE
LWE
t CAC
t DZC
High-Z
Din
t DH
t DZC t CAC
t DS
t DH
tDZC
High-Z
Din
t CAC
t DZO
t OAC
t OEH
Dout
t DZO
Din
t AA
t RAC
Dout
t DH
High-Z
Din
t AA
High-Z
t ACP
t DS
t DS
t OAC
t OEH
t OFF2
t OEH
Dout
Dout
t OFF2
t OAC
t DZO
t OFF2
OE
t ODD
28
t ODD
t ODD
HM51(S)4170D Series, HM51(S)4270D Series
Self Refresh Cycle*23, 24, 25, 26
t RASS
t RP
t RPS
RAS
tT
t CRP
,
t RPC
t CPN
t CSR
t CHS
)"
CAS
Address
t OFF1
Dout
High-Z
29
HM51(S)4170D Series, HM51(S)4270D Series
Package Dimensions
HM514170DJ/DLJ, HM514270DJ/DLJ Series
HM51S4170DJ/DLJ, HM51S4270DJ/DLJ Series (CP-40D)
Unit: mm
20
1.30 Max
0.43 ± 0.10
1.27
0.10
30
3.50 ± 0.26
0.74
0.31
2.30 +– 0.14
1
0.63 Min
21
10.16 ± 0.13
40
11.18 ± 0.13
25.80
26.16 Max
9.40 ± 0.25
HM51(S)4170D Series, HM51(S)4270D Series
HM514170DTT/DLTT, HM514270DTT/DLTT Series
HM51S4170DTT/DLTT, HM51S4270DTT/DLTT Series (TTP-44/40DB)
23
10.16
44
18.41
18.81 Max
35 32
Unit: mm
1
0.27 ± 0.07
10 13
0.80
0.13
22
M
11.76 ± 0.2
0 – 5°
0.68
0.08 Min
0.18 Max
+0.075
–0.025
0.10
0.145
1.20 Max
1.15 Max
0.50 ± 0.10
31
HM51(S)4170D Series, HM51(S)4270D Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
USA
Tel: 415-589-8300
Fax: 415-583-4207
32
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Tel: 089-9 91 80-0
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Tel: 27359218
Fax: 27306071
HM51(S)4170D Series, HM51(S)4270D Series
Revision Record
Rev.
Date
Contents of Modification
0.0
Oct. 18, 1996
Initial issue
Drawn by
Approved by
33
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