NUP4201DR2 Low Capacitance Surface Mount TVS for High−Speed Data Interfaces The NUP4201DR2 transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD, EFT, and lightning. Features: SO−8 LOW CAPACITANCE VOLTAGE SUPPRESSOR 500 WATTS PEAK POWER 6 VOLTS • SO−8 Package • Peak Power − 500 Watts 8 x 20 S • ESD Rating: • http://onsemi.com IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000−4−4 (EFT) 40 A (5/50 ns) IEC 61000−4−5 (lightning) 23 (8/20 s) UL Flammability Rating of 94V−0 PIN CONFIGURATION AND SCHEMATIC Typical Applications: • • • • • • High Speed Communication Line Protection USB Power and Data Line Protection Video Line Protection Base Stations HDSL, IDSL Secondary IC Side Protection Microcontroller Input Protection I/O 1 1 8 REF 2 REF 1 2 7 I/O 4 REF 1 3 6 I/O 3 I/O 2 4 5 REF 2 8 MAXIMUM RATINGS Rating Peak Power Dissipation 8 x 20 S @ TA = 25°C (Note 1) Junction and Storage Temperature Range Lead Solder Temperature − Maximum 10 Seconds Duration Symbol Value Unit Ppk 500 W TJ, Tstg −55 to +150 °C TL 260 °C 1 SO−8 CASE 751 PLASTIC MARKING DIAGRAM 1. Non−repetitive current pulse 8 x 20 S exponential decay waveform P4201 LYW P4201 L Y W = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device NUP4201DR2 Package Shipping† SO−8 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 March, 2004 − Rev. 3 1 Publication Order Number: NUP4201DR2/D NUP4201DR2 ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Typ Max Unit VBR 6.0 − − V Reverse Leakage Current @ VRWM = 5.0 Volts IR N/A − 10 A Maximum Clamping Voltage @ IPP = 1.0 A, 8 x 20 S VC N/A − 9.8 V Maximum Clamping Voltage @ IPP = 10 A, 8 x 20 S VC N/A − 12 V Between I/O Pins and Ground @ DC Bias = 0 V, 1.0 MHz Capacitance − 5.0 10 pF Between I/O Pins and I/O @ DC Bias = 0 V, 1.0 MHz Capacitance − 2.5 5.0 pF Reverse Breakdown Voltage @ It = 1.0 mA ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) UNIDIRECTIONAL (Circuit tied to Pins 1 and 3 or 2 and 3) Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT VBR IF VC VBR VRWM IR VF IT Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current IPP Maximum Temperature Coefficient of VBR IF Forward Current VF Forward Voltage @ IF ZZT Maximum Zener Impedance @ IZT IZK Reverse Current ZZK Maximum Zener Impedance @ IZK Uni−Directional TVS http://onsemi.com 2 V NUP4201DR2 9 8 8 7 IR, REVERSE LEAKAGE (A) VZ, REVERSE BREAKDOWN (V) TYPICAL CHARACTERISTICS 7 6 5 4 3 2 1 0 −100 −50 0 50 100 T, TEMPERATURE (°C) 150 6 5 4 3 2 1 0 −100 200 VC, CLAMPING VOLTAGE (V) % OF PEAK PULSE CURRENT 70 60 HALF VALUE IRSM/2 @ 20 s 50 40 30 tP 20 10 0 0 20 40 200 35 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 s 80 150 100 Figure 2. Reverse Leakage versus Temperature PEAK VALUE IRSM @ 8 s tr 90 50 T, TEMPERATURE (°C) Figure 1. Reverse Breakdown versus Temperature 100 0 −50 60 30 25 20 15 10 5 0 80 0 10 20 30 40 50 60 70 80 IPP, PEAK PULSE CURRENT (A) t, TIME (s) Figure 3. 8 × 20 s Pulse Waveform Figure 4. Clamping Voltage versus Peak Pulse Current http://onsemi.com 3 90 NUP4201DR2 APPLICATIONS INFORMATION The new NUP4201DR2 device is a low capacitance TVS Diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD conditions or transient voltage conditions. Because of its low capacitance array configuration, it can be used in high speed I/O data lines. The integrated design of the NUP4201DR2 device offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SO−8). If a transient condition occurs, the steering diodes will drive the transient condition to the positive polarity of the power supply or to ground. The TVS device protects the power line against over−voltage conditions to avoid damage in any downstream components. Option 2 Four Data lines protection with Bias and power supply isolation resistor. NUP4201DR2 Device’s Configurations Options The NUP4201DR2 is able to protect up to four data lines against transient over−voltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vcc+Vf). The diodes will drive the transient current away from the sensitive circuit. Data lines are connected at pins 1,4,6 and 7. The negative reference is connected at pins 5 and 8. These pins must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce as much as possible the PCB trace lengths to minimize parasitic inductances. The NUP4201DR2 device can be isolated from the power supply by connecting a series resistor between pins 2 & 3 and Vcc. A resistor of 10K is recommended for isolation purposes. The internal TVS and steering diodes remain biased, which provides the advantage of lower capacitance. I/O 1 I/O 2 VCC 10 K 8 2 7 3 6 4 5 I/O 3 I/O 4 Option 3 Four Data lines protection using internal TVS diode as reference. I/O 1 I/O 2 Option 1 Four Data lines protection and power supply protection using Vcc as reference. 1 8 NC 2 7 NC 3 6 4 5 I/O 3 I/O 1 I/O 2 VCC 1 I/O 4 1 8 2 7 3 6 4 5 In the case of applications in which a positive supply reference is not available or full isolation is required, the internal TVS could be used as the reference, so for this purpose, the pins 2 and 3 are not connected. In this case, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). I/O 3 I/O 4 For this configuration, connect pins 2 & 3 directly to the positive supply rail (Vcc), the data lines are referenced to the supply voltage. The internal TVS diode prevents over−voltage on the supply rail. http://onsemi.com 4 NUP4201DR2 “Rail to Rail” Protection Topology The following figure shows a case when discrete diodes are configured for rail to rail protection on an I/O line: a good board layout to minimize the effects of the parasitic inductances. Nevertheless, some disadvantages are still present when discrete diodes are used to suppress ESD conditions in “rail to rail” configuration. If the ESD current is too high, it can potentially result in the damage of any components connected to that rail and it is also possible to experience damage in the discrete diodes if their power dissipation capability is exceeded. The NUP4201DR2 On Semiconductor’s device provides a concept named “RailClamp” which is designed to eliminate the disadvantages of the usage of discrete diodes for ESD protection. The RailClamp concept is achieved with the integration of the TVS device in together with the steering diodes. VCC ESD Positive 11 ESD Negative 12 D1 VF + VCC −VF D2 Upon the above figure, it is possible to observe that if a positive ESD condition occurs, the D1 diode will be forward biased while the D2 diode will be biased when a negative ESD condition occurs. A valid first approximation of the resulting clamping voltage due to the protection diodes can be made as follows: For positive pulse conditions: Vc = Vcc + Vf For negative pulse conditions: Vc = −Vf It is important to mention that effects of parasitic inductances must be considered for fast rise time transient conditions because the clamping voltage on the protected circuit will be different than in the previous case. A valid approximation of the resulting clamping voltage can be made as show below: For positive pulse conditions: Vc = Vcc + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also in the L diESD/dt factor, so this is why it is very important to have D1 D3 D5 D7 D2 D4 D6 D8 0 Rail to Rail Protection with integrated TBS to achieve the RailClamp concept During an ESD condition, the ESD current will be driven to ground through the TVS device, so the resulting clamping voltage on the protected IC will be: Vc = VF(RailClamp) + VTVS. The clamping voltage of the TVS device is shown as part of the specifications of the NUP4201DR2 datasheet. The clamping voltage will depend on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 5 NUP4201DR2 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS VBUS VBUS D+ RT D+ RT D− VBUS USB Controller GND D− VBUS NUP4201DR2 CT CT DOWNSTREAM USB PORT GND VBUS VBUS NUP2201DT1 RT D+ RT D− GND CT CT ESD Protection for USB Port R1 RTIP R3 R2 RRING T1 VCC T1/E1 TRANCEIVER NUP4201DR2 R4 TTIP R5 TRING T2 TI/E1 Interface Protection http://onsemi.com 6 DOWNSTREAM USB PORT NUP4201DR2 PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NUP4201DR2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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