Maxim MAX3971U 3.3v, 10.3gbps limiting amplifier Datasheet

19-2086; Rev 1; 12/02
+3.3V, 10.3Gbps Limiting Amplifier
____________________________Features
♦ Single +3.3V Power Supply
♦ 155mW Power Consumption
♦ 9.5mVP-P Input Sensitivity
♦ 800mVP-P Input Overload
♦ 3.4psP-P Deterministic Jitter
♦ Dice and 4mm x 4mm QFN Packages
♦ Output Disable Feature
Applications
Ordering Information
10-Gigabit Ethernet Optical Receivers
PART
TEMP. RANGE
VSR OC-192 Receivers
MAX3971UGP
0°C to +85°C
20 QFN*
PIN-PACKAGE
10-Gigabit Fibre Channel Receivers
MAX3971U/D
0°C to +85°C
Dice**
*Exposed pad
**Dice are designed to operate over a 0°C to +110°C junction
temperature (TJ) range, but are tested and guaranteed at
TA = +25°C.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.1µF
SUPPLY FILTER
+3.3V
CZ-
CZ+
VCC1 VCC2 VCC3
GNDIN+
0.1µF
TIA
OUT+
IN+
100Ω
0.1µF
0.1µF
0.1µF
100Ω
OUT-
INGNDIN-
MAX3970
MAX3971
DISABLE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3971
General Description
The MAX3971 is a compact, low-power, 10.3Gbps limiting amplifier. It accepts signals over a wide range of input
voltage levels and provides constant-level output voltages with controlled edge speeds. It functions as a data
quantizer. The output of the amplifier is a 250mVP-P differential CML signal with a 100Ω differential termination.
The MAX3971 is designed to work with the MAX3970, a
10.3Gbps transimpedance amplifier (TIA). The limiting
amplifier operates on a single +3.3V supply and consumes only 155mW. The part functions over the 0°C to
+85°C temperature range. It also has a disable function
that allows the outputs to be squelched if required by
the application.
The MAX3971 is offered in die form and in a compact
4mm x 4mm, 20-pin QFN plastic package.
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC1, VCC2, VCC3 .......................-0.5V to +0.5V
Voltage at IN+, IN-, DISABLE,
CZ+, CZ-, OUT+, OUT-........................+0.5V to (VCC + 0.5V)
Differential Voltage Between CZ+ and CZ- ...........................±1V
Differential Voltage Between IN+ and IN-...........................±2.5V
Continuous Power Dissipation (TA = +85°C)
20-Lead QFN (derate 20mW/°C above +85°C) ..............1.3W
Operating Ambient Temperature Range .............-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V, output load = 50Ω to VCC, TA = +25°C, unless otherwise noted. Data mark density is 50%.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
85
Supply Current
ICC
47
Small-Signal Bandwidth
BW
10
Low-Frequency Cutoff
CZ = 0.1µF
40
Data Rate
Random Jitter
Transition Time, Output
tr, tf
Input Sensitivity
VIN-min
Input Overload
VIN-max
4.7
14
800mVP-P input, K28.5 pattern at 10.3Gbps
(Note 1)
3.4
7
20mVP-P to 800mVP-P (Note 2)
0.7
1.0
20% to 80%, OUT+, OUT-
20
30
ps
9.5
mVP-P
BER = 1E-12, 223 - 1PRBS, 10.3Gbps
800
Differential Data
Output-Voltage Swing
VOD1
DISABLE high
VOD2
DISABLE low
Output Resistance
ROUT
42
190
Single-ended
42
58
1
50
250
400
52
Note 2:
2
58
0.05
Ω
mVP-P
Ω
mVP-P
1
mA
1.4
V
2.8
DISABLE Input Low Voltage
Note 1:
psRMS
V
75
High = VCC, low = GND
psP-P
mVP-P
52
VCC 0.75
Data Output Offset when
DISABLE is High
DISABLE Input High Voltage
Gbps
20mVP-P input, K28.5 pattern at 10.3Gbps
(Note 1)
Single-ended
VCM
kHz
8
RIN
DISABLE Input Current
160
10mVP-P input, K28.5 pattern at 10.3Gbps
(Note 1)
Data Input Resistance
Data Output Common-Mode
Voltage
mA
GHz
10
Deterministic Jitter
UNITS
V
Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). It is the peak-to-peak deviation from the
ideal time crossings, measured at the zero-level crossings of the differential output.
Random jitter is measured with the minimum input signal applied. To achieve a bit error rate of 10-12, the peak-to-peak random jitter is 14.1 times the RMS random jitter.
_______________________________________________________________________________________
+3.3V, 10.3Gbps Limiting Amplifier
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 800mVP-P AT 10.3Gbps)
SUPPLY CURRENT vs. TEMPERATURE
MAX3971 toc02
MAX3971 toc03
MAX3971 toc01
70
65
SUPPLY CURRENT (mA)
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 9mVP-P AT 10.3Gbps)
60
55
50mV/div
50mV/div
50
45
40
0
10
20
30
40
50
60
70
80
20ps/div
20ps/div
DETERMINISTIC JITTER vs. TEMPERATURE
(800mVP-P INPUT K28.5 PATTERN AT 10.3Gbps)
DETERMINISTIC JITTER vs. TEMPERATURE
(10mVP-P INPUT K28.5 PATTERN AT 10.3Gbps)
90
(1) VCC = +3.0V, INPUT = 800mVP-P
(2) VCC = +3.6V, INPUT = 800mVP-P
JITTER (psP-P)
TIME (ps)
21
(1)
(2)
20
19
0
10
20
30
40
50
60
70
80
90
(1) VCC = +3.0V
(2) VCC = +3.6V
(1)
(2)
0
10
20
30
40
50
60
70
80
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
90
(1) VCC = +3.0V
(2) VCC = +3.6V
(1)
(2)
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT SENSITIVITY vs. TEMPERATURE
(FOR BIT-ERROR RATIO OF 1E-12)
INPUT RETURN (S11)
INPUT SIGNAL = -20dBm
OUTPUT RETURN (S22)
INPUT SIGNAL = -20dBm
90
MAX3971 toc09
0
80
10
MAX3971 toc08
10
MAX3971 toc07
11
0
10
-10
9
GAIN (dB)
-10
GAIN (dB)
SIGNAL INPUT LEVEL (mVP-P)
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
MAX3971 toc06
MAX3971 toc04
22
JITTER (psP-P)
TRANSITION TIME vs. TEMPERATURE
(20% to 80%)
MAX3971 toc05
TEMPERATURE (°C)
-20
-20
-30
-30
-40
-40
8
7
-50
-50
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
100
2100
4100
6100
FREQUENCY (MHz)
8100
10,100
100
2100
4100
6100
FREQUENCY (MHz)
8100
10,100
_______________________________________________________________________________________
3
MAX3971
Typical Operating Characteristics
(VCC = +3.3V, output load = 50Ω to VCC, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = +3.3V, output load = 50Ω to VCC, TA = +25°C, unless otherwise noted.)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
50
MAX3971 toc11
60
MAX3971 toc10
60
50
40
CMMR (dB)
40
PSRR (dB)
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
30
30
20
20
10
10
0
0
1
10
100
1000
1
10
100
1000
10,000
FREQUENCY (MHz)
FREQUENCY (MHz)
Pin Description
4
PIN
NAME
1
GNDIN+
2
FUNCTION
IN+
Input Ground for Shielding Input Signal IN+. Not connected internally.
Noninverting Input Signal
3
IN-
Inverting Input Signal
4
GNDIN-
Input Ground for Shielding Input Signal IN-. Not connected internally.
5, 7, 9, 10
N.C.
No Connection. Leave unconnected.
6, 8, 11
GND
Ground
12, 15
VCC3
Output Circuitry Power Supply
13
OUT-
Inverting Output of Amplifier
14
OUT+
16
DISABLE
17
VCC2
Power Supply to Circuitry Other than Input and Output Circuits
18
CZ+
Filter Capacitor for Offset Correction. Attach other side of a capacitor to pin 19. See the Detailed
Description.
19
CZ-
20
VCC1
EP
Exposed
Pad
Noninverting Output of Amplifier
When High, the Outputs are Disabled
See pin 18.
Input Circuitry Power Supply
Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.
_______________________________________________________________________________________
+3.3V, 10.3Gbps Limiting Amplifier
Figure 1 is a functional diagram of the MAX3971 limiting amplifier.The signal path consists of an input buffer
followed by a gain stage and output amplifier. A feedback loop provides offset correction by driving the
average value of the differential output to zero.
Gain Stage and Offset Correction
The limiting amplifier provides approximately 50dB
gain. This large gain makes the amplifier susceptible to
small DC offsets, which cause deterministic
jitter. A low-frequency loop is integrated into the limiting
amplifier to reduce output offset, typically to less than
2mV.
The external capacitor CZ is required to set the low-frequency cutoff for the offset correction loop and for stability. The time constant of the loop is set by the
CZ
CZ-
MAX3971
GNDIN+
OFFSET
CORRECTION
AMP
CZ+
DISABLE
OUT+
OUTPUT
AMPLIFIER
GAIN
50dB
IN-
CML Input Circuit
The input buffer is designed to accept CML input signals such as the output from the MAX3970 transimpedance amplifier. An equivalent circuit for the input is
shown in Figure 2. DC-coupling the inputs is not recommended because doing so prevents the part’s offset
correction circuitry from working properly. Thus, ACcoupling capacitors are required on the input.
CML Output Circuit
An equivalent circuit for the output network is shown in
Figure 3. It consists of two 50Ω resistors connected to
VCC driven by the collectors of an output differential
transistor pair (Q1 and Q2). The differential output signals are clamped by transistors Q3 and Q4 when the
DISABLE input is high.
Disable Function
LOWPASS
FILTER
IN+
INPUT
AMPLIFIER
product of an equivalent 20kΩ on-chip resistor and the
value of the off-chip capacitor, CZ. For stable operation, the minimum value of CZ is 0.01µF. To minimize
pattern-dependent jitter, CZ should be as large as possible. For 10-Gigabit Ethernet applications, the typical
value of CZ is 0.1µF. Keep CZ as close to the package
as possible.
A logic signal can be applied to the DISABLE pin to
squelch the output signal. When the output is disabled,
an offset is added to the output, preventing the following stage from oscillating (if DC-coupled).
OUT-
GNDIN-
Figure 1. Functional Diagram
VCC3
VCC1
GNDIN+
50Ω
50Ω
50Ω
50Ω
OUT+
OUT-
IN+
DISABLE
Q3
Q4
Q1
Q2
ESD
STRUCTURES
INDATA
GNDIN-
ESD
STRUCTURES
Figure 2. CML Input Equivalent Circuit
Figure 3. CML Input Equivalent Circuit Showing Clamping
Circuit for Squelching the Output Signal
_______________________________________________________________________________________
5
MAX3971
Detailed Description and
Applications Information
Layout Considerations
Circuit board layout and design can significantly affect
the MAX3971’s performance. Use good high-frequency
techniques, including fixed-impedance transmission
lines for the high-frequency data signal. Use a multilayer board with solid ground plane. Minimize the inductance between MAX3971 and the ground plane.
The MAX3971 uses three power supply pins (VCC1,
VCC2, VCC3). The input circuitry of the MAX3971 is
supplied by VCC1. The output drivers have a separate
supply (VCC3), which usually has large pulsing currents. All other circuitry is powered by VCC2. It is possible to simply connect the three pins together. However,
better isolation of the input circuitry is ensured by using
a supply filter. For optimal isolation, Figure 4 shows a
possible supply filtering circuit. Element L, a ferrite
bead, provides isolation between a noisy VCC3 and
sensitive VCC1.
+3.3V
L
C = 0.001µF
SUPPLY FILTER
C = 0.001µF
VCC1
C = 0.001µF
VCC2
VCC3
MAX3971
Figure 4. Power-Supply Filter
VCC1
CZ-
CZ+
VCC2
DISABLE
Pin Configuration
20
19
18
17
16
SUBSTRATE: Electrically Isolated
1
15 VCC3
IN+
2
14 OUT+
IN-
3
GNDIN-
4
12 VCC3
N.C.
5
11 GND
13 OUT-
8
9
10
GND
N.C.
N.C.
7
N.C.
MAX3971
6
Chip Information
TRANSISTOR COUNT: 1803
PROCCESS: SiGe Bipolar
GNDIN+
GND
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
20 QFN
6
_______________________________________________________________________________________
+3.3V, 10.3Gbps Limiting Amplifier
VCC1
CZ-
CZ+
VCC2
DISABLE
GNDIN+
VCC3
IN+
OUT+
IN-
OUT0.045"
(1.15mm)
GNDIN-
VCC3
N.C.
GND
GND
N.C.
GND
N.C.
N.C.
0.049"
(1.25mm)
_______________________________________________________________________________________
7
MAX3971
Chip Topography
+3.3V, 10.3Gbps Limiting Amplifier
MAX3971
Chip Topography (continued)
MAX3971
8
PIN NUMBER
X DIMENSION
(MICRONS)
Y DIMENSION
(MICRONS)
1
0
672
2
0
546
3
0
420
4
0
294
5
0
168
6
163.8
0
7
289.8
0
8
415.8
0
9
541.8
0
10
667.8
0
11
884.8
168
12
884.8
294
13
884.8
420
14
884.8
546
15
884.8
672
16
667.8
772.8
17
541.8
772.8
18
415.8
772.8
19
289.8
772.8
20
163.8
772.8
•
All dimensions are in microns.
•
Pad dimensions:
PASSIVATION OPENING: 94.4 microns ×
94.4 microns
METAL: 102.4 microns × 102.4 microns
•
All measurements specify the lower left corner of
the pad
20
19
18
17
16
15
1
Y
14
2
13
3
MAX3971
12
4
5
(0,0)
11
X
6
7
8
9
10
_______________________________________________________________________________________
+3.3V, 10.3Gbps Limiting Amplifier
12,16,20, 24L QFN.EPS
_______________________________________________________________________________________
9
MAX3971
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX3971
+3.3V, 10.3Gbps Limiting Amplifier
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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