PHILIPS HEF40240BD Octal inverting buffers with 3-state output Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40240B
buffers
Octal inverting buffers with 3-state
outputs
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF40240B
buffers
Octal inverting buffers with 3-state outputs
DESCRIPTION
The HEF40240B is an octal inverting buffer with 3-state
outputs. It features output stages with high current output
capability suitable for driving highly capacitive loads.
The 3-state outputs are controlled by the output enable
inputs EOA and EOB. A HIGH on EO causes the outputs to
assume a high impedance OFF-state. The device also
features hysteresis on all inputs to improve noise
immunity.
Schmitt-trigger action in the inputs makes the circuit highly
tolerant to slower input rise and fall times.
The HEF40240B is pin and functionally compatible with
the TTL ‘240’ device.
Fig.2 Pinning diagram.
HEF40240BP(N): 20-lead DIL; plastic (SOT146-1)
HEF40240BD(F): 20-lead DIL; ceramic (cerdip) (SOT152)
HEF40240BT(D): 20-lead SO; plastic (SOT163-1)
( ): Package Designator North America
PINNING
IA1 to IA4
inputs
IB1 to IB4
inputs
OA1 to OA4
bus outputs
OB1 to OB4
bus outputs
EOA, EOB
output enable inputs (active LOW)
FAMILY DATA, IDD LIMITS category buffers
Fig.1 Functional diagram.
January 1995
See Family Specifications
2
Philips Semiconductors
Product specification
HEF40240B
buffers
Octal inverting buffers with 3-state outputs
TRUTH TABLE
INPUTS
OUTPUT
In
EO
On
H
L
L
L
L
H
X
H
Z
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance off state
Fig.3 Logic diagram (one buffer).
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
See Family Specifications except for:
D.C. current into any input
± II
max.
D.C. source or sink current into any output
± IO
max.
25 mA
D.C. current into the supply terminals
±I
max.
100 mA
10 mA
DC CHARACTERISTICS
VSS = 0 V
VDD
VOH
V
HIGH
Output current
HIGH
−40
SYMBOL
PARAMETER
Output current
Tamb (°C)
VOL
V
V
MIN.
5
3,6
−
−IOH
10
8,4
−
15
13,2
+25
+85
UNIT
TYP.
MIN.
TYP.
MIN.
TYP.
9,3
−
10,0
24,0
10,7
−
mA
−IOH
14,4
−
15,0
46,0
15,0
−
mA
−
−IOH
19,5
−
20,0
62,0
19,8
−
mA
5
4,6
−
−IOH
0,75
−
0,6
1,2
0,45

mA
10
9,5
−
−IOH
1,85
−
1,5
3,0
1,1
−
mA
15
13,5
−
−IOH
14,5
−
15,0
50,0
15,5
−
mA
5
−
0,4 IOL
2,9
−
2,3
5,4
1,75
−
mA
10
−
0,5 IOL
9,5
−
7,6
17,0
5,50
−
mA
15
−
1,5 IOL
30,0
−
25,0
45,0
19,0
−
mA
Hysteresis
5
−
−
VH
−
−
−
220,0
−
−
mV
voltage
10
−
−
VH
−
−
−
250,0
−
−
mV
(any input)
15
−
−
VH
−
−
−
320,0
−
−
mV
Output current
LOW
January 1995
3
Philips Semiconductors
Product specification
HEF40240B
buffers
Octal inverting buffers with 3-state outputs
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar
n-p-n transistor conducting.
Fig.4 Typical output source current characteristic.
Fig.5 Schematic diagram of output stage.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
ALL BUFFERS SWITCHING
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
4 250 fi + ∑ (foCL) × VDD2
10
17 000 fi + ∑ (foCL) × VDD
2
15
46 000 fi + ∑ (foCL) × VDD
2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF40240B
buffers
Octal inverting buffers with 3-state outputs
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
PARAMETER
VDD
V
SYMBOL MIN.
TYP. MAX.
UNIT
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
IAn/Bn → OAn/Bn
HIGH to LOW
5
10
tPHL
15
IAn/Bn → OAn/Bn
LOW to HIGH
5
10
tPLH
15
Output transition
times
HIGH to LOW
LOW to HIGH
5
95
190
ns
83 ns + (0,24 ns/pF) CL
40
80
ns
35 ns + (0,10 ns/pF) CL
30
60
ns
26 ns + (0,07 ns/pF) CL
85
170
ns
82 ns + (0,06 ns/pF) CL
40
80
ns
38 ns + (0,03 ns/pF) CL
30
60
ns
29 ns + (0,02 ns/pF) CL
40
80
ns
20
40
ns
15
15
30
ns
5
30
60
ns
20
40
ns
15
15
30
ns
5
70
140
ns
35
70
ns
10
10
tTHL
tTLH
3-state propagation delays
Output disable times
EO → OAn/Bn
HIGH
LOW
10
tPHZ
15
30
60
ns
5
75
150
ns
40
80
ns
15
30
60
ns
5
80
160
ns
10
tPLZ
Output enable times
EO → OAn/Bn
HIGH
LOW
10
tPZH
35
70
ns
15
30
60
ns
5
90
180
ns
40
80
ns
30
60
ns
10
tPZL
15
January 1995
5
see Fig.6
Philips Semiconductors
Product specification
Octal inverting buffers with 3-state outputs
 tTLH
− − − − tTHL
Fig.6 Output transition times as a function of the load capacitance.
January 1995
6
HEF40240B
buffers
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