Cypress CY7C09579V-83AI 3.3v 16k/32k x 36 fle x 36-tm synchronous dual-port static ram Datasheet

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
CY7C09569V
CY7C09579V
3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
Features
• 3.3V Low operating power
• True dual-ported memory cells which allow simultaneous access of the same memory location
— Active = 250 mA (typical)
— Standby = 10 μA (typical)
• Fully synchronous interface for ease of use
• Two Flow-Through/Pipelined devices
• Burst counters increment addresses internally
— 16K x 36 organization (CY7C09569V)
— Shorten cycle times
— 32K x 36 organization (CY7C09579V)
— Minimize bus noise
• 0.25-micron CMOS for optimum speed/power
— Supported in Flow-Through and Pipelined modes
• Three modes
— Flow-Through
• Counter Address Read Back via I/O lines
— Pipelined
• Single Chip Enable
— Burst
• Automatic power-down
• Commercial and Industrial Temperature Ranges
• Bus-Matching Capabilities on Right Port
(x36 to x18 or x9)
• Compact package
• Byte-Select Capabilities on Left Port
— 144-Pin TQFP (20 x 20 x 1.4 mm)
• 100-MHz Pipelined Operation
— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)
• High-speed clock to data access 5/6/8 ns
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)
Logic Block Diagram
R/WL
R/WR
OEL
Left
Port
Control
Logic
B0–B3
CEL
Right
Port
Control
Logic
OER
CER
FT/PipeR
FT/PipeL
BE
9
9
I/O0L–I/O8L
9
9
I/O9L–I/O17L
I/O
Control
9
I/O
Control
9
Bus
Match
9/18/36
I/OR
I/O18L–I/O26L
9
9
BM
SIZE
I/O27L–I/O35L
14/15
A0–A13/14L[1]
CLKL
ADSL
CNTENL
CNTRSTL
14/15
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
A0–A13/14R[1]
CLKR
ADSR
CNTENR
CNTRSTR
Note:
1. A0–A13 for 16K; A0–A14 for 32K devices.
Cypress Semiconductor Corporation
Document #: 38-06054 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 18, 2005
CY7C09569V
CY7C09579V
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3V
synchronous CMOS 16K and 32K x 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 5 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available tCD1 = 12.5 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
external R/W LOW duration. The internal write pulse is selftimed to allow the shortest possible cycle times.
Document #: 38-06054 Rev. *B
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the
pipelined mode, one cycle is required with CE LOW to
reactivate the outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 144-Pin Thin Quad Plastic Flatpack
(TQFP), 144-Pin Pb-Free Thin Quad Plastic Flatpack (TQFP)
and 172-Ball Ball Grid Array (BGA) packages.
Page 2 of 30
CY7C09569V
CY7C09579V
Pin Configurations
144-Pin Thin Quad Flatpack (TQFP)
I/O33L
I/O34L
I/O35L
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
B0
B1
B2
B3
OEL
R/WL
VDD
VSS
VSS
CEL
CLKL
ADSL
CNTRSTL
CNTENL
FT/PIPEL
A8L
A9L
A10L
A11L
A12L
A13L
NC
I/O26L
I/O25L
I/O24L
CY7C09569V (16K x 36)
CY7C09579V (32K x 36)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
I/O33R
I/O34R
I/O35R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
BM
SIZE
BE
vss
OER
R/WR
VDD
VSS
VSS
CER
CLKR
ADSR
CNTRSTR
CNTENR
FT/PIPER
A8R
A9R
A10R
A11R
A12R
A13R
NC
I/O26R
I/O25R
I/O24R
[3
I/O5R
I/O6R
I/O7R
I/O8R
VDD
I/O18R
I/O19R
I/O20R
I/O21R
VSS
I/O22R
I/O23R
I/O0L
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
VSS
I/O5L
VSS
I/O4L
I/O3L
I/O2L
I/O1L
I/O21L
I/O20L
I/O19L
I/O18L
VDD
I/O8L
I/O7L
I/O6L
I/O23L
I/O22L
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
[2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
I/O32L
I/O31L
VSS
I/O30L
I/O29L
I/O28L
I/O27L
VDD
I/O17L
I/O16L
I/O15L
I/O14L
VSS
I/O13L
I/O12L
I/O11L
I/O10L
I/O9L
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
VSS
I/O14R
I/O15R
I/O16R
I/O17R
VDD
I/O27R
I/O28R
I/O29R
I/O30R
VSS
I/O31R
I/O32R
Top View
Notes:
2. This pin is A14L for CY7C09579V.
3. This pin is A14R for CY7C09579V.
Document #: 38-06054 Rev. *B
Page 3 of 30
CY7C09569V
CY7C09579V
Pin Configurations (continued)
172-Ball Ball Grid Array (BGA)
Top View
1
A
2
I/O32L I/O30L
3
4
5
6
NC
VSS
I/O13L
VDD
B
A0L
C
NC
A1L
I/O31L I/O27L
D
A2L
A3L
I/O35L I/O34L I/O28L I/O16L
E
A4L
A5L
NC
B0L
NC
F
VDD
A6L
A7L
B1L
NC
G
OEL
B2L
B3L
H
VSS
R/WL
J
A9L
K
7
9
10
11
I/O11L I/O11R VDD I/O13R VSS
I/O33L I/O29 I/O17L I/O14L I/O12L I/O9L
NC
8
NC
13
A0R
I/O27R I/O31R
A1R
NC
VSS I/O16R I/O28R I/O34R I/O35R
A3R
A2R
NC
NC
BM
NC
A5R
A4R
NC
SIZE
A7R
A6R
VDD
CEL
CER
VSS
BE
OER
A8L
CLKL
CLKR
A8R
R/WR
VSS
A10L
VSS
ADSL
NC
NC
ADSR
VSS
A10R
A9R
A11L
A12L
NC
CNTRSTL
NC
NC
CNTRSTR
NC
A12R
A11R
L
FT/PIPEL
A13L
CNTENL
CNTENR
A13R
FT/PIPER
M
NC
NC
I/O26L I/O25L I/O19L
NC[2] I/O22L I/O18L
NC
NC
14
I/O30R I/O32R
I/O9R I/O12R I/O14R I/O17R I/O29R I/O33R
I/O15L I/O10L I/O10R I/O15R
VSS
12
NC
VSS
VSS I/O19R I/O25R I/O26R
NC
I/O7L
I/O2L
I/O2R I/O7R
NC
I/O18R I/O22R NC[3]
NC
N
I/O24L I/O20L I/O8L
I/O6L
I/O5L
I/O3L
I/O0L
I/O0R
I/3R
I/O5R I/O6R I/O8R I/O20R I/O24R
P
I/O23L I/O21L
VSS
I/O4L
VDD
I/O1L
I/O1R
VDD
I/O4R
Document #: 38-06054 Rev. *B
NC
VSS
NC
I/O21R I/O23R
Page 4 of 30
CY7C09569V
CY7C09579V
Selection Guide
fMAX2 (Pipelined)
Max. Access Time (Clock to Data, Pipelined)
CY7C09569V
CY7C09579V
-100
CY7C09569V
CY7C09579V
-83
CY7C09569V
CY7C09579V
-67
Unit
100
83
67
MHz
5
6
8
ns
Typical Operating Current ICC
250
240
230
mA
Typical Standby Current for ISB1 (Both Ports TTL Level)
30
25
25
mA
Typical Standby Current for ISB3 (Both Ports CMOS Level)
10
10
10
μA
Pin Definitions
Left Port
Right Port
A0L–A13/14L
A0R–A13/14R
Address Inputs (A0–A13 for 16K, A0–A14 for 32K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins. To load this address into
the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST
is asserted LOW
CEL
CER
Chip Enable Input.
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O35L
I/O0R–I/O35R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
B0L–B3L
Description
Byte Select Inputs. Asserting these signals enable read and write operations to the corresponding bytes of the memory array.
BM, SIZE
Select Pins for Bus Matching. See Bus Matching for details.
BE
Big Endian Pin. See Bus Matching for details.
VSS
Ground Input.
VDD
Power Input.
Document #: 38-06054 Rev. *B
Page 5 of 30
CY7C09569V
CY7C09579V
Maximum Ratings [4]
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VDD+0.5V
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
VDD
0°C to +70°C
3.3V ± 165 mV
–40°C to +85°C
3.3V ± 165 mV
DC Input Voltage.................................. –0.5V to VDD+0.5V[5]
Electrical Characteristics Over the Operating Range
CY7C09569V
CY7C09579V
-100
Parameter
Description
VOH
Output HIGH Voltage
(VDD = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VDD = Min., IOL= +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current (VDD = Max.,
IOUT = 0 mA) Outputs Disabled
ISB1
ISB2
ISB3
ISB4
-83
-67
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
2.4
2.4
2.4
0.4
2.0
0.4
2.0
Commercial
10
250
385
Industrial
Standby Current (Both Ports TTL Commercial
Level) CEL & CER ≥ VIH, f = fMAX Industrial
30
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Commercial
170
Standby Current (Both Ports
CMOS Level)
CEL & CER ≥ VDD – 0.2V, f = 0
Commercial
75
220
Industrial
0.01
1
Industrial
Standby Current (One Port CMOS Commercial
Level)
Industrial
CEL | CER ≥ VIH, f = fMAX
150
200
0.4
2.0
0.8
–10
V
V
0.8
–10
10
240
360
270
385
25
70
35
85
160
210
170
235
0.01
1
0.01
1
140
190
150
200
V
–10
230
0.8
V
10
μA
340
mA
mA
25
65
mA
mA
150
200
mA
mA
0.01
1
mA
mA
130
180
mA
mA
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
Max.
Unit
10
pF
10
pF
Note:
4. The voltage on any input or I/O pin can not exceed the power pin during power-up.
5. Pulse width < 20 ns.
Document #: 38-06054 Rev. *B
Page 6 of 30
CY7C09569V
CY7C09579V
AC Test Load and Waveforms
3.3V
OUTPUT
Z0 = 50Ω
R = 50Ω
R1 = 590Ω
C [6]
OUTPUT
VTH = 1.5V
C = 5 pF
(b) Three-State Delay (Load 2)
(a) Normal Load (Load 1)
3.0V
ALL INPUT PULSES
R2 = 435Ω
VSS
10%
90%
10%
90%
≤ 3 ns
≤ 3 ns
7
6
Δ for tCD2 (ns)
5
4
3
2
1
20[7] 30
60
80 100
200
Capacitance (pF)
(b) Load Derating Curve
Notes:
6. External AC Test Load Capacitance = 10 pF.
7. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
Document #: 38-06054 Rev. *B
Page 7 of 30
CY7C09569V
CY7C09579V
Switching Characteristics Over the Operating Range
CY7C09569V
CY7C09579V
-100
Parameter
Description
Min.
-83
Max.
Min.
-67
Max.
Min.
Max.
Unit
fMAX1
fMax Flow-Through
67
45
40
MHz
fMAX2
fMax Pipelined
100
83
67
MHz
tCYC1
Clock Cycle Time - Flow-Through
15
22
25
ns
tCYC2
Clock Cycle Time - Pipelined
10
12
15
ns
tCH1
Clock HIGH Time - Flow-Through
6.5
7.5
8.5
ns
tCL1
Clock LOW Time - Flow-Through
6.5
7.5
8.5
ns
tCH2
Clock HIGH Time - Pipelined
4
5
6.5
ns
tCL2
Clock LOW Time - Pipelined
4
5
6.5
ns
tR
Clock Rise Time
tF
Clock Fall Time
tSA
Address Set-Up Time
3.5
4
4
ns
tHA
Address Hold Time
0.5
0.5
0.5
ns
tSB
Byte Select Set-Up Time
3.5
4
4
ns
tHB
Byte Select Hold Time
0.5
0.5
0.5
ns
tSC
Chip Enable Set-Up Time
3.5
4
4
ns
tHC
Chip Enable Hold Time
0.5
0.5
0.5
ns
tSW
R/W Set-Up Time
3.5
4
4
ns
tHW
R/W Hold Time
0.5
0.5
0.5
ns
tSD
Input Data Set-Up Time
3.5
4
4
ns
tHD
Input Data Hold Time
0.5
0.5
0.5
ns
tSAD
ADS Set-Up Time
3.5
4
4
ns
tHAD
ADS Hold Time
0.5
0.5
0.5
ns
tSCN
CNTEN Set-Up Time
3.5
4
4
ns
tHCN
CNTEN Hold Time
0.5
0.5
0.5
ns
tSRST
CNTRST Set-Up Time
3.5
4
4
ns
tHRST
CNTRST Hold Time
0.5
0.5
0.5
ns
tOE
Output Enable to Data Valid
3
3
3
8
[8, 9]
OE to Low Z
2
tOHZ[8, 9]
OE to High Z
1
tCD1
Clock to Data Valid - Flow-Through
tCD2
Clock to Data Valid - Pipelined
tCA1
Clock to Counter Address Valid Flow-Through
tCA2
Clock to Counter Address Valid - Pipelined
tDC
Data Output Hold After Clock HIGH
2
tCKHZ[8, 9]
Clock HIGH to Output High Z
2
tCKLZ[8, 9]
Clock HIGH to Output Low Z
2
tOLZ
3
9
2
7
1
3
ns
3
ns
10
2
7
1
ns
ns
7
ns
12.5
18
20
ns
5
6
8
ns
12.5
18
20
ns
9
10
11
ns
2
6
2
2
2
7
2
2
ns
8
ns
ns
Notes:
8. This parameter is guaranteed by design, but it is not production tested.
9. Test conditions used are Load 2.
Document #: 38-06054 Rev. *B
Page 8 of 30
CY7C09569V
CY7C09579V
Switching Characteristics Over the Operating Range (continued)
CY7C09569V
CY7C09579V
-100
Parameter
Description
Min.
-83
Max.
Min.
-67
Max.
Min.
Max.
Unit
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
30
35
35
ns
tCCS
Clock to Clock Set-Up Time
9
10
12
ns
Document #: 38-06054 Rev. *B
Page 9 of 30
CY7C09569V
CY7C09579V
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[10, 11, 12, 13]
tCH1
tCYC1
tCL1
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
tSB
tSC
tHB
tHC
B0-3
R/W
An
ADDRESS
An+1
An+2
An+3
tCKHZ
tDC
tCD1
DATAOUT
Qn
Qn+1
Qn+2
tDC
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[10, 11, 12, 13]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tSB
tHC
tHB
B0-3
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
10. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
11. ADS = VIL, CNTEN = VIL and CNTRST = VIH.
12. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.
13. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06054 Rev. *B
Page 10 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Read Cycle for Flow-Through Output (FT/PIPE = VIL)[10, 12, 14, 15, 16]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
tSW
tSA
tHW
tHA
ADS
R/W
An
ADDRESS
An
An+1
tDC
tCD1
DATAOUT
Qn
Qn
1st
Cycle
tCKLZ
OE
An+1
2nd
Cycle
Qn+1
Qn+1
1st
Cycle
2nd
Cycle
tDC
LOW
Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH)[10, 12, 14, 15, 16]
tCYC2
tCH2
tCL2
CLK
CE
tHC
tSC
R/W
tSW tHW
ADS
ADDRESS
An
An+1
An
tSA tHA
tCD2
tCD2
tCD2
tCLKZ
DATAOUT
Qn
Qn
1 Latency
OE
An+1
LOW
tDC
1st Cycle
Qn+1
tDC
2nd Cycle
tDC
1st Cycle
Notes:
14. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
15. See table “Right Port Operation“ for data output on first and subsequent cycles.
16. CNTEN = VIL. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at VIH level
all the time except when loading the initial external address (i.e. ADS = VIL only required when reading or writing the first Byte or Word).
Document #: 38-06054 Rev. *B
Page 11 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bank Select Pipelined Read[17, 18]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
ADDRESS(B2)
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[18, 19, 20, 21, 22]
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tHD
tSD
DATAINL
VALID
tCCS
CLKR
R/WR
ADDRESSR
tCD1
tSW
tSA
tHW
tHA
NO
MATCH
MATCH
tCWDD
DATAOUTR
tCD1
VALID
tDC
VALID
tDC
Notes:
17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
18. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = VIL, CNTRST = VIH.
19. The same waveforms apply for a right port write to flow-through left port read.
20. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=VIL; CNTRST= VIH.
21. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
22. If tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1 (tCWDD does not apply in this case).
Document #: 38-06054 Rev. *B
Page 12 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[13, 23, 24, 25]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
An+1
An+2
tHA
DATAIN
An+2
An+3
An+4
tSD tHD
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DATAOUT
READ
Qn+3
NO OPERATION
WRITE
READ
Notes:
23. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
24. CE = ADS = CNTEN = VIL; CNTRST = VIH.
25. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06054 Rev. *B
Page 13 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE Controlled)[11, 23, 24, 25]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
READ
Document #: 38-06054 Rev. *B
WRITE
READ
Page 14 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Pipelined Read-to-Write-to-Read (OE = VIL)[11, 14, 15, 16, 24, 25, 26]
tCYC2
CLK
tCH2 tCL2
CE
tSC
tHC
tSW
tHW
R/W
ADDRESS
tSA
An+1
An
An
An+2
An+1
An+3
An+2
An+4
An+3
An+4
tHA
ADS
1st Word
Qn
Qn
DATAOUT
tCKLZ
2nd Word
1st Word
2nd Word
Qn+3
Qn+3
tCKHZ
tCD2
tCD2
1st Word
2nd Word
Dn+2
Dn+2
DATAIN
READ
READ
1st Cycle
READ
2nd Cycle
tSD
tHD
No
Operation
WRITE
WRITE
1st Cycle
2nd Cycle
tCD2
READ
READ
1st Cycle
tDC
READ
2nd Cycle
Note:
26. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document #: 38-06054 Rev. *B
Page 15 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[11, 13, 14, 15, 24, 25]
tCH1
tCYC1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
DATAIN
An+2
An+2
tSD
tHA
An+3
tHD
Dn+2
tCD1
tCD1
DATAOUT
An+4
tCD1
Qn
Qn+1
tDC
tCKHZ
READ
tCD1
Qn+3
tCKLZ
NO
OPERATION
WRITE
tDC
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[11, 13, 23, 24, 25]
tCH1
tCYC1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
DATAIN
tSD
tHA
DATAOUT
Dn+2
tDC
tCD1
tHD
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
READ
Document #: 38-06054 Rev. *B
WRITE
READ
Page 16 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Flow-Through Read-to-Write-to-Read (OE = VIL)[11, 14, 15, 16, 24, 25, 26]
tCYC1
tCH1 tCL1
CLK
tSC
tHC
CE
tSW tHW
tSW tHW
R/W
tSA
ADDRESS
tHA
An
An
An+1
An+1
An+1
An+1
An+2
An+1
ADS
tSD
DATAIN
Dn+1
tCD1
tCKHZ
tDC
tCD1
Qn
DATAOUT
Document #: 38-06054 Rev. *B
Dn+1
1st Word
2nd Word
tCD1
tCD1
2nd Word
READ
2nd Cycle
Qn+1
Qn+1
Qn
1st Word
READ
1st Cycle
tHD
No
Operation
WRITE
1st Cycle
WRITE
2nd Cycle
tCKLZ
tDC
READ
1st Cycle
READ
2nd Cycle
Page 17 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[27]
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Qn
tDC
READ WITH COUNTER
Qn+1
Qn+2
COUNTER HOLD
Qn+3
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[27]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
tCD1
Qx
Qn
Qn+1
tDC
READ
EXTERNAL
ADDRESS
Qn+2
Qn+3
Qn+4
COUNTER HOLD
READ WITH COUNTER
tDC
tCD1
READ tDC
WITH
tCD1
COUNTER
Note:
27. CE = OE = VIL; R/W = CNTRST = VIH.
Document #: 38-06054 Rev. *B
Page 18 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[28, 29]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Notes:
28. CE= B0 = B1 = B2 = B3 = R/W = VIL; CNTRST = VIH.
29. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = VILand CNTRST=VIH.
Document #: 38-06054 Rev. *B
Page 19 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[11, 23, 30, 31, 32]
tCYC2
tCH2 tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tSW
An
1
0
Ap
Am
An
ADDRESS
tHA
Ap
Am
tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD tHD
DATAIN
D0
tCD2
tCD2
DATAOUT
[32
Q0
Qn
Q1
tCKLZ
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS An
READ
ADDRESS Am
Notes:
30. CE = B0 = B1 = B2 = B3 = VIL.
31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATAOUT should be in the High-Impedance state during
a valid WRITE cycle.
Document #: 38-06054 Rev. *B
Page 20 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Counter Reset (Flow-Through Outputs)[23, 25, 30, 31, 32]
tCH2
tCYC2
tCL2
CLK
tSA
An
ADDRESS
INTERNAL
ADDRESS
tHA
AX
0
tSW
tHW
tSD
tHD
An+1
An
1
An+1
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
D0
DATAIN
tCD1
DATAOUT
Q0
COUNTER
RESET
Document #: 38-06054 Rev. *B
WRITE
ADDRESS 0
READ
ADDRESS 0
Qn
Q1
READ
ADDRESS 1
READ
ADDRESS n
Page 21 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read of State of Address Counter [33, 34, 35]
tCYC2
tCH2 tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL
ADDRESS
An
An+2
An+1
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tSCN tHCN
DATAOUT
Qx-1
Qx-2
LOAD
EXTERNAL
ADDRESS
tSCN tHCN
tCA2
Qn
An
READ WITH
COUNTER
tDC
READ COUNTER ADDRESS
Flow-Through Read of State of Address Counter
Qn+1
COUNTER
HOLD
Qn+2
READ WITH COUNTER
[33, 34, 36]
tCYC1
tCH1 tCL1
CLK
tSA tHA
ADDRESS
An
INTERNAL
ADDRESS
An
An+1
An+3
An+2
tSAD tHAD
ADS
tSCN tHCN tSCN
tSAD
tHCN
tHAD
CNTEN
tCA1
DATAOUT
Qn
Qx
tSCN
An
tDC
LOAD
EXTERNAL
ADDRESS
READ COUNTER ADDRESS
Qn+1
Qn+2
tHCN
Qn+3
READ WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
Notes:
33. CE = OE = VIL; R/W = CNTRST = VIH.
34. When reading ADDRESSOUT in x9 Bus Match mode, readout of AN is extended by 1 cycle.
35. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3
consecutive cycles for x9 mode.
36. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
Document #: 38-06054 Rev. *B
Page 22 of 30
CY7C09569V
CY7C09579V
Read/Write and Enable Operation[37, 38, 39]
Inputs
OE
CLK
Outputs
CE
R/W
I/O0–I/O35
Operation
Deselected[40]
X
H
X
High-Z
X
L
L
DIN
L
L
H
DOUT
Read[40]
L
X
High-Z
Outputs Disabled
H
X
Write
Address Counter Control Operation[37, 41]
Address
Previous
Address
X
CLK
OE
R/W
ADS
CNTEN
CNTRST
Mode
Operation
X
X
X
X
X
L
Reset
Counter Reset
An
X
X
X
L
L
H
Load
Address Load into Counter
An
An
L
H
L
H
H
Hold +
Read
External Address Blocked Counter Address Readout
X
An
X
X
H
H
H
Hold
External Address Blocked Counter Disabled
X
An
X
X
H
L
H
Increment Counter Increment
Notes:
37. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
38. ADS, CNTEN, CNTRST = “Don’t Care.”
39. OE is an asynchronous input signal.
40. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
41. Counter operation is independent of CE.
Document #: 38-06054 Rev. *B
Page 23 of 30
CY7C09569V
CY7C09579V
Right Port Configuration[26, 42]
BM
SIZE
Configuration
I/O Pins used
0
0
x36
I/O0R–35R
1
0
x18
I/O0R–17R
1
1
x9
I/O0R–8R
Right Port Operation[43]
Configuration
BE
Data on 1st Cycle
Data on 2nd Cycle
Data on 3rd Cycle
Data on 4th Cycle
x18
0
DQ0R–17R
DQ18R–35R
-
-
x18
1
DQ18R–35R
DQ0R–17R
-
-
x9
0
DQ0R–8R
DQ9R–17R
DQ18R–26R
DQ27R–35R
x9
1
DQ27R–35R
DQ18R–26R
DQ9R–17R
DQ0R–8R
Readout of Internal Address Counter[44]
Configuration
Address on 1st Cycle
I/O Pins used on 1st Cycle
Address on 2nd
Cycle
I/O Pins used on 2nd
Cycle
Left Port x36
A0L–14L
I/O3L–17L
-
-
Right Port x36
A0R–14R
I/O3R–17R
-
-
Right Port x18
WA, A0R–14R
I/O2R–17R
-
-
Right Port x9
A6R–14R
I/O0R–8R
BA, WA, A0R–5R
I/O1R–8R
Left Port Operation
Control Pin
Effect
B0
I/O0–8 Byte Control
B1
I/O9–17 Byte Control
B2
I/O18–26 Byte Control
B3
I/O27–35 Byte Control
Notes:
42. In x36 mode, BE input is a “Don’t Care.”
43. DQ represents data output of the chip.
44. x18 and x9 configuration apply to right port only.
Document #: 38-06054 Rev. *B
Page 24 of 30
CY7C09569V
CY7C09579V
The CY7C09569V/09579V Dual-Port RAM (DPRAM) contains
on-chip address counters (one for each port) for the
synchronous members of the product family. Besides the main
x36 format, the right port allows bus matching (x18 or x9, userselectable). An internal sub-counter provides the extra
addresses required to sequence out the 36-bit word in 18-bit
or 9-bit increments. The sub-counter counts up in the “Little
Endian” mode, and counts down if the user has chosen the
“Big Endian” mode. The address counter is required to be in
increment mode in order for the sub-counter to sequence out
the second word (in x18 mode) or the remaining three bytes
(in x9 mode).
word, or 9-bit byte format for data I/O. The data lines are
divided into four lanes, each consisting of 9 bits (byte-size data
lines).
BE
x36
/
CY7C09569V
CY7C09579V
16K/32Kx36
Dual Port
9
/
9
/
9
/
9
/
For a x36 format (the only active format on the left port), each
address counter in the CY7C09579V uses addresses (A0–14).
BUS MODE
Counter Operation
x9, x18, x36
/
BM SIZE
For the right port (allowing for the bus-matching feature), a
maximum of two address bits (out of a 2-bit sub-counter) are
added.
Figure 2. Bus Match Operation Diagram
1. ADSL/R (pin #23/86) is a port's address strobe, allowing the
loading of that port's burst counters if the corresponding
CNTENL/R pin is active as well.
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) and Big Endian Select (BE) to select the bus width
(long-word, word, or byte) and data sequencing arrangement
for the right port of the dual-port device. A logic “0” applied to
both the Bus Match Select (BM) pin and to the Bus Size Select
(SIZE) pin will select long-word (36-bit) operation. A logic “1”
level applied to the Bus Match Select (BM) pin will enable
whether byte or word bus width operation on the right port I/Os
depending on the logic level applied to the SIZE pin. The level
of Bus Match Select (BM) must be static throughout normal
device operation.
2. CNTENL/R (pin #25/84) is a port's count enable, provided
to stall the operation of the address input and utilize the
internal address generated by the internal counter for fast
interleaved memory applications; when asserted, the
address counter will increment on each positive transition
of that port's clock signal.
3. CNTRSTL/R (pin #24/85) is a port's burst counter reset.
A new read-back (Hold+Read Mode) feature has been added,
which is different between the left and right port due to the bus
matching feature provided only for the right port. In read-back
mode the internal address of the counter will be read from the
data I/Os as shown in Figure 1.
_______
ADS
______________
Address Read-Back
COUNTER
Address
CY7C09569V
CY7C09579V
RAM
ARRAY
CNTRST
____________
CNTEN
I/O’s
Figure 1. Counter Operation Diagram
Bus Match Operation
The right port of the CY7C09569V/09579V 16K/32Kx36 dualport SRAM can be configured in a 36-bit long-word, 18-bit
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement. A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
The Big Endian Select (BE) pin is a multiple-function pin during
word or byte bus selection (BM = 1). BE is used in Big Endian
Select mode to determine the order by which bytes (or words)
of data are transferred through the right data port. A logic “0”
on the BE pin will select Little Endian data sequencing
arrangement and a logic “1” on the BE pin will select a Big
Endian data sequencing arrangement. Under these circumstances, the level on the BE pin should be static throughout
dual-port operation.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit)
operation. In this mode, the right port’s I/O operates essentially
in an identical fashion to the left port of the dual-port SRAM.
However no Byte Select control is available. All 36 bits of the
long-word are shifted into and out of the right port’s I/O buffer
stages. All read and write timing parameters may be identical
with respect to the two data ports. When the right port is
configured for a long-word size, Big- Endian Select (BE) pin
has no application and their inputs are “Don’t Care”[45] for the
external user.
Note:
45. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
Document #: 38-06054 Rev. *B
Page 25 of 30
CY7C09569V
CY7C09579V
Word (18-bit) Operation
Byte (9-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Big Endian (BE) pin
determines the right port data I/O sequencing order (Big
Endian or Little Endian).
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, 9 bits of data are ported
through I/O0R–8R.
During word (18-bit) bus size operation, a logic LOW applied
to the BE pin will select Little Endian operation. In this case,
the least significant data word is read from the right port first
or written to the right port first. A logic “1” on the BE pin during
word (18-bit) bus size operation will select Big Endian
operation resulting in the most significant data word being
transferred through the right port first. Internally, the data will
be stored in the appropriate 36-bit LSB or MSB I/O memory
location. Device operation requires a minimum of two clock
cycles to read or write during word (18-bit) bus size operation.
An internal sub-counter automatically increments the right port
multiplexer control when Little or Big Endian operation is in
effect.
Document #: 38-06054 Rev. *B
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin
(BE) under these circumstances will determine the right port
data I/O sequencing order (Big or Little Endian). A logic LOW
applied to the BE pin during byte (9-bit) bus size operation will
select Little Endian operation. In this case, the least significant
data byte is read from the right port first or written to the right
port first. A logic “1” on the BE pin during byte (9-bit) bus size
operation will select Big Endian operation resulting in the most
significant data word to be transferred through the right port
first. Internally, the data will be stored in the appropriate 36-bit
LSB or MSB I/O memory location. Device operation requires
a minimum of four clock cycles to read or write during byte (9bit) bus size operation. An internal sub-counter automatically
increments the right port multiplexer control when Little or Big
Endian operation is in effect. When transferring data in byte (9bit) bus match format, the unused I/O pins (I/O9RQ–35R) are
three-stated.
Page 26 of 30
CY7C09569V
CY7C09579V
Ordering Information
16K x36 3.3V Synchronous Dual-Port SRAM
Speed
(MHz)
100
83
67
Ordering Code
CY7C09569V-100AC
Package
Name
Package Type
Operating
Range
A144
144-Pin Thin Quad Flat Pack
Commercial
CY7C09569V-100AXC
A144
144-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C09569V-100BBC
BB172
172-Ball Ball Grid Array (BGA)
Commercial
CY7C09569V-83AC
A144
144-Pin Thin Quad Flat Pack
Commercial
CY7C09569V-83AXC
A144
144-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C09569V-83BBC
BB172
172-Ball Ball Grid Array (BGA)
Commercial
144-Pin Thin Quad Flat Pack
Commercial
172-Ball Ball Grid Array (BGA)
Commercial
CY7C09569V-67AC
CY7C09569V-67BBC
A144
BB172
32K x36 3.3V Synchronous Dual-Port SRAM
Speed
(MHz)
100
83
67
Ordering Code
CY7C09579V-100AC
Package
Name
Package Type
Operating
Range
A144
144-Pin Thin Quad Flat Pack
Commercial
CY7C09579V-100AXC
A144
144-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C09579V-100BBC
BB172
172-Ball Ball Grid Array (BGA)
Commercial
CY7C09579V-83AC
A144
144-Pin Thin Quad Flat Pack
Commercial
CY7C09579V-83AXC
A144
144-Pin Pb-Free Thin Quad Flat Pack
Commercial
CY7C09579V-83AI
A144
144-Pin Thin Quad Flat Pack
Industrial
CY7C09579V-83AXI
A144
144-Pin Pb-Free Thin Quad Flat Pack
Industrial
CY7C09579V-83BBC
BB172
172-Ball Ball Grid Array (BGA)
Commercial
CY7C09579V-83BBI
BB172
172-Ball Ball Grid Array (BGA)
Industrial
144-Pin Thin Quad Flat Pack
Commercial
172-Ball Ball Grid Array (BGA)
Commercial
CY7C09579V-67AC
CY7C09579V-67BBC
Document #: 38-06054 Rev. *B
A144
BB172
Page 27 of 30
CY7C09569V
CY7C09579V
Package Diagrams
144-Pin Plastic Thin Quad Flat Pack (TQFP) A144
144-Pin Pb-Free Plastic Thin Quad Flat Pack (TQFP) A144
51-85047-*A
Document #: 38-06054 Rev. *B
Page 28 of 30
CY7C09569V
CY7C09579V
Package Diagrams (continued)
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
FLeX36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-06054 Rev. *B
Page 29 of 30
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C09569V
CY7C09579V
Document History Page
Document Title: CY7C09569V/CY7C09579V 3.3 16K/ 32K x 36 FLEx36™ Synchronous Dual-Port Static RAM
Document Number: 38-06054
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110213
12/16/01
SZV
Change from Spec number: 38-00743 to 38-06054
*A
122304
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
349775
See ECN
RUY
Added Pb-Free Information
Document #: 38-06054 Rev. *B
Page 30 of 30
Similar pages