Intersil CXD2570 1-bit ad/da converter for audio application Datasheet

HI2570, CXD2570
®
O
NOT REC
September 1997
E D FO R
M ME N D
SIGNS
NEW DE
1-Bit AD/DA
Converter For Audio Application
Features
Description
• Two-Channel AD/DA Converters and Their Each Decimation and Oversampling Digital Filter in a Single Chip
• Simplified External Parts with a Built-In Analog Circuit
Around AD Converter
• Distortion
- ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.015%
- DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.009% (-3dB)
• S/N Ratio (Typical Values when FS = 16kHz)
- ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80dB
- DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90dB
• Ripple in the Digital Filter Pass Band . . . . . . . ±0.05dB<
• Attenuation in the Digital Filter Rejection Band. . . 45dB>
The HI2570, CXD2570 is a 1-bit stereo AD/DA converter
which uses a 2nd-order ∆∑ system noise shaper. This LSI is
especially suited for sampling frequency between 8kHz and
32kHz.
Function
• Data Can Be Input/Output at Rate of 1xFS with a BuiltIn Digital Filter
• Multi-Channel Systems can be Connected Using Several
HI2570, CXD2570Qs
• The 32-Slot Serial Data Interface Enables Independent
Selection of Data Frontward Truncation/Rearward
Truncation and MSB First/LSB First
Applications
- Telephones, TV Conference Systems, Language Laboratory Equipment, TV Game Equipment and Electronic Musical Instrument
• 512FS/1024FS (when FS = 8 to 16kHz) or 256FS/512FS/
768FS/1024FS (When FS = 16 to 32kHz) Can be Used
as the Master Clock
Ordering Information
PART
NUMBER
TEMP.
RANGE ( oC)
PACKAGE
• The Sampling Frequency of Not Only 8kHz or 16kHz, but
32kHz or 44.1kHz Can Be Used for Audio Equipment
PKG. NO.
HI2570JCQ
-20 to 55
48 Ld MPQF
Q48.12x12-S
CXD2570Q
-20 to 55
48 Ld MPQF
Q48.12x12-S
• Various Frequency Divided Clocks are Output for LSIs
Connected
Pinout
DASL0
WO
DASL1
DVDD
SUB
NC
NC
AIN1
AVDD1
AVSS1
AOUT1+
AVSS3
HI2570, CXD2570 (48 LEAD MQFP)
TOP VIEW
AVDD3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
AOUT1-
2
3
35
34
XSL1
4
33
32
31
MLSL
MASL
DVSS
30
29
SOUT
XCLK
XVDD
XTLI
5
XTLO
8
9
26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
XSL0
SIN
BCK
LRCK
MS
DVDD
CLR
TEST
DVSS
XMCK2
NC
SUB
NC
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
AOUT2+
AVDD4
10
AVDD2
AOUT2-
28
27
AVSS2
AIN2
XVSS
AVSS4
6
7
AVSS4
AVSS3
UCLK
XSL2
File Number
4122.1
®
File Number
2
HI2570, CXD2570
Pin Descriptions
PIN NO.
SYMBOL
I/O
DESCRIPTION
1
AVDD3
—
Analog power supply for channel-1 DA converter
2
AOUT1 (-)
O
Analog reversed phase output of channel-1 DA converter
3
AVSS3
—
Analog GND for channel-1 DA converter
4
UCLK
O
Outputs a 1/2 frequency divider of clock input from oscillation pin XTLI (Pin 7).
User clock output for the externally connected ICs.
5
XCLK
O
256Fs/512Fs clock output. This provides the master clock for ICs operating in
the slave mode when multiple CXD2570Qs are connected.
6
XVDD
—
Digital power supply for the master clock
7
XTLI
I
Crystal oscillation circuit input. Connects the crystal oscillator selected by the
crystal selector pins XSL0 to 2 (Pins 34, 35 and 36). To input an external master clock, this pin is used.
8
XTLO
O
Crystal oscillation circuit output. Connects the crystal oscillator selected by the
crystal selector pins XSL0 to 2 (Pins 34, 35 and 36).
9
XVSS
—
Digital GND for the master clock
10
AVSS4
—
Analog GND for channel-2 DA converter
11
AOUT2 (-)
O
Analog reversed phase output of channel-2 DA converter
12
AVDD4
—
Analog power supply for channel-2 DA converter
13
AOUT2 (+)
O
Analog forward phase output of channel-2 DA converter
14
AVSS4
—
Analog GND for channel-2 DA converter
15
AVSS2
—
Analog GND for channel-2 AD converter
16
AIN1
17
AVDD2
—
18
NC
—
19
SUB
—
20
NC
—
21
DVSS
—
Digital GND
22
XMCK2
O
IC measurement. Normally, Low is output.
23
TEST
I
Test. Normally, fixed at Low. Equipped with a pull-down resistor.
24
CLR
I
System clear input. Normally, fixed at High; cleared at Low. Equipped with a
pull-up resistor.
25
DVDD
26
MS
27
LRCK
I
—
Analog input of channel-2 converter
Analog power supply for channel-2 AD converter
Connected to the substrate in the IC (having the same potential as power supply). Connect this pin to GND via a capacitor on the external printed wiring
board.
Digital power supply.
I
Master/slave mode switching input. High = Master mode. Low = Slave mode.
Equipped with a pull-up resistor.
I/O
Sampling frequency clock pin of serial I/O. Outputs in master mode (when Pin
26 is High). Inputs in slave mode (when Pin 26 is Low). Transfers channel-1
data at High; transfers channel-2 data at Low.
3
HI2570, CXD2570
Pin Descriptions
PIN NO.
(Continued)
SYMBOL
I/O
DESCRIPTION
28
BCK
I/O
Serial bit transfer clock for serial input data SIN or serial output data SOUT
(64FS). Outputs in master mode (when Pin 26 is High). Inputs in slave mode
(when Pin 26 is Low). Retrieves serial input data at
; send serial output data at
.
29
SIN
I
Serial data input of 2-channel sampling. The data format is 2’s complement,
and consists of 32-bit slot.
30
SOUT
O
Serial data output of 2-channel per sampling. The data format is 2’s complement, and consists of 32-bit slot.
31
DVSS
—
Digital GND
32
MASL
I
Selects whether 16-bit serial data is applied in the first 16-bits or the last 16bit of 32-bit slot in serial I/O. High = Frontward truncation; Low = Rearward
truncation
33
MLSL
I
Selects whether 16-bit serial data is input/output at LSB first or MSB first in
serial I/O. High = MSB first; Low = LSB first
34
XSL0
I
Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency
to be input from XTLI (Pin 7).
35
XSL1
I
Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency
to be input from XTLI (Pin 7).
36
XSL2
I
Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency
to be input from XTLI (Pin 7).
37
DASL0
I
IC measurement. Normally, fixed at High.
38
DASL1
I
IC measurement. Normally fixed at Low.
39
WO
I
Window masked when High; window open when Low (forced synchronization). Equipped with a pull-up resistor.
40
DVDD
—
41
NC
—
42
NC
—
43
SUB
—
Connected to the substrate in the IC (having the same potential as power supply). Connect this pin to GND via capacitor on the external printed wiring
board.
44
AVDD1
—
Analog power supply for channel-1 AD converter
45
AIN1
46
Digital power supply
I
Analog input of channel-1 AD converter
AVSS1
—
Analog GND for channel-1 AD converter
47
AVSS3
—
Analog GND for channel-1 DA converter
48
AOUT1 (+)
O
Analog forward phase output of channel-1 DA converter
4
HI2570, CXD2570
Absolute Maximum Ratings TA = 25oC
I/O Capacitance
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . VSS–0.5V to 7.0V
Input Voltage (V 1). . . . . . . . . . . . . . . . . . .VSS – 0.5V to VDD + 0.5V
Output Voltage (V 0) . . . . . . . . . . . . . . . . . VSS – 0.5V to VDD + 0.5V
Operating Temperature (Topr) . . . . . . . . . . . . . . . . . . -20oC to 75οC
Storage Temperature (Tstg . . . . . . . . . . . . . . . . . . . -55oC to 150oC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN
.—
Input Pin (CIN)
Output Pin (COUT) . . . . . . . . . . . . . . . . . . . —
Bidirectional Pin (CI/O) . . . . . . . . . . . . . . . . -—
TYP
—
—
—
MAX
9pF
11pF
11 pF
Measurement conditions: V DD = V1 = 0V, f = 1MHz
Recommended Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN
Supply Voltage (Note 1) (VDD)
4.5V
Ambient Temperature (TA) . . . . . . . . . . . . . . -20oC
Sampling Frequency (Note 2) (FS). . . . . . . . 7kHz
TYP
5.0V
—
—
MAX
5.5V
+75oC
33kHz
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other poser supplies.
turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. this precaution, however, does not apply when turning off the power supplies.
2. Although the device can operate with FS frequencies such as FS = 44.1kHz or 48kHz, its analog characteristics deteriorate to extent.
When used at only these FS frequencies, the CXD255Q is recommended that is pin-compatible with the CXD2570Q.
Electrical Specifications
PARAMETER
DC Characteristics
Input Voltage
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
APPLICABLE
PINS
AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = -20oC to 75oC
0.7VDD
VIHC
—
—
V
*1
Ò
Ò
0.3VDD
VIN
Analog Input
V SS
—
VDD
V
*2
VOH1
IOH = -2mA
VDD -0.5
—
VDD
V
*3
VOL1
IOL = 4mA
0
—
0.4
VOH2
IOH = -4mA
VDD -0.5
—
VDD
V
*4
VOL2
IOL = 4mA
0
—
0.4
VOH3
IOH = -12mA
VDD/2
—
VDD
V
*5
VOL3
IOL = 16mA
0
—
VDD/2
VOH4
IOH = -2mA
VDD -0.8
—
VDD
V
*6
VOL4
IOL = 4mA
0
—
0.4
VILC
Output Voltage
PART NUMBER
OR GRADE
Input Leak Current 1
ILI1
-10
—
10
µA
*7
Input Leak Current 2
ILI2
-40
—
40
µA
*8
Input Leak Current 3
ILI3
-20
-50
-12-
µA
*9
Input Leak Current 4
ILI4
20
50
120
µA
*10
Output Leak Current
ILZ
Feedback Resistance
RFB
VIN = VSS or VDD
IDD
(Note 3)
Supply Current
AC Characteristics
-40
—
40
µA
*11
250K
1M
‘2.5M
Ω
*12
—
43
60
mA
AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = -20oC to 75oC
SIN Setup Time
tsus
SIN Hold Time
ths
LRCK Setup Time
tsul
Slave mode
10
—
—
ns
15
—
—
ns
10
—
—
ns
LRCK Hold Time
thl
Slave mode
15
—
—
ns
LRCK Delay Time
tdl
Master mode
CL = 130pF
-40
—
30
ns
5
HI2570, CXD2570
Electrical Specifications
(Continued)
PARAMETER
TEST
CONDITIONS
SYMBOL
SOUT Delay Time
tds
SOUT Data Recovery Time
tzd
SOUT Data Erase Time
tdz
XTLI Pulse Width for Low Period twl
PART NUMBER
OR GRADE
MIN
CL = 60pF
FS = 16kHz, 256Fs
(XSL0 = XSL1 = XSL2 = Low
TYP
MAX
UNITS
9
—
65
ns
7
—
42
ns
6
—
40
ns
40
—
200
ns
APPLICABLE
PINS
NOTES:
3. This includes current consumption at load resistance (RL = 3.9Ω). Fs = 16kHz
*1 All input pins except AIN1 and AIN2, and when bidirectional pins (BCK and LRCK) are input mode.
*2 AIN1, AIN2
*3 XCLK, XMCK2, SOUT
*4 AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK
*5 XTLO
*6 When bidirectional pins (BCK and LRCK) are output mode
*7 All input pins except AIN1 and AIN2
*8 When directional pins (BCK and LRCK) are input mode
*9 MS, WO, CLR
*10 TEST
*11 SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK
*12 Resistance between XTLO and XTLI
Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = 25oC
ITEM
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADC + DAC Connection Overall Characteristics. Measured under the following conditions unless otherwise specified.
Input waveform = 1kHz sine wave, 1.4Vrms (= 0dB), R IN = 16kΩ
XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz)
CLR = MS = WO = open (= 5V)
SOUT and SIN directly coupled.
S/N Ratio
8kHz LPF
74
80
—
dB
THD + N
8kHz LPF
—
0.015
0.03
%
Dynamic Range
1kHz, -60dB
8kHz LPF
74
80
—
dB
Channel Separation
1kHz, 0dB
—
97
—
dB
—
0.1
—
dB
Gain Difference Between Channels
Gain
RL = 3.9kW
-3
0
+3
dB
Input Level
RIN = 0Ω
—
0.1
—
Vrms
RIN = 16Ω
—
1.4
—
Vrms
DC Offset (ADC Output)
—
030F
—
Hex
ADC Input Impedance
—
1.2
kΩ
DAC characteristics in a single unit. Measured under the following conditions unless otherwise specified.
Input data = 1kHz sine wave, full scale (= 0dB)
XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz
CLR = WO = open (= 5V), MS = GND
S/N Ratio
8kHz LPF
84
90
—
dB
THD + N
8kHz LPF, -3dB
—
0.009
0.03
%
Dynamic Range
1kHz, -60dB
8kHz LPF
82
88
—
dB
6
HI2570, CXD2570
Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = 25oC (Continued)
ITEM
Channel Separation
CONDITIONS
MIN.
TYP.
MAX.
UNIT
—
100
—
dB
—
0.05
—
dB
1.80
1.93
2.10
Vrms
1kHz, 0dB
Gain Difference Between Channels
Output Level
RL = 3.9kW
Description of Functions
1. Serial data interface
[Related pins] LRCK, BCK, SOUT, SIN, MASL, MLSL
The serial data format is common for both SIN (DA converter
input) and SOUT (AD converter output), consisting of two
channels per sampling serial data represented by 2’s complement. Each channel is divided into 32-bit slots, of which
16 bits are handled as data.
XSL0
CRYSTAL
OSCILLATOR
FREQUENCY
XSL2
XSL1
XCLK
UCLK
L
L
L
L
L
H
256Fs
256Fs
128Fs
512Fs
256Fs
L
H
L
768Fs
256Fs
256Fs
384Fs
L
H
H
1024Fs
256Fs
512Fs
MASL is used to select whether the 16 bits of valid data is
placed in the first or the last half of the 32-bit slots.
*The CXD2555Q, which has the same pin configuration with
this IC is recommended when using only Fs = 32kHz to
48kHz.
Similarly, MLSL is used to select whether the serial data is
arranged at MSB first of LSB first.
4. Crystal oscillator frequency selection (FS = 8kHz to
16kHz)
MASL
[Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK,
XCLK
MLSL
High
Frontward truncation
High
MSB first
Low
Rearward truncation
Low
LSB first
With XSL2 fixed High, the device can be operated with lowFs frequencies. In this case, the frequency of the crystal
oscillator can be selected by setting a combination of XSL0
and XSL1 accordingly.
2. Master mode/slave mode
[Related pins] MS, LRCK, BCK
When using the CXD2570Q in multiple units or in a pair with
DA converter such as the CXD2558M, one of these
CXD2570Qs should be in the master mode to serve as the
source of clocks LRCK and BCK.
The other ICs including CXD2570Qs are used in the slave
mode, with their clocks LRCK and BCK supplied by the master CXD2570Q.
MS
MODE
LRCK AND BCK I/O
High
Master mode
Output
Low
Slave mode
Input
XSL2
XSL1
XSL0
CRYSTAL
OSCILLATOR
FREQUENCY*
H
L
L
512Fs
H
L
H
—
—
—
H
H
L
1024Fs
512Fs
512Fs
H
H
H
—
—
—
XCLK
UCLK
512Fs
256Fs
5. A/D converter input level
Any desired input level VIN (m . 0.1Vrms) can be selected by
adjusting RIN to generate the full-scale output of the AD converter.
VIN generation of full-scale output varies with the products,
and calculate the V IN maximum level (approximately -3dB
below the full-scale) using the following equation to input the
signal.
3. Crystal oscillator frequency selection (FS = 16kHz to
48kHz)
[Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK,
XCLK
(1) Fs = 16kHz to 48kHz (XSL2 = Low)
RIN = 1230 ⋅ VIN [Vrms] -1200 (Ω)
(2) Fs = 8 to 16kHz (XSL2 = High)
RIN = 26600 ⋅ VIN [Vrms] -1200 (Ω)
By setting a combination of XSL0 and XSL1, with XSL2 fixed
low, the frequency of the external crystal oscillator connected to XTLI and XTLO can be selected. In this case,
XCLK outputs a clock whose frequency is always 256 times
Fs, and UCLK outputs a clock that is half the crystal oscillator frequency.
6. D/A converter output level
To change the D/A converter output level, adjust R15, R17,
R30 and R32 in Application Circuit on page.
When supplying the master clock from some other external
source, not a crystal oscillator, use XTLI for this clock input
and leave XTLO open.
7
HI2570, CXD2570
Metric Plastic Quad Flatpack Packages (MQFP)
D
Q48.12x12-S
D1
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES
SYMBOL
E E1
e
PIN 1
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.081
0.100
2.05
2.55
-
A1
0.000
0.011
0.00
0.30
-
B
0.008
0.017
0.20
0.45
5
D
0.587
0.618
14.90
15.70
2
D1
0.469
0.488
11.90
12.40
3, 4
E
0.587
0.618
14.90
15.70
2
E1
0.469
0.488
11.90
12.40
3, 4
L
0.028
0.043
0.70
1.10
-
N
48
48
6
e
0.032 BSC
0.80 BSC
Rev. 0 2/96
-H-
A
SEATING
PLANE
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
0.15
2. Dimensions D and E to be determined at seating plane -C- .
0.006
0.24
3. Dimensions D1 and E1 to be determined at datum plane -H- .
-C-
M
4. Dimensions D1 and E1 do not include mold protrusion.
5. Dimension B does not include dambar protrusion.
B
6. “N” is the number of terminal positions.
A1
0o-10o
L
0.10/0.25
0.004/0.010
8
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