Hanbit HMD4M36M9AG-5 16mbyte(4mx36) fast page with parity mode, 2k/4k refresh Datasheet

HANBiT
HMD4M36M9G, HMD4M36M9AG
16Mbyte(4Mx36) Fast Page with Parity Mode, 2K/4K Refresh
Part No. HMD4M36M9G, HMD4M36M9AG
GENERAL DESCRIPTION
The HMD4M36M9G is a 4M x 36 bit dynamic RAM high-density memory module. The module HMD4M36M9G consists
of eight CMOS 4M x 4 bit DRAMs in 24-pin SOJ packages and one CMOS 4M x 4 bit Quad /CAS DRAM in 28-pin SOJ
package mounted on a 72-pin, double-sided, FR-4-printed circuit board.
A 0.1uF or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The module is a single
In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets.
All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
PIN ASSIGNMENT
w Part Identification
HMD4M36M9G- 2,048 cycles/32ms Ref. Gold Lead
PIN
HMD4M36M9AG-4,096 cycles/64ms Ref. Gold Lead
w Access times : 50ns, 60ns
w High-density 16MByte design
w 2,048 Cycles/32ms Ref.
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w Fast page mode operation
w /CAS-before-/RAS refresh capability
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
Vss
25
DQ24
49
DQ9
2
DQ0
26
DQ7
50
DQ27
3
DQ18
27
DQ25
51
DQ10
4
DQ1
28
A7
52
DQ28
5
DQ19
29
A11
53
DQ11
6
DQ2
30
Vcc
54
DQ29
7
DQ20
31
A8
55
DQ12
8
DQ3
32
A9
56
DQ30
9
DQ21
33
NC
57
DQ13
10
Vcc
34
/RAS2
58
DQ31
11
NC
35
DQ26
59
Vcc
12
A0
36
DQ8
60
DQ32
13
A1
37
DQ17
61
DQ14
50ns access
-5
14
A2
38
DQ35
62
DQ33
60ns access
-6
15
A3
39
Vss
63
DQ15
16
A4
40
/CAS0
64
DQ34
17
A5
41
/CAS2
65
DQ16
18
A6
42
/CAS3
66
NC
19
A10
43
/CAS1
67
Vss
20
DQ4
44
/RAS0
68
PD2
21
DQ22
45
NC
69
PD3
22
DQ5
46
NC
70
PD4
23
DQ23
47
/WE
71
NC
24
DQ6
48
NC
72
Vss
w Packages
72-pin SIMM
M
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
5
50ns
13ns
90ns
6
60ns
15ns
110ns
PRESENCE DETECT PINS
Pin
50ns
60ns
PD1
Vss
Vss
PD2
NC
NC
PD3
Vss
NC
PD4
Vss
NC
A0 – A11 : Address Input(4K Ref.)
A0 – A10 : Address Input(2K Ref.)
*A11 is used for only HMD4M36M9AG
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-1-
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HANBiT
HMD4M36M9G, HMD4M36M9AG
FUNCTIONAL BLOCK DIAGRAM
/CAS0
/RAS0
CAS
RAS
OE
W
CAS
RAS
OE
W
/CAS1
CAS
RAS
OE
W
CAS
RAS
OE
W
CAS0
CAS0
CAS0
CAS0
RAS
OE W
/CAS2
/RAS2
CAS
RAS
OE
W
CAS
RAS
OE
W
/CAS3
CAS
RAS
OE
W
CAS
RAS
OE
W
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ0-DQ3
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ4-DQ7
U1
U2
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U4
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U5
U3
DQ0
DQ1
DQ2
DQ3
A0-A10(A11)
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U6
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ18-DQ21
DQ22-DQ25
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ27-DQ30
DQ0
DQ1
DQ2
A0-A10 (A11)DQ3
DQ31-DQ34
U9
Vss
-2-
DQ8
DQ17
DQ26
DQ35
U8
Vcc
URL:www.hbe.co.kr
REV.1.0 (August.2002)
DQ13-DQ16
U7
/WE
A0-A10(A11)
DQ9-DQ12
0.1uF
or
Capacitor
for each DRAM
0.22uF
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M36M9G, HMD4M36M9AG
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 7.0V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 7.0V
Power Dissipation
PD
9W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage reference to VSS, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
ICC1
-5
-
990
mA
-6
-
900
mA
-
18
mA
-5
-
990
mA
-6
-
900
mA
-5
-
810
mA
-6
-
720
mA
-
9
mA
-5
-
990
mA
-6
-
900
mA
Il(L)
-40
45
µA
IO(L)
-40
5
µA
VOH
2.4
-
V
VOL
-
0.4
V
ICC2
ICC3
ICC4
ICC5
ICC6
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
ICC2 : Standby Current ( /RAS=/CAS=VIH )
ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
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REV.1.0 (August.2002)
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HANBiT
HMD4M36M9G, HMD4M36M9AG
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V
VOH : Output High Voltage Level (IOH= -5mA )
VOL : Output Low Voltage Level (IOL = 4.2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while
/RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
o
( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A10)
CIN1
-
70
pF
Input Capacitance (/WE)
C IN2
-
80
pF
Input Capacitance (/RAS0, /RAS2)
CIN3
-
80
pF
Input Capacitance (/CAS0-/CAS3)
CIN4
-
40
pF
Input / Output Capacitance (DQ0-35)
CDQ
-
17
pF
AC CHARACTERISTICS
o
( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.)
-5
STANDARD OPERATION
-6
SYMBOL
UNIT
MIN
MAX
MAX
Random read or write cycle time
tRC
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
13
15
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
0
Output buffer turn-off delay
tOFF
0
13
0
15
ns
Transition time (rise and fall)
tT
3
50
3
50
ns
/RAS precharge time
tRP
30
/RAS pulse width
tRAS
50
/RAS hold time
tRSH
13
15
ns
/CAS hold time
tCSH
50
60
ns
/CAS pulse width
tCAS
13
10K
15
10K
ns
/RAS to /CAS delay time
tRCD
20
37
20
45
ns
/RAS to column address delay time
tRAD
15
25
15
30
ns
/CAS to /RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
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REV.1.0 (August.2002)
-4-
90
MIN
110
ns
0
ns
40
10K
60
ns
10K
ns
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M36M9G, HMD4M36M9AG
Column address hold time
tCAH
10
10
ns
Column address hold referenced to /RAS
tAR
40
45
ns
Column Address to /RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
40
45
ns
Write command pulse width
tWP
10
10
ns
Write command to /RAS lead time
tRWL
15
15
ns
Write command to /CAS lead time
tCWL
13
15
ns
Data-in set-up time
tDS
0
0
ns
Data-in hold time
tDH
10
15
ns
Data-in hold referenced to /RAS
tDHR
40
45
ns
Refresh period 2K Ref.
tREF
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
Fast page mode cycle time
tPC
35
40
ns
/CAS precharge time (Fast page)
tCP
10
10
ns
/RAS pulse width (Fast page)
tRASP
50
/WE to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/WE to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
32
32
30
200K
35
60
200K
ns
ns
ns
/CAS precharge(C-B-R counter test)
tCPT
20
20
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF.
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or
VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and
the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by t AA.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M36M9G, HMD4M36M9AG
TIMING DIAGRAM
Please refer to attached timing diagram chart (I)
PACKAGING INFORMATION
SIMM DESIGN
2.54 mm MIN
0.25 mm MAX
1.27±0.08mm
1.27 mm
Gold : 1.04±0.10 mm
Solder:0.914±0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMD4M36M9G-5
16MByte
4MX 36bit
72 Pin-SIMM
HMD4M36M9AG-5
16MByte
4MX 36bit
72 Pin-SIMM
HMD4M36M9G-6
16MByte
4MX 36bit
72 Pin-SIMM
HMD4M36M9AG-6
16MByte
4MX 36bit
72 Pin-SIMM
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REV.1.0 (August.2002)
-6-
Refresh
Cycle
2,048 Cycles
32ms Ref.
4,096 Cycle
64ms Ref.
2,048 Cycles
32ms Ref.
4,096 Cycle
64ms Ref.
Vcc
Speed
5.0V
50ns
5.0V
50ns
5.0V
60ns
5.0V
60ns
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REV.1.0 (August.2002)
HMD4M36M9G, HMD4M36M9AG
-7-
HANBit Electronics Co.,Ltd.
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