Linear LTC4267CGN Power over ethernet ieee 802.3af pd interface with integrated switching regulator Datasheet

LTC4267
Power over Ethernet
IEEE 802.3af PD Interface with
Integrated Switching Regulator
DESCRIPTIO
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FEATURES
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Complete Power Interface Port for IEEE 802®.3af
Powered Device (PD)
Onboard 100V, 400mA UVLO Switch
Precision Dual Level Inrush Current Limit
Integrated Current Mode Switching Regulator
Onboard 25kΩ Signature Resistor with Disable
Programmable Classification Current (Class 0-4)
Thermal Overload Protection
Power Good Signal
Integrated Error Amplifier and Voltage Reference
Low Profile 16-Pin SSOP and 3mm × 5mm DFN
Packages
The LTC®4267 combines an IEEE 802.3af compliant Powered Device (PD) interface with a current mode switching
regulator, providing a complete power solution for PD
applications. The LTC4267 integrates the 25kΩ signature
resistor, classification current source, thermal overload protection, signature disable and power good signal along with
an undervoltage lockout optimized for use with the IEEErequired diode bridge. The precision dual level input current
limit allows the LTC4267 to charge large load capacitors
and interface with legacy PoE systems.
The current mode switching regulator is designed for
driving a 6V rated N-channel MOSFET and features programmable slope compensation, soft-start, and constant
frequency operation, minimizing noise even with light
loads. The LTC4267 includes an onboard error amplifier
and voltage reference allowing use in both isolated and
nonisolated configurations.
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APPLICATIO S
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IP Phone Power Management
Wireless Access Points
Security Cameras
Power over Ethernet
The LTC4267 is available in space saving, low profile
16-pin SSOP or DFN packages.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Class 2 PD with 3.3V Isolated Power Supply
PA1133
SBM1040
3.3V
1.5A
10k
–48V
FROM
DATA PAIR
+
HD01
VPORTP
–
SMAJ58A
PWRGD
LTC4267
NGATE
–48V
FROM
SPARE PAIR
HD01
–
+
PVCC
+
4.7µF
•
5µF
MIN
•
320µF
MIN
CHASSIS
Si3440
10k
0.1µF
+
PVCC
SENSE
RCLASS
RCLASS
68.1Ω
1%
ITH/RUN
PVCC
470
6.8k
VFB
SIGDISA
PGND
VPORTN
POUT
0.1Ω
22nF
BAS516
100k
PS2911
TLV431
60.4k
4267 TA01
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LTC4267
W W
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ABSOLUTE
AXI U RATI GS
(Note 1)
VPORTN with Respect to VPORTP Voltage ... 0.3V to –100V
POUT, SIGDISA, ⎯P⎯W⎯R⎯G⎯D
Voltage..................... VPORTN + 100V to VPORTN –0.3V
PVCC to PGND Voltage (Note 2)
Low Impedance Source ........................... –0.3V to 8V
Current Fed .......................................... 5mA into PVCC
RCLASS Voltage .................VPORTN + 7V to VPORTN – 0.3V
⎯P⎯W⎯R⎯G⎯D Current .....................................................10mA
RCLASS Current.....................................................100mA
NGATE to PGND Voltage ...........................–0.3V to PVCC
VFB, ITH/RUN to PGND Voltages ................ –0.3V to 3.5V
SENSE to PGND Voltage .............................. –0.3V to 1V
NGATE Peak Output Current (<10μs) ..........................1A
Operating Ambient Temperature Range
LTC4267C ................................................ 0°C to 70°C
LTC4267I .............................................–40°C to 85°C
Junction Temperature
GN Package ...................................................... 150°C
DHC Package .................................................... 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ITH/RUN
1
16 VFB
PGND
2
15 PGND
NGATE
3
14 SENSE
PVCC
4
13 VPORTP
RCLASS
5
12 SIGDISA
NC
6
11 PWRGD
VPORTN
7
10 POUT
NC
8
9
17
ORDER PART
NUMBER
PGND 1
ITH/RUN 2
LTC4267CDHC
LTC4267IDHC
NC
DHC16 PACKAGE
16-LEAD (3mm × 5mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43.5°C/W
EXPOSED PAD (PIN 17) MUST BE SOLDERED
TO ELECTRICALLY ISOLATED PCB HEAT SINK
DFN PART*
MARKING
4267
4267
ORDER PART
NUMBER
TOP VIEW
16 PGND
15 VFB
NGATE 3
14 SENSE
PVCC 4
13 VPORTP
LTC4267CGN
LTC4267IGN
RCLASS 5
12 SIGDISA
NC 6
11 PWRGD
VPORTN 7
PGND 8
GN PART
MARKING
10 POUT
9
PGND
4267
4267I
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 150°C, θJA = 90°C/W
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF
Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VPORTN
Supply Voltage
Maximum Operating Voltage
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
Voltage with Respect to VPORTP Pin
(Notes 4, 5, 6)
PVCC Turn-On Voltage
PVCC Turn-Off Voltage
PVCC Hysteresis
PVCC Shunt Regulator Voltage
Voltage with Respect to PGND
Voltage with Respect to PGND
VTURNON – VTURNOFF
IPVCC = 1mA, VITH/RUN = 0V, Voltage
with Respect to PGND
VTURNON
VTURNOFF
VHYST
VCLAMP1mA
MIN
●
●
●
●
●
●
●
●
●
–1.5
–12.5
–34.8
–29.3
7.8
4.6
1.5
8.3
TYP
–36.0
–30.5
8.7
5.7
3.0
9.4
MAX
UNITS
–57
–9.5
–21
–37.2
–31.5
9.2
6.8
V
V
V
V
V
V
V
V
V
10.3
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LTC4267
ELECTRICAL
CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
VMARGIN
IVPORTN_ON
IPVCC_ON
VCLAMP1mA – VTURNON Margin
VPORTN Supply Current when ON
PVCC Supply Current
Normal Operation
Start-Up
IVPORTN_CLASS VPORTN Supply Current
During Classification
∆ICLASS
Current Accuracy
During Classification
RSIGNATURE
Signature Resistance
CONDITIONS
●
VPORTN = –48V, POUT, ⎯P⎯W⎯R⎯G⎯D, SIGDISA Floating
(Note 7)
VITH/RUN – PGND = 1.3V
PVCC – PGND = VTURNON – 100mV
VPORTN = –17.5V, POUT Tied to VPORTP, RCLASS,
SIGDISA Floating (Note 8)
●
10mA < ICLASS < 40mA, –12.5V ≤ VPORTN ≤ –21V
(Notes 9, 10)
●
–1.5V ≤ VPORTN ≤ – 9.5V, POUT Tied to VPORTP,
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
●
●
Invalid Signature Resistance
–1.5V ≤ VPORTN ≤ – 9.5V, SIGDISA and POUT Tied to
VPORTP, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
●
VIH
Signature Disable
High Level Input Voltage
With Respect to VPORTN
High Level Invalidates Signature (Note 11)
●
VIL
Signature Disable
Low Level Input Voltage
With Respect to VPORTN
Low Level Enables Signature
●
RINPUT
Signature Disable, Input Resistance
Power Good Output Low Voltage
With Respect to VPORTN
I = 1mA VPORTN = –48V,
⎯P⎯W⎯R⎯G⎯D Referenced to VPORTN
VPORTN = –48V, Voltage between VPORTN and POUT (Note 10)
POUT Falling
POUT Rising
VPORTN = 0V, ⎯P⎯W⎯R⎯G⎯D FET Off, V⎯P⎯W⎯R⎯G⎯D = 57V
I = 300mA, VPORTN = –48V, Measured from
VPORTN to POUT (Note 10)
PVCC – PGND = VTURNON + 100mV
VITH/RUN – PGND = 0V, PVCC – PGND = 8V
Referenced to PGND, PVCC – PGND = 8V (Note 12)
PVCC – PGND = 8V (Note 12)
ITH/RUN Pin Load = ±5µA (Note 12)
●
Power Good Trip Point
VPG _FALL
VPG_RISE
IPG_LEAK
RON
VITHSHDN
ITHSTART
VFB
IFB
gm
∆VO(LINE)
Power Good Leakage Current
On-Resistance
Shutdown Threshold (at ITH/RUN)
Start-Up Current Source at ITH/RUN
Regulated Feedback Voltage
VFB Input Current
Error Amplifier Transconductance
∆VO(LOAD)
Output Voltage Line Regulation
Output Voltage Load Regulation
IPOUT_LEAK
POUT Leakage
ILIM_HI
Input Current Limit, High Level
ILIM_LO
fOSC
DCON(MIN)
Input Current Limit, Low Level
Oscillator Frequency
Minimum Switch On Duty Cycle
DCON(MAX)
Maximum Switch On Duty Cycle
VTURNOFF < PVCC < VCLAMP (Note 12)
ITH/RUN Sinking 5µA, PVCC – PGND = 8V (Note 12)
ITH/RUN Sourcing 5µA, PVCC – PGND = 8V (Note 12)
VPORTN = 0V, Power MOSFET Off,
POUT = 57V (Note 13)
VPORTN = –48V, POUT = –43V (Note 14, 15)
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
VPORTN = –48V, POUT = –43V (Note 14, 15)
VITH/RUN – PGND = 1.3V, PVCC – PGND = 8V
VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,
PVCC – PGND = 8V
VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,
PVCC – PGND = 8V
TYP
0.05
0.6
●
●
RINVALID
VPG_OUT
MIN
0.35
240
40
0.5
23.25
9
3
1.3
2.7
1.5
3.0
●
1.0
●
●
●
0.15
0.2
0.780
200
0.28
0.3
0.800
10
333
V
mA
350
90
0.65
µA
µA
mA
±3.5
%
26.00
kΩ
11.8
kΩ
57
V
0.45
V
0.5
kΩ
V
1.7
3.3
1
1.6
2
0.45
0.4
0.812
50
500
0.05
3
3
●
●
●
●
UNITS
3
100
●
●
●
MAX
V
V
µA
Ω
Ω
V
µA
V
nA
µA/V
150
mV/V
mV/µA
mV/µA
µA
325
300
80
180
375
375
140
200
6
400
400
180
240
8
mA
mA
mA
kHz
%
70
80
90
%
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LTC4267
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
tRISE
tFALL
VIMAX
ISLMAX
tSFST
TSHUTDOWN
NGATE Drive Rise Time
NGATE Drive Fall Time
Peak Current Sense Voltage
Peak Slope Compensation Output Current
Soft-Start Time
Thermal Shutdown Trip Temperature
CLOAD = 3000pF, PVCC – PGND = 8V
CLOAD = 3000pF, PVCC – PGND = 8V
RSL = 0, PVCC – PGND = 8V (Note 16)
PVCC – PGND = 8V (Note 17)
PVCC – PGND = 8V
(Notes 14, 18)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: PVCC internal clamp circuit self regulates to 9.4V with respect to
PGND.
Note 3: The LTC4267 operates with a negative supply voltage in the range
of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface
are always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and
a “rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4267 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics section are with respect to this product pins and
are designed to meet IEEE 802.3af specifications when these diode drops
are included. See the Application Information section.
Note 5: Signature resistance is measured via the two-point ΔV/ΔI method
as defined by IEEE 802.3af. The PD signature resistance is offset from the
25kΩ to account for diode resistance. With two series diodes, the total PD
resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4267
pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and
–9.5V.
Note 6: The PD interface includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD
will power up from a voltage source with 20Ω series resistance on the first
trial.
Note 7: Dynamic Supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 8: IVPORTN_CLASS does not include classification current
programmed at the RCLASS pin. Total current in classification mode will be
IVPORTN_CLASS + ICLASS (See note 9).
Note 9: ICLASS is the measured current flowing through RCLASS. ΔICLASS
accuracy is with respect to the ideal current defined as ICLASS = 1.237/
MIN
●
90
TYP
40
40
100
5
1.4
140
MAX
115
UNITS
ns
ns
mV
µA
ms
°C
RCLASS. The current accuracy does not include variations in RCLASS
resistance. The total classification current for a PD also includes the IC
quiescent current (IVPORTN_CLASS). See Applications Information.
Note 10: For the DHC package, this parameter is assured by design and
wafer level testing.
Note 11: To disable the 25kΩ signature, tie SIGDISA to VPORTP or hold
SIGDISA high with respect to VPORTN. See Applications Information.
Note 12: The switching regulator is tested in a feedback loop that servos
VFB to the output of the error amplifier while maintaining ITH/RUN at the
midpoint of the current limit range.
Note 13: IPOUT_LEAK includes current drawn through POUT by the power
good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.
Note 14: The LTC4267 PD Interface includes thermal protection. In the
event of an overtemperature condition, the PD interface will turn off
the switching regulator until the part cools below the overtemperature
limit. The LTC4267 is also protected against thermal damage from
incorrect classification probing by the PSE. If the LTC4267 exceeds the
overtemperature threshold, the classification load current is disabled.
Note 15: The PD interface includes dual level input current limit. At turnon, before the POUT load capacitor is charged, the PD current level is set
to a low level. After the load capacitor is charged and the POUT – VPORTN
voltage difference is below the power good threshold, the PD switches to
high level current limit. The PD stays in high level current limit until the
input voltage drops below the UVLO turn-off threshold.
Note 16: Peak current sense voltage is reduced dependent on duty cycle
and an optional external resistor in series with the SENSE pin (RSL). For
details, refer to the programmable slope compensation feature in the
Applications Information section.
Note 17: Guaranteed by design.
Note 18: The PD interface includes overtemperature protection that is
intended to protect the device from momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
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LTC4267
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
0.5
Input Current vs Input Voltage
50
TA = 25°C
Input Current vs Input Voltage
12.0
TA = 25°C
CLASS 4
11.5
0.3
0.2
INPUT CURRENT (mA)
40
INPUT CURRENT (mA)
INPUT CURRENT (mA)
0.4
CLASS 3
30
CLASS 2
20
CLASS 1
0.1
CLASS 1 OPERATION
10
11.0
85°C
10.5
–40°C
10.0
9.5
CLASS 0
0
–2
0
–10
–4
–6
–8
VPORTN VOLTAGE (V)
0
–10
–20
–30
–40
VPORTN VOLTAGE (V)
–50
4267 G01
SIGNATURE RESISTANCE (kΩ)
INPUT CURRENT (mA)
0
–40
–50
–45
–55
VPORTN VOLTAGE (V)
–60
26
LTC4267 + 2 DIODES
24
LTC4267 ONLY
IEEE LOWER LIMIT
23
22
V1: –1
V2: –2
–3
–4
4267 G04
–7
–5
–8
–6
VPORTN VOLTAGE (V)
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
1
0
–1
–2
–40
–9
–10
–20
60
0
20
40
TEMPERATURE (C)
4267 G06
POUT Leakage Current
120
TA = 25°C
Current Limit vs Input Voltage
400
VIN = 0V
TA = 25°C
85°C
– 40°C
1
CURRENT LIMIT (mA)
90
VOUT CURRENT (µA)
VPG_OUT (V)
3
2
80
4267 G05
Power Good Output Low Voltage
vs Current
4
2
RESISTANCE = ∆V = V2 – V1
∆I I2 – I1
27 DIODES: S1B
TA = 25C
IEEE UPPER LIMIT
25
–22
Normalized UVLO Threshold vs
Temperature
28
EXCLUDES ANY LOAD CURRENT
TA = 25°C
1
–20
–18
–16
VPORTN VOLTAGE (V)
4267 G03
Signature Resistance vs
Input Voltage
2
–14
4267 G02
Input Current vs Input Voltage
3
9.0
–12
–60
NORMALIZED UVLO THRESHOLD (%)
0
60
30
HIGH CURRENT MODE
300
200
85°C
LOW CURRENT MODE
– 40°C
0
0
2
6
4
CURRENT (mA)
8
10
4267 G07
0
0
20
40
POUT PIN VOLTAGE (V)
60
4267 G08
100
–40
–50
–45
–55
VPORTN VOLTAGE (V)
–60
4267 G09
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LTC4267
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TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage vs
Temperature
240
801.0
PVCC = 8V
TA = 25°C
PVCC ≤ VCLAMP1mA
800.8
800.6
VFB VOLTAGE (mV)
VFB VOLTAGE (mV)
808
OSCILLATOR FREQUENCY (kHz)
812
Oscillator Frequency vs
Temperature
Reference Voltage vs
Supply Voltage
804
800
796
800.4
800.2
800.0
799.8
799.6
799.4
792
PVCC = 8V
(WITH RESPECT TO PGND)
230
220
210
200
190
799.2
788
–50 –30 –10
10
30
50
70
90
6
TEMPERATURE (°C)
6.5
PVCC Undervoltage Lockout
Thresholds vs Temperature
PVCC UNDERVOLTAGE LOCKOUT (V)
OSCILLATOR FREQUENCY (kHz)
208
206
204
202
200
198
196
194
192
190
6.5
7.5
8
8.5
7
PVCC SUPPLY VOLTAGE (V)
9
10.0
10.0
9.5
9.9
9.0
9.8
VTURNON
8.5
9.7
8.0
9.6
7.5
7.0
6.5
9.5
9.4
9.3
VTURNOFF
6.0
IPVCC = 1mA
9.2
5.5
9.1
5.0
–50 –30 –10 10 30 50 80
TEMPERATURE (°C)
9.0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
4267 G16
4267 G14
110
PVCC Shunt Regulator Voltage vs
Temperature
PVCC (V)
TA = 25°C
90
4267 G13
4267 G11
Oscillator Frequency vs
Supply Voltage
6
9.5
8
7.5
8.5
9
PVCC SUPPLY VOLTAGE (V)
7
4267 G10
210
180
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
799.0
110
90
110
4267 G17
IPVCC Supply Current vs
Temperature
265
260
PVCC = 8V
VITH/RUN = 1.3V
SUPPLY CURRENT (µA)
255
250
245
240
235
230
225
220
215
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
4267 G18
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LTC4267
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TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up IPVCC Supply Current vs
Temperature
ITH/RUN Start-Up Current Source
vs Temperature
450
SHUTDOWN THRESHOLD (mV)
50
40
30
20
10
600
ITH/RUN PIN CURRENT SOURCE (nA)
PVCC = VTURNON – 0.1V
400
350
300
250
200
150
0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
100
–50 –30 –10
10
30
50
70
90
500
400
300
200
100
0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
4267 G21
Soft-Start Time vs Temperature
4.0
PVCC = 8V
3.5
110
3.0
SOFT-START TIME (ms)
115
105
100
95
90
85
80
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
PVCC = VTURNON + 0.1V
VITH/RUN = 0V
4267 G20
Peak Current Sense Voltage vs
Temperature
120
110
TEMPERATURE (°C)
4267 G19
SENSE PIN VOLTAGE (mV)
START-UP SUPPLY CURRENT (µA)
60
ITH/RUN Shutdown Threshold vs
Temperature
2.5
2.0
1.5
1.0
0.5
90
110
4267 G22
0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
4267 G23
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LTC4267
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PI FU CTIO S
(GN/DHC)
ITH/RUN (Pin 2/Pin 1): Current Threshold/Run Input. This
pin performs two functions. It serves as the switching
regulator error amplifier compensation point as well as
the run/shutdown control input. Nominal voltage range is
0.7V to 1.9V. Forcing the pin below 0.28V with respect to
PGND causes the controller to shut down.
⎯ W
⎯ R
⎯ G
⎯ D
⎯ (Pin 11/Pin 11): Power Good Output, Open-Drain.
P
Indicates that the PD MOSFET is on and the switching
regulator can start operation. Low impedance indicates
power is good. ⎯P⎯W⎯R⎯G⎯D is high impedance during detection, classification and in the event of a thermal overload.
⎯P⎯W⎯R⎯G⎯D is referenced to VPORTN.
PGND (Pin 1, 8, 9, 16/Pin 2, 15): Switching Regulator
Negative Supply. This pin is the negative supply rail for the
switching regulator controller and must be tied to POUT.
SIGDISA (Pin 12/Pin 12): Signature Disable Input. SIGDISA
allows the PD to present an invalid signature resistance
and remain inactive. Connecting SIGDISA to VPORTP lowers
the signature resistance to an invalid value and disables
all functions of the LTC4267. If unused, tie SIGDISA to
VPORTN.
NGATE (Pin 3/Pin 3): Gate Driver Output. This pin drives
the regulator’s external N-Channel MOSFET and swings
from PGND to PVCC.
PVCC (Pin 4/Pin 4): Switching Regulator Positive Supply.
This pin is the positive supply rail for the switching regulator and must be closely decoupled to PGND.
RCLASS (Pin 5/Pin 5): Class Select Input. Used to set the current value the PD maintains during classification. Connect
a resistor between RCLASS and VPORTN (see Table 2).
VPORTN (Pin 7/Pin 7): Negative Power Input. Tie to the
–48V input port through the input diodes.
POUT (Pin 10/Pin 10): Power Output. Supplies –48V to
the switching regulator PGND pin and any additional PD
loads through an internal power MOSFET that limits input
current. POUT is high impedance until the voltage reaches
the turn-on UVLO threshold. The output is then current
limited. See the Application Information section.
VPORTP (Pin 13/Pin 13): Positive Power Input. Tie to the
input port power return through the input diodes.
SENSE (Pin 14/Pin 14): Current Sense. This pin performs
two functions. It monitors the regulator switch current by
reading the voltage across an external sense resistor. It also
injects a current ramp that develops a slope compensation
voltage across an optional external programming resistor.
See the Applications Information section.
VFB (Pin 15/Pin 16): Feedback Input. Receives the feedback voltage from the external resistor divider across the
output.
NC (Pin 6/Pin 6, 8, 9): No Internal Connection.
Backside Connection (DHC Only, Pin 17): Exposed Pad.
This exposed pad must be soldered to an electrically isolated
and thermally conductive PC board heat sink.
4267fc
8
LTC4267
BLOCK DIAGRAM
VPORTP
PVCC
SIGDISA
CLASSIFICATION
CURRENT LOAD
1.237V
+
–
RCLASS
0.3µA 0.28V
25k
SIGNATURE
RESISTOR
EN
9k
800mV
REFERENCE
VCC
SHUNT
REGULATOR
+
SHUTDOWN
COMPARATOR
–
16k
PWRGD
CONTROL
CIRCUITS
+
+
EN
SHUTDOWN
SOFTSTART
CLAMP
POWER GOOD
375mA
PVCC <
VTURNON UNDERVOLTAGE
LOCKOUT
ERROR
AMPLIFIER
+
VFB
INPUT
CURRENT
LIMIT
–
CURRENT
COMPARATOR
R
Q
S
–
PVCC
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
NGATE
GATE
DRIVER
ITH/RUN
140mA
20mV
–
1.2V
VPORTN
200kHz
OSCILLATOR
SLOPE
COMP
CURRENT
RAMP
SENSE
POUT
PGND
4267 BD
BOLD LINE INDICATES HIGH CURRENT PATH
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OVERVIEW
The LTC4267 is partitioned into two major blocks: a
Powered Device (PD) interface controller and a current
mode flyback switching regulator. The Powered Device
(PD) interface is intended for use as the front end of a
PD adhering to the IEEE 802.3af standard, and includes
a trimmed 25kΩ signature resistor, classification current
source, and an input current limit circuit. With these
functions integrated into the LTC4267, the signature and
power interface for a PD can be built that meets all the
requirements of the IEEE 802.3af specification with a
minimum of external components.
The switching regulator portion of the LTC4267 is a constant frequency current mode controller that is optimized
for Power over Ethernet applications. The regulator is
designed to drive a 6V N-channel MOSFET and features
soft-start and programmable slope compensation. The
integrated error amplifier and precision reference give the
PD designer the option of using a nonisolated topology
without the need for an external amplifier or reference. The
LTC4267 has been specifically designed to interface with
both IEEE compliant Power Sourcing Equipment (PSE)
and legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. By setting
the initial inrush current limit to a low level, a PD using
the LTC4267 minimizes the current drawn from the PSE
during start-up. After powering up, the LTC4267 switches
to the high level current limit, thereby allowing the PD to
consume up to 12.95W if an IEEE 802.3af PSE is present.
This low level current limit also allows the LTC4267 to
charge arbitrarily large load capacitors without exceeding
the inrush limits of the IEEE 802.3af specification. This
dual level current limit provides the system designer with
flexibility to design PDs which are compatible with legacy
PSEs while also being able to take advantage of the higher
power available in an IEEE 802.3af system.
Using an LTC4267 for the power and signature interface
functions of a PD provides several advantages. The
LTC4267 current limit circuit includes an onboard 100V,
400mA power MOSFET. This low leakage MOSFET is
4267fc
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specified to avoid corrupting the 25kΩ signature resistor
while also saving board space and cost. In addition, the inrush current limit requirement of the IEEE 802.3af standard
can cause large transient power dissipation in the PD. The
LTC4267 is designed to allow multiple turn-on sequences
without overheating the miniature 16-lead package. In the
event of excessive power cycling, the LTC4267 provides
thermal overload protection to keep the onboard power
MOSFET within its safe operating area.
DETECTION V1
VPORTN (V)
–10
UVLO
TURN-ON
– 30
UVLO
TURN-OFF
– 50
TIME
τ = RLOAD C1
POUT (V)
– 10
UVLO
OFF
– 20
– 30
UVLO
ON
UVLO
OFF
dV = ILIM_LO
C1
dt
– 40
The LTC4267 PD interface has several modes of operation depending on the applied input voltage as shown in
Figure 1 and summarized in Table 1. These modes satisfy
the requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the VPORTN pin and must
be negative relative to the VPORTP pin. Voltages in the data
sheet for the PD interface portion of the LTC4267 are with
respect to VPORTP while the voltages for the switching
regulator are referenced to PGND. It is assumed that PGND
is tied to POUT. Note the use of different ground symbols
throughout the data sheet.
– 50
TIME
PWRGD (V)
– 10
POWER
BAD
– 20
POWER
GOOD
POWER
BAD
– 30
– 40
PWRGD TRACKS
VPORTN
– 50
CURRENT
LIMIT, ILIM_LO
ILIM_LO
PD CURRENT
INPUT VOLTAGE
(VPORTN with RESPECT to VPORTP) LTC4267 MODE OF OPERATION
0V to – 1.4V
Inactive
–1.5V to –9.5V**
25kΩ Signature Resistor Detection
–9.8V to –12.4V
Classification Load Current Ramps up
from 0% to 100%
–12.5V to UVLO*
Classification Load Current Active
UVLO* to –57V
Power Applied to Switching Regulator
*VPORTN UVLO includes hysteresis.
Rising input threshold ≅ – 36.0V
Falling input threshold ≅ –30.5V
**Measured at LTC4267 pin. The LTC4267 meets the IEEE 802.3af 10V
minimum when operating with the required diode bridges.
– 20
– 40
OPERATION
Table 1. LTC4267 Operational Mode
as a Function of Input Voltage
TIME
DETECTION V2
CLASSIFICATION
LOAD, ILOAD (UP TO ILIM_HI)
ICLASS
CLASSIFICATION
ICLASS
TIME
DETECTION I2
DETECTION I1
VOLTAGES WITH RESPECT TO VPORTP
I1 =
V1 – 2 DIODE DROPS
25kΩ
V2 – 2 DIODE DROPS
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
I2 =
ILIM_LO = 140mA (NOMINAL), ILIM_HI = 375mA (NOMINAL)
PSE
ILOAD =
VOUT
(UP TO ILIM_HI)
RLOAD
IIN
RCLASS VPORTP
VIN R
CLASS
LTC4267
R9
RLOAD
VOUT
C1
PWRGD
VPORTN
POUT
4267 F01
PGND
Figure 1. Output Voltage, ⎯P⎯W⎯R⎯G⎯D and PD
Current as a Function of Input Voltage
4267fc
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Series Diodes
The signature range extends below the IEEE range to accommodate the voltage drop of the two diodes. The IEEE
specification requires the PSE to use a ΔV/ΔI measurement
technique to keep the DC offset of these diodes from affecting the signature resistance measurement. However,
the diode resistance appears in series with the signature
resistor and must be included in the overall signature
resistance of the PD. The LTC4267 compensates for the
two series diodes in the signature path by offsetting the
resistance so that a PD built using the LTC4267 will meet
the IEEE specification.
The IEEE 802.3af-defined operating modes for a PD reference the input voltage at the RJ45 connector on the PD.
The PD must be able to accept power of either polarity
at each of its inputs, so it is common to install diode
bridges (Figure 2). The LTC4267 takes this into account
by compensating for these diode drops in the threshold
points for each range of operation. A similar adjustment
is made for the UVLO voltages.
Detection
During detection, the PSE will apply a voltage in the
range of –2.8V to –10V on the cable and look for a 25kΩ
signature resistor. This identifies the device at the end of
the cable as a PD. With the terminal voltage in this range,
the LTC4267 connects an internal 25kΩ resistor between
the VPORTP and VPORTN pins. This precision, temperature
compensated resistor presents the proper signature to
alert the PSE that a PD is present and desires power to be
applied. The internal low-leakage UVLO switch prevents
the switching regulator circuitry from affecting the detection signature.
In some applications it is necessary to control whether or
not the PD is detected. In this case, the 25kΩ signature
resistor can be enabled and disabled with the use of the
SIGDISA pin (Figure 3). Disabling the signature via the
SIGDISA pin will change the signature resistor to 9kΩ
(typical) which is an invalid signature per the IEEE 802.3af
specification. This invalid signature is present for PD input
voltages from –2.8V to –10V. If the input rises above –10V,
the signature resistor reverts to 25kΩ to minimize power
dissipation in the LTC4267. To disable the signature, tie
SIGDISA to VPORTP. Alternately, the SIGDISA pin can be
driven high with respect to VPORTN. When SIGDISA is high,
all functions of the PD interface are disabled.
The LTC4267 is designed to compensate for the voltage
and resistance effects of the IEEE required diode bridge.
RJ45
1
2
3
POWERED DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
6
TX+
T1
TX–
BR1
RX+
TO PHY
RX–
VPORTP
4
SPARE+
LTC4267
BR2
5
D3
4
7
8
8
SPARE–
VPORTN
4267 F02
Figure 2. LTC4267 PD Front End Using
Diode Bridges on Main and Spare Inputs
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CURRENT PATH
LTC4267
TO
PSE
VPORTP
9k
25k SIGNATURE
RESISTOR
16k
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
SIGNATURE DISABLE
SIGDISA
LTC4267
RCLASS
VPORTP
RCLASS
VPORTN
VPORTN
4267 F03
4267 F04
V
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4267
PSE CURRENT MONITOR
Figure 3. 25k Signature Resistor with Disable
Classification
PD
Figure 4. IEEE 802.3af Classification Probing
Once the PSE has detected a PD, the PSE may optionally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
to identify lower power PDs and allocate less power for
these devices. The IEEE 802.3af specification defines five
classes (Table 2) with varying power levels. The designer
selects the appropriate classification based on the power
consumption of the PD. For each class, there is an associated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current to determine the proper classification and
PD power requirements.
During classification (Figure 4), the PSE presents a fixed
voltage between –15.5V and –20.5V to the PD. With the
input voltage in this range, the LTC4267 asserts a load
current from the VPORTP pin through the RCLASS resistor.
The magnitude of the load current is set by the RCLASS
resistor. The resistor values associated with each class
are shown in Table 2. Note that the switching regulator
will not interfere with the classification measurement since
the LTC4267 has not passed power to the regulator.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4267 RCLASS Resistor Selection
Maximum
Nominal
Power Levels
Classification
at Input of PD
Load Current
Class
Usage
(W)
(mA)
0
Default
0.44 to 12.95
<5
1
Optional
0.44 to 3.84
10.5
2
Optional
3.84 to 6.49
18.5
3
Optional
6.49 to 12.95
28
4
Reserved
Reserved*
40
*Class 4 is currently reserved and should not be used.
PSE
LTC4267
RCLASS
Resistor
(Ω, 1%)
Open
124
68.1
45.3
30.9
The IEEE 802.3af specification limits the classification
time to 75ms because a significant amount of power is
dissipated in the PD. The LTC4267 is designed to handle the
power dissipation for this time period. If the PSE probing
exceeds 75ms, the LTC4267 may overheat. In this situation,
the thermal protection circuit will engage and disable the
classification current source in order to protect the part.
The LTC4267 stays in classification mode until the input
voltage rises above the UVLO turn-on voltage.
VPORTN Undervoltage Lockout
The IEEE specification dictates a maximum turn-on voltage
of 42V and a minimum turn-off voltage of 30V for the PD.
In addition, the PD must maintain large on-off hysteresis
to prevent resistive losses in the wiring between the PSE
and the PD from causing start-up oscillation. The LTC4267
incorporates an undervoltage lockout (UVLO) circuit that
monitors the line voltage at VPORTN to determine when
to apply power to the integrated switching regulator
(Figure 5). Before the power is applied to the switching
regulator, the POUT pin is high impedance and sitting at
the ground potential since there is no charge on capacitor
C1. When the input voltage rises above the UVLO turn-on
threshold, the LTC4267 removes the detection and classification loads and turns on the internal power MOSFET.
C1 charges up under the LTC4267 current limit control
and the POUT pin transitions from 0V to VPORTN. This
sequence is shown in Figure 1. The LTC4267 includes
a hysteretic UVLO circuit on VPORTN that keeps power
applied to the load until the input voltage falls below the
UVLO turn-off threshold. Once the input voltage drops
below –30V, the internal power MOSFET is turned off and
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the classification current is reenabled. C1 will discharge
through the PD circuitry and the POUT pin will go to a high
impedance state.
LTC4267
TO
PSE
UNDERVOLTAGE
LOCKOUT
CIRCUIT
VPORTN
VPORTP
C1
5µF
MIN
+
PGND
POUT
INPUT
LTC4267
VOLTAGE
POWER MOSFET
0V TO UVLO*
OFF
>UVLO*
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –36V
FALLING INPUT THRESHOLD ≅ –30.5V
4267 F05
CURRENT-LIMITED
TURN ON
Figure 5. LTC4267 VPORTN Undervoltage Lockout
Input Current Limit
IEEE 802.3af specifies a maximum inrush current and also
specifies a minimum load capacitor between the VPORTP
and POUT pins. To control turn-on surge current in the
system, the LTC4267 integrates a dual level current limit
circuit with an onboard power MOSFET and sense resistor to provide a complete inrush control circuit without
additional external components. At turn-on, the LTC4267
will limit the input current to the low level, allowing the
load capacitor to ramp up to the line voltage in a controlled
manner.
The LTC4267 has been specifically designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. At turn-on
the LTC4267 current limit is set to the lower level. After C1
is charged up and the POUT – VPORTN voltage difference is
below the power good threshold, the LTC4267 switches
to the high level current limit. The dual level current limit
allows legacy PSEs with limited current sourcing capability
to power up the PD while also allowing the PD to draw full
power from an IEEE 802.3af PSE. The dual level current
limit also allows use of arbitrarily large load capacitors.
The IEEE 802.3af specification mandates that at turn-on
the PD not exceed the inrush current limit for more than
50ms. The LTC4267 is not restricted to the 50ms time
limit because the load capacitor is charged with a current
below the IEEE inrush current limit specification.
As the LTC4267 switches from the low to high level current
limit, the current will increase momentarily. This current
spike is a result of the LTC4267 charging the last 1.5V at
the high level current limit. When charging a 10µF capacitor, the current spike is typically 100µs wide and 125%
of the nominal low level current limit.
The LTC4267 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the system designer with the flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of
power is dissipated in the power MOSFET. The LTC4267
PD interface is designed to accept this thermal load and
is thermally protected to avoid damage to the onboard
power MOSFET. Note that in order to adhere to the IEEE
802.3af standard, it is necessary for the PD designer to
ensure the PD steady state power consumption falls within
the limits shown in Table 2. In addition, the steady state
current must be less than ILIM_HI.
Power Good
The LTC4267 PD Interface includes a power good circuit
(Figure 6) that is used to indicate that load capacitor C1
is fully charged and that the switching regulator can start
operation. The power good circuit monitors the voltage
across the internal UVLO power MOSFET and ⎯P⎯W⎯R⎯G⎯D is
asserted when the voltage falls below 1.5V. The power
good circuit includes hysteresis to allow the LTC4267 to
operate near the current limit point without inadvertently
disabling ⎯P⎯W⎯R⎯G⎯D. The MOSFET voltage must increase to
3V before ⎯P⎯W⎯R⎯G⎯D is disabled.
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4267 will depend on the magnitude of the voltage
step, the rise time of the step, the value of capacitor C1
and the switching regulator load. For fast rising inputs,
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LTC4267
PWRGD
R9
100k
THERMAL SHUTDOWN
UVLO
–
TO
PSE
+
PGND
+
–
C1
5µF
MIN
PWRGD
LTC4267
+
–48V
C1 R18
5µF 10k
100V
C15
0.047µF
D6
MMBD4148
LTC3803
GND
OPTIONAL
AUXILIARY
SWITCHING
REGULATOR
POUT
PGND
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP
300k
POUT
ITH/RUN
C17
+
PGND
VPORTN
Q1
FMMT2222
R9
100k
VPORTP
1.125V
300k
VPORTN
ITH/RUN
TO
PSE
ITH/RUN
PGND
RSTART
4267 F06
Figure 6. LTC4267 Power Good
PVCC
TO
PSE
the LTC4267 will attempt to quickly charge capacitor C1
using an internal secondary current limit circuit. In this
scenario, the PSE current limit should provide the overall
limit for the circuit. For slower rising inputs, the 375mA
current limit in the LTC4267 will set the charge rate of the
capacitor C1. In either case, the ⎯P⎯W⎯R⎯G⎯D signal may go
inactive briefly while the capacitor is charged up to the
new line voltage. In the design of a PD, it is necessary
to determine if a step in the input voltage will cause the
⎯P⎯W⎯R⎯G⎯D signal to go inactive and how to respond to this
event. In some designs, it may be desirable to filter the
⎯P⎯W⎯R⎯G⎯D signal so that intermittent power bad conditions
are ignored. Figure 7 demonstrates a method to insert a
lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the switching regulator with the ⎯P⎯W⎯R⎯G⎯D signal. If the
regulator is not disabled during the current-limited turn-on
sequence, the PD circuitry will rob current intended for
charging up the load capacitor and create a slow rising
input, possibly causing the LTC4267 to go into thermal
shutdown.
The ⎯P⎯W⎯R⎯G⎯D pin connects to an internal open drain, 100V
transistor capable of sinking 1mA. Low impedance to
VPORTN indicates power is good. ⎯P⎯W⎯R⎯G⎯D is high impedance during signature and classification probing and in
the event of a thermal overload. During turn-off, ⎯P⎯W⎯R⎯G⎯D
is deactivated when the input voltage drops below 30V.
In addition, ⎯P⎯W⎯R⎯G⎯D may go active briefly at turn-on for
fast rising input waveforms. ⎯P⎯W⎯R⎯G⎯D is referenced to the
VPORTN pin and when active, will be near the VPORTN potential. Connect the ⎯P⎯W⎯R⎯G⎯D pin to the switching regulator
circuitry as shown in Figure 7.
VPORTP
PWRGD
LTC4267
PGND
–48V
VPORTN
Q1
FMMT2222
R9
100k
+
CPVCC
C1 R18
5µF 10k
100V
C15
0.047µF
D6
MMBD4148
POUT
PGND
ALTERNATE ACTIVE-HIGH ENABLE FOR PVCC PIN
SEE APPLICATIONS INFORMATION SECTION
4267 F07
Figure 7. Power Good Interface Examples
PD Interface Thermal Protection
The LTC4267 PD Interface includes thermal overload
protection in order to provide full device functionality
in a miniature package while maintaining safe operating temperatures. Several factors create the possibility
of significant power dissipation within the LTC4267. At
turn-on, before the load capacitor has charged up, the
instantaneous power dissipated by the LTC4267 can be
as much as 10W. As the load capacitor charges up, the
power dissipation in the LTC4267 will decrease until it
reaches a steady-state value dependent on the DC load
current. The size of the load capacitor determines how
fast the power dissipation in the LTC4267 will subside. At
room temperature, the LTC4267 can typically handle load
capacitors as large as 800µF without going into thermal
shutdown. With large load capacitors, the LTC4267 die
temperature will increase by as much as 50°C during a
single turn-on sequence. If for some reason power were
removed from the part and then quickly reapplied so that
the LTC4267 had to charge up the load capacitor again, the
temperature rise would be excessive if safety precautions
were not implemented.
The LTC4267 PD interface protects itself from thermal
damage by monitoring the die temperature. If the die
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temperature exceeds the overtemperature trip point, the
current is reduced to zero and very little power is dissipated in the part until it cools below the overtemperature
set point. Once the LTC4267 has charged up the load
capacitor and the PD is powered and running, there will
be minor residual heating due to the DC load current of
the PD flowing through the internal MOSFET. The DHC
package offers superior thermal performance by including
an exposed pad that is soldered to an electrically isolated
heat sink on the printed circuit board.
During classification, excessive heating of the LTC4267
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4267, thermal overload circuitry will disable classification current if the die temperature exceeds
the overtemperature trip point. When the die cools down
below the trip point, classification current is reenabled.
The PD is designed to operate at a high ambient temperature and with the maximum allowable supply (57V).
However, there is a limit to the size of the load capacitor
that can be charged up before the LTC4267 reaches the
overtemperature trip point. Hitting the overtemperature
trip point intermittently does not harm the LTC4267, but it
will delay the completion of capacitor charging. Capacitors
up to 200µF can be charged without a problem over the
full operating temperature range.
Switching Regulator Main Control Loop
Due to space limitations, the basics of current mode
DC/DC conversion will not be discussed here. The reader
is referred to the detail treatment in Application Note 19
or in texts such as Abraham Pressman’s Switching Power
Supply Design.
In a Power over Ethernet System, the majority of applications involve an isolated power supply design. This
means that the output power supply does not have any
DC electrical path to the PD interface or the switching
regulator primary. The DC isolation is achieved typically
through a transformer in the forward path and an optoisolator in the feedback path or a third winding in the
transformer. The typical application circuit shown on the
front page of the datasheet represents an isolated design
using an optoisolator. In applications where a nonisolated
topology is desired, the LTC4267 features a feedback port
and an internal error amplifier that can be enabled for this
specific application.
In the typical application circuit (Figure 11), the isolated
topology employs an external resistive voltage divider
to present a fraction of the output voltage to an external
error amplifier. The error amplifier responds by pulling
an analog current through the input LED on an optoisolator. The collector of the optoisolator output presents a
corresponding current into the ITH/RUN pin via a series
diode. This method generates a feedback voltage on the
ITH/RUN pin while maintaining isolation.
The voltage on the ITH/RUN pin controls the pulse-width
modulator formed by the oscillator, current comparator,
and RS latch. Specifically, the voltage at the ITH/RUN pin
sets the current comparator’s trip threshold. The current
comparator monitors the voltage across a sense resistor
in series with the source terminal of the external N-Channel MOSFET. The LTC4267 turns on the external power
MOSFET when the internal free-running 200kHz oscillator
sets the RS latch. It turns off the MOSFET when the current comparator resets the latch or when 80% duty cycle
is reached, whichever happens first. In this way, the peak
current levels through the flyback transformer’s primary
and secondary are controlled by the ITH/RUN voltage.
In applications where a nonisolated topology is desirable
(Figure 11), an external resistive voltage divider can present
a fraction of the output voltage directly to the VFB pin of
the LTC4267. The divider must be designed so when the
output is at its desired voltage, the VFB pin voltage will
equal the 800mV onboard internal reference. The internal
error amplifier responds by driving the ITH/RUN pin. The
LTC4267 switching regulator performs in a similar manner
as described previously.
Regulator Start-Up/Shutdown
The LTC4267 switching regulator has two shutdown
mechanisms to enable and disable operation: an undervoltage lockout on the PVCC supply pin and a forced
shutdown whenever external circuitry drives the ITH/RUN
pin low. The LTC4267 switcher transitions into and out of
shutdown according to the state diagram (Figure 8). It is
important not to confuse the undervoltage lockout of the
PD interface at VPORTN with that of the switching regulator
at PVCC. They are independent functions.
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The undervoltage lockout mechanism on PVCC prevents
the LTC4267 switching regulator from trying to drive the
external N-Channel MOSFET with insufficient gate-toLTC4267
PWM
SHUTDOWN
PVCC < VTURNOFF
ALL VOLTAGES WITH
RESPECT TO PGND
VITH/RUN
< VITHSHDN
(NOMINALLY
0.28V)
VITH/RUN > VITHSHDN
AND PVCC > VTURNON
(NOMINALLY 8.7V)
Adjustable Slope Compensation
The LTC4267 switching regulator injects a 5µA peak current ramp out through its SENSE pin which can be used
for slope compensation in designs that require it. This
current ramp is approximately linear and begins at zero
current at 6% duty cycle, reaching peak current at 80%
duty cycle. Programming the slope compensation via a
series resistor is discussed in the External Interface and
Component Selection section.
EXTERNAL INTERFACE AND COMPONENT SELECTION
LTC4267
PWM
ENABLED
4267 F08
Figure 8. LTC4267 Switching Regulator
Start-Up/Shutdown State Diagram
source voltage. The voltage at the PVCC pin must exceed
VTURNON (nominally 8.7V with respect to PGND) at least
momentarily to enable operation. The PVCC voltage must
fall to VTURNOFF (nominally 5.7V with respect to PGND)
before the undervoltage lockout disables the switching
regulator. This wide UVLO hysteresis range supports
applications where a bias winding on the flyback transformer is used to increase the efficiency of the LTC4267
switching regulator.
The ITH/RUN can be driven below VITHSHDN (nominally
0.28V with respect to PGND) to force the LTC4267 switching
regulator into shutdown. An internal 0.3µA current source
always tries to pull the ITH/RUN pin towards PVCC. When
the ITH/RUN pin voltage is allowed to exceed VITHSHDN and
PVCC exceeds VTURNON, the LTC4267 switching regulator
begins to operate and an internal clamp immediately pulls
the ITH/RUN pin to about 0.7V. In operation, the ITH/RUN
pin voltage will vary from roughly 0.7V to 1.9V to represent
current comparator thresholds from zero to maximum.
Input Interface Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 9). For
PoE devices, the isolation transformer must include a
center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Bel Fuse, Coilcraft, Pulse and Tyco (Table 3) can provide assistance with
selection of an appropriate isolation transformer and proper
termination methods. These vendors have transformers
specifically designed for use in PD applications.
Table 3. Power over Ethernet Transformer Vendors
VENDOR
Bel Fuse Inc.
Coilcraft, Inc.
Pulse Engineering
Internal Soft-Start
An internal soft-start feature is enabled whenever the
LTC4267 switching regulator comes out of shutdown.
Specifically, the ITH/RUN voltage is clamped and is
prevented from reaching maximum until 1.4ms have
passed. This allows the input current of the PD to rise in a
smooth and controlled manner on start-up and stay within
the current limit requirement of the LTC4267 interface.
16
Tyco Electronics
CONTACT INFORMATION
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com
1102 Silver Lake Road
Cary, IL 60013
Tel: 847-639-6400
FAX: 847-639-1469
http://www.coilcraft.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com
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Diode Bridge
IEEE 802.3af allows power wiring in either of two configurations: on the TX/RX wires or via the spare wire pairs in
the RJ45 connector. The PD is required to accept power in
either polarity on either the main or spare inputs; therefore
it is common to install diode bridges on both inputs in
order to accommodate the different wiring configurations.
Figure 9 demonstrates an implementation of these diode
bridges. The IEEE 802.3af specification also mandates
that the leakage back through the unused bridge be less
than 28µA when the PD is powered with 57V.
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capacitor C14 in Figure 9 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
falls into and then select the appropriate value of RCLASS
from Table 2. If a unique load current is required, the value
of RCLASS can be calculated as:
RCLASS = 1.237V/(IDESIRED – IIN_CLASS)
where IIN_CLASS is the LTC4267 IC supply current during
classification and is given in the electrical specifications.
The RCLASS resistor must be 1% or better to avoid degrading
the overall accuracy of the classification circuit. Resistor
power dissipation will be 50mW maximum and is transient
so heating is typically not a concern. In order to maintain
loop stability, the layout should minimize capacitance at
the RCLASS node. The classification circuit can be disabled
by floating the RCLASS pin. The RCLASS pin should not be
shorted to VPORTN as this would force the LTC4267 classification circuit to attempt to source very large currents
and quickly go into thermal shutdown.
The LTC4267 has several different modes of operation
based on the voltage present between VPORTN and VPORTP
pins. The forward voltage drop of the input diodes in a PD
design subtracts from the input voltage and will affect the
transition point between modes. When using the LTC4267,
it is necessary to pay close attention to this forward voltage
drop. Selection of oversized diodes will help keep the PD
thresholds from exceeding IEEE specifications.
Power Good Interface
The input diode bridge of a PD can consume over 4%
of the available power in some applications. It may be
desirable to use Schottky diodes in order to reduce power
loss. However, if the standard diode bridge is replaced
with a Schottky bridge, the transition points between the
modes will be affected. Figure 10 shows a technique for
using Schottky diodes while maintaining proper threshold
points to meet IEEE 802.3af compliance. D13 is added to
compensate for the change in UVLO turn-on voltage caused
by the Schottky diodes and consumes little power.
In some applications, it is desirable to ignore intermittent
power bad conditions. This can be accomplished by including capacitor C15 in Figure 7 to form a lowpass filter.
With the components shown, power bad conditions less
than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
⎯P⎯W⎯R⎯G⎯D to the switching regulator using CPVCC or C17
as shown in Figure 7.
Classification Resistor Selection (RCLASS)
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from RCLASS to
VPORTN (Figure 4) sets the value of the load current. The
designer should determine which power category the PD
The ⎯P⎯W⎯R⎯G⎯D signal is controlled by a high voltage, opendrain transistor. The designer has the option of using this
signal to enable the onboard switching regulator through
the ITH/RUN or the PVCC pins. Examples of active-high
interface circuits for controlling the switching regulator
are shown in Figure 7.
It is recommended that the designer use the power
good signal to enable the switching regulator. Using
⎯P⎯W⎯R⎯G⎯D ensures the capacitor C1 has reached within
1.5V of the final value and is ready to accept a load. The
LTC4267 is designed with wide power good hysteresis
to handle sudden fluctuations in the load voltage and
current without prematurely shutting off the switching
regulator. Please refer to the Power-Up Sequencing of the
Application Information section.
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RJ45
1
TX+
16 T1 1
TX–
2
RX+
3
RX–
6
15
2
14
11
3
6
10
7
9
8
BR1
HD01
TO PHY
PULSE H2019
SPARE+
4
BR2
HD01
5
7
VPORTP
C14
0.1µF
100V
SPARE–
8
LTC4267
D3
SMAJ58A
TVS
VPORTN
4267 F09
Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
D11
B1100
D9
B1100
R2
75Ω
C3
0.01µF
200V
R1
75Ω
C7
0.01µF
200V
D12
B1100
D10
B1100
D6
SMAJ58A
C2
1000pF
2kV
J2
1
2
IN
FROM
PSE
3
6
4
5
7
8
TX+
TX–
RX+
RX–
16
T1
1
15
2
14
3
11
6
10
7
9
8
C11
0.1µF
100V
OUT
TO PHY
TXOUT+
D13
MMSD4148
–
TXOUT
RXOUT+
C25
0.01µF
200V
C24
0.01µF
200V
RXOUT–
R31
75Ω
R30
75Ω
D14
B1100
SPARE+
SPARE–
D15
B1100
RJ45
RCLASS
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
2. SELECT RCLASS FOR CLASS 1-4 OPERATION. REFER
TO DATA SHEET APPLICATIONS INFORMATION SECTION
C2: AVX 1808GC102MAT
D9 TO D12, D14 TO D17: DIODES INC., B1100
T1: PULSE H2019
D17
B1100
D16
B1100
RCLASS
1%
VPORTP
LTC4267
VPORTN
4267 F10
Figure 10. PD Front End with Isolation Transformer, 2nd Schottky Diode Bridge
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Signature Disable Interface
To disable the 25kΩ signature resistor, connect SIGDISA pin
to the VPORTP pin. Alternately, SIGDISA pin can be driven
high with respect to VPORTN. An example of a signature
disable interface is shown in Figure 16, option 2. Note that
the SIGDISA input resistance is relatively large and the
threshold voltage is fairly low. Because of high voltages
present on the printed circuit board, leakage currents from
the VPORTP pin could inadvertently pull SIGDISA high. To
ensure trouble-free operation, use high voltage layout
techniques in the vicinity of SIGDISA. If unused, connect
SIGDISA to VPORTN.
Load Capacitor
The IEEE 802.3af specification requires that the PD maintain
a minimum load capacitance of 5µF (provided by C1 in
Figure 11). It is permissible to have a much larger load
capacitor and the LTC4267 can charge very large load
capacitors before thermal issues become a problem. The
load capacitor must be large enough to provide sufficient
energy for proper operation of the switching regulator.
However, the capacitor must not be too large or the PD
design may violate IEEE 802.3af requirements.
If the load capacitor is too large, there can be a problem
with inadvertent power shutdown by the PSE. Consider
the following scenario. If the PSE is running at –57V
(maximum allowed) and the PD has detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (minimum allowed), the input bridge will reverse bias
and the PD power will be supplied by the load capacitor.
Depending on the size of the load capacitor and the DC load
of the PD, the PD will not draw any power for a period of
time. If this period of time exceeds the IEEE 802.3af 300ms
disconnect delay, the PSE will remove power from the PD.
For this reason, it is necessary to ensure that inadvertent
shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily, causing the capacitor to charge at a somewhat reduced rate.
Conversely, charging a very large capacitor may cause the
current limit to increase slightly. In either case, once the
output voltage reaches its final value, the input current
limit will be restored to its nominal value.
The load capacitor can store significant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4267. The polarity-protection diode(s) prevent an accidental short on the
cable from causing damage. However, if the VPORTN pin
is shorted to VPORTP inside the PD while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4267.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed.
Selecting Feedback Resistor Values
The regulated output voltage of the switching regulator is
determined by the resistor divider across VOUT (R1 and
R2 in Figure 11) and the error amplifier reference voltage
VREF. The ratio of R2 to R1 needed to produce the desired
voltage can be calculated as:
R2 = R1 • (VOUT – VREF)/VREF
In an isolated power supply application, VREF is determined
by the designer’s choice of an external error amplifier.
Commercially available error amplifiers or programmable
shunt regulators may include an internal reference of
1.25V or 2.5V. Since the LTC4267 internal reference and
error amplifier are not used in an isolated design, tie the
VFB pin to PGND.
In a nonisolated power supply application, the LTC4267
onboard internal reference and error amplifier can be
used. The resistor divider output can be tied directly to
the VFB pin. The internal reference of the LTC4267 is 0.8V
nominal.
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Choose resistance values for R1 and R2 to be as large as
possible to minimize any efficiency loss due to the static
current drawn from VOUT, but just small enough so that
when VOUT is in regulation, the error caused by the nonzero
input current from the output of the resistor divider to the
error amplifier pin is less than 1%.
Error Amplifier and Optoisolator Considerations
In an isolated topology, the selection of the external error
amplifier depends on the output voltage of the switching
regulator. Typical error amplifiers include a voltage reference of either 1.25V or 2.5V. The output of the amplifier
and the amplifier upper supply rail are often tied together
internally. The supply rail is usually specified with a wide
upper voltage range, but it is not allowed to fall below the
reference voltage. This can be a problem in an isolated
switcher design if the amplifier supply voltage is not properly managed. When the switcher load current decreases
and the output voltage rises, the error amplifier responds
by pulling more current through the LED. The LED voltage
can be as large as 1.5V, and along with RLIM, reduces the
supply voltage to the error amplifier. If the error amp does
not have enough headroom, the voltage drop across the
LED and RLIM may shut the amplifier off momentarily,
causing a lock-up condition in the main loop. The switcher
will undershoot and not recover until the error amplifier
releases its sink current. Care must be taken to select the
reference voltage and RLIM value so that the error amplifier
always has enough headroom. An alternate solution that
avoids these problems is to utilize the LT1431 or LT4430
where the output of the error amplifier and amplifier supply
rail are brought out to separate pins.
The PD designer must also select an optoisolator such
that its bandwidth is sufficiently wider than the bandwidth
of the main control loop. If this step is overlooked, the
main control loop may be difficult to stabilize. The output
collector resistor of the optoisolator can be selected for
an increase in bandwidth at the cost of a reduction in gain
of this stage.
Output Transformer Design Considerations
Since the external feedback resistor divider sets the
output voltage, the PD designer has relative freedom in
selecting the transformer turns ratio. The PD designer
can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)
which yields more freedom in setting the total turns and
mutual inductance and may allow the use of an off the
shelf transformer.
Transformer leakage inductance on either the primary or
secondary causes a voltage spike to occur after the output
switch (Q1 in Figure 11) turns off. The input supply voltage plus the secondary-to-primary referred voltage of the
flyback pulse (including leakage spike) must not exceed
the allowed external MOSFET breakdown rating. This spike
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In some cases,
a “snubber” circuit will be required to avoid overvoltage
breakdown at the MOSFET’s drain node. Application
Note 19 is a good reference for snubber design.
Current Sense Resistor Consideration
The external current sense resistor (RSENSE in Figure 11)
allows the designer to optimize the current limit behavior
for a particular application. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak swing current goes from a fraction of an ampere to
several amperes. Care must be taken to ensure proper
circuit operation, especially for small current sense resistor values.
Choose RSENSE such that the switching current exercises
the entire range of the ITH/RUN voltage. The nominal voltage
range is 0.7V to 1.9V and RSENSE can be determined by
experiment. The main loop can be temporarily stabilized
by connecting a large capacitor on the power supply. Apply
the maximum load current allowable at the power supply output based on the class of the PD. Choose RSENSE
such that ITH/RUN approaches 1.9V. Finally, exercise the
output load current over the entire operating range and
ensure that ITH/RUN voltage remains within the 0.7V to
1.9V range. Layout is critical around the RSENSE resistor.
For example, a 0.020Ω sense resistor, with one milliohm
(0.001Ω) of parasitic resistance will cause a 5% reduction
in peak switch current. The resistance of printed circuit
copper traces cannot necessarily be ignored and good
layout techniques are mandatory.
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ISOLATED DESIGN EXAMPLE
–48V
FROM
DATA PAIR
+
VOUT
•
C1
RSTART
–
D1
T1
VPORTP
LPRI
PGND
PVCC
COUT
LSEC
•
CPVCC
PVCC
VPORTP
0.1µF
100V
–48V
FROM
SPARE PAIR
–
NGATE
Q1
RSL
RCLASS
RCLASS
+
PGND
VPORTN
RLIM
SENSE
LTC4267
SIGDISA
VPORTN
RSENSE
PGND
VPORTP
VFB
ITH/RUN
POUT
OPTOISOLATOR
PGND
PVCC
PGND
ERROR
AMPLIFIER
RC
CC
R2
R1
PGND
CISO
NONISOLATED DESIGN EXAMPLE
T1
LBIAS
D2
–48V
FROM
DATA PAIR
•
+
R3
RSTART
–
0.1µF
100V
VPORTP
LPRI
PGND
NGATE
+
–
COUT
PGND
RSL
SENSE
LTC4267
SIGDISA
VPORTN
LSEC
•
Q1
RCLASS
RCLASS
VOUT
•
C1
CPVCC
PGND
PVCC
–48V
FROM
SPARE PAIR
D1
PGND
RSENSE
R2
PGND
VFB
ITH/RUN
CC
POUT
PGND
R1
4267 F11
PGND
Figure 11. Typical LTC4267 Application Circuits
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Programmable Slope Compensation
The LTC4267 switching regulator injects a ramping current
through its SENSE pin into an external slope compensation
resistor (RSL in Figure 11). This current ramp starts at
zero after the NGATE pin has been high for the LTC4267’s
minimum duty cycle of 6%. The current rises linearly towards a peak of 5µA at the maximum duty cycle of 80%,
shutting off once the NGATE pin goes low. A series resistor (RSL) connecting the SENSE pin to the current sense
resistor (RSENSE) develops a ramping voltage drop. From
the perspective of the LTC4267 SENSE pin, this ramping
voltage adds to the voltage across the sense resistor,
effectively reducing the current comparator threshold in
proportion to duty cycle. This stabilizes the control loop
against subharmonic oscillation. The amount of reduction
in the current comparator threshold (∆VSENSE) can be
calculated using the following equation:
∆VSENSE = 5µA • RSL • [(Duty Cycle – 6%)/74%]
Note: The LTC4267 enforces 6% < Duty Cycle < 80%.
Designs not needing slope compensation may replace RSL
with a short-circuit.
Applications Employing a Third Transformer Winding
A standard operating topology may employ a third
winding on the transformer’s primary side that provides
power to the LTC4267 switching regulator via its PVCC pin
(Figure 11). However, this arrangement is not inherently
self-starting. Start-up is usually implemented by the use of
an external “trickle-charge” resistor (RSTART) in conjunction with the internal wide hysteresis undervoltage lockout
circuit that monitors the PVCC pin voltage.
RSTART is connected to VPORTP and supplies a current,
typically 100µA, to charge CPVCC. After some time, the
voltage on CPVCC reaches the PVCC turn-on threshold. The
LTC4267 switching regulator then turns on abruptly and
draws its normal supply current. The NGATE pin begins
switching and the external MOSFET (Q1) begins to deliver
power. The voltage on CPVCC begins to decline as the
switching regulator draws its normal supply current, which
exceeds the delivery from RSTART. After some time, typically
tens of milliseconds, the output voltage approaches the
desired value. By this time, the third transformer winding
is providing virtually all the supply current required by the
LTC4267 switching regulator.
One potential design pitfall is under-sizing the value of
capacitor CPVCC. In this case, the normal supply current
drawn through PVCC will discharge CPVCC rapidly before the
third winding drive becomes effective. Depending on the
particular situation, this may result in either several off-on
cycles before proper operation is reached or permanent
relaxation oscillation at the PVCC node.
Resistor RSTART should be selected to yield a worst-case
minimum charging current greater that the maximum rated
LTC4267 start-up current to ensure there is enough current
to charge CPVCC to the PVCC turn-on threshold. RSTART
should also be selected large enough to yield a worst-case
maximum charging current less than the minimum-rated
PVCC supply current, so that in operation, most of the
PVCC current is delivered through the third winding. This
results in the highest possible efficiency.
Capacitor CPVCC should then be made large enough to avoid
the relaxation oscillation behavior described previously.
This is difficult to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended.
The third transformer winding should be designed so
that its output voltage, after accounting for the forward
diode voltage drop, exceeds the maximum PVCC turn-off
threshold. Also, the third winding’s nominal output voltage
should be at least 0.5V below the minimum rated PVCC
clamp voltage to avoid running up against the LTC4267
shunt regulator, needlessly wasting power.
PVCC Shunt Regulator
In applications including a third transformer winding,
the internal PVCC shunt regulator serves to protect the
LTC4267 switching regulator from overvoltage transients
as the third winding is powering up.
If a third transformer winding is undesirable or unavailable, the shunt regulator allows the LTC4267 switching
regulator to be powered through a single dropping resistor
from VPORTP as shown in Figure 12. This simplicity comes
at the expense of reduced efficiency due to static power
dissipation in the RSTART dropping resistor.
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The shunt regulator can sink up to 5mA through the PVCC
pin to PGND. The values of RSTART and CPVCC must be
selected for the application to withstand the worst-case
load conditions and drop on PVCC, ensuring that the PVCC
turn-off threshold is not reached. CPVCC should be sized
sufficiently to handle the switching current needed to drive
NGATE while maintaining minimum switching voltage.
+
actual current needed to power the LTC4267 switching
regulator goes through Q1 and PVCC sources current on
an “as-needed” basis. The static current is then limited
only to the current through RB and D1.
+
RB
VPORTP
– 48
FROM
PSE
PVCC
PGND
RSTART
– 48
FROM
PSE
PVCC
LTC4267
CPVCC
CPVCC
PGND
–
VPORTN POUT
PGND
–
PGND
LTC4267
VPORTP
RSTART
Q1
D1
8.2V
PGND
4267 F15
Figure 13. Powering the LTC4267 Switching
Regulator with an External Preregulator
VPORTN POUT
PGND
4267 F14
Figure 12. Powering the LTC4267 Switching
Regulator via the Shunt Regulator
External Preregulator
The circuit in Figure 13 shows a third way to power the
LTC4267 switching regulator circuit. An external series
preregulator consists of a series pass transistor Q1, zener
diode D1, and a bias resistor RB. The preregulator holds
PVCC at 7.6V nominal, well above the maximum rated PVCC
turn-off threshold of 6.8V. Resistor RSTART momentarily
charges the PVCC node up to the PVCC turn-on threshold,
enabling the switching regulator. The voltage on CPVCC
begins to decline as the switching regulator draws its
normal supply current, which exceeds the delivery of
RSTART. After some time, the output voltage approaches
the desired value. By this time, the pass transistor Q1
catches the declining voltage on the PVCC pin, and provides
virtually all the supply current required by the LTC4267
switching regulator. CPVCC should be sized sufficiently to
handle the switching current needed to drive NGATE while
maintaining minimum switching voltage.
Compensating the Main Loop
In an isolated topology, the compensation point is typically
chosen by the components configured around the external
error amplifier. Shown in Figure 14, a series RC network
is connected from the compare voltage of the error amplifier to the error amplifier output. In PD designs where
transient load response is not critical, replace RZ with a
short. The product of R2 and CC should be sufficiently large
to ensure stability. When fast settling transient response
is critical, introduce a zero set by RZCC. The PD designer
must ensure that the faster settling response of the output
voltage does not compromise loop stability.
In a nonisolated design, the LTC4267 incorporates an
internal error amplifier where the ITH/RUN pin serves as
a compensation point. In a similar manner, a series RC
network can be connected from ITH/RUN to PGND as
shown in Figure 15. CC and RZ are chosen for optimum
load and line transient response.
TO OPTOISOLATOR
RZ
CC
VOUT
R2
The external preregulator has improved efficiency over
the simple resistor-shunt regulator method mentioned
previously. RB can be selected so that it provides a small
current necessary to maintain the zener diode voltage and
the maximum possible base current Q1 will encounter. The
R1
4267 F14
Figure 14. Main Loop Compensation for an Isolated Design
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of the LTC4267. In this case, it is necessary to ensure the
user cannot access the terminals of the wall transformer
jack on the PD since this would compromise the 802.3af
isolation safety requirements.
LTC4267
ITH/RUN
CC
PGND
RZ
4267 F15
Figure 15. Main Loop Compensation for a Nonisolated Design
Selecting the Switching Transistor
With the N-channel power MOSFET driving the primary of
the transformer, the inductance will cause the drain of the
MOSFET to traverse twice the voltage across VPORTP and
PGND. The LTC4267 operates with a maximum supply of
– 57V; thus the MOSFET must be rated to handle 114V or
more with sufficient design margin. Typical transistors have
150V ratings while some manufacturers have developed
120V rated MOSFETs specifically for Power-over-Ethernet
applications.
The NGATE pin of the LTC4267 drives the gate of the
N-channel MOSFET. NGATE will traverse a rail-to-rail voltage from PGND to PVCC. The designer must ensure the
MOSFET provides a low “ON” resistance when switched
to PVCC as well as ensure the gate of the MOSFET can
handle the PVCC supply voltage.
For high efficiency applications, select an N-channel
MOSFET with low total gate charge. The lower total gate
charge improves the efficiency of the NGATE drive circuit
and minimizes the switching current needed to charge
and discharge the gate.
Auxiliary Power Source
In some applications, it may be desirable to power the
PD from an auxiliary power source such as a wall transformer. The auxiliary power can be injected into the PD at
several locations and various trade-offs exist. Power can
be injected at the 3.3V or 5V output of the isolated power
supply with the use of a diode ORing circuit. This method
accesses the internal circuits of the PD after the isolation
barrier and therefore meets the 802.3af isolation safety
requirements for the wall transformer jack on the PD.
Power can also be injected into the PD interface portion
Figure 16 demonstrates three methods of diode ORing
external power into a PD. Option 1 inserts power before
the LTC4267 interface controller while options 2 and 3
bypass the LTC4267 interface controller section and power
the switching regulator directly.
If power is inserted before the LTC4267 interface controller, it is necessary for the wall transformer to exceed
the LTC4267 UVLO turn-on requirement and include a
transient voltage suppressor (TVS) to limit the maximum
voltage to 57V. This option provides input current limit
for the transformer, provides a valid power good signal,
and simplifies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it
will take priority and the PSE will not power up the PD
because the wall power will corrupt the 25kΩ signature. If
the PSE is already powering the PD, the wall transformer
power will be in parallel with the PSE. In this case, priority will be given to the higher supply voltage. If the wall
transformer voltage is higher, the PSE should remove the
line voltage since no current will be drawn from the PSE.
On the other hand, if the wall transformer voltage is lower,
the PSE will continue to supply power to the PD and the
wall transformer will not be used. Proper operation should
occur in either scenario.
If auxiliary power is applied directly to the LTC4267 switching regulator (bypassing the LTC4267 PD interface), a
different set of tradeoffs arise. In the configuration shown
in option 2, the wall transformer does not need to exceed
the LTC4267 turn-on UVLO requirement; however, it is
necessary to include diode D9 to prevent the transformer
from applying power to the LTC4267 interface controller.
The transformer voltage requirement will be governed by
the needs of the onboard switching regulator. However,
power priority issues require more intervention. If the
wall transformer voltage is below the PSE voltage, then
priority will be given to the PSE power. The LTC4267
interface controller will draw power from the PSE while
the transformer will sit unused. This configuration is not
a problem in a PoE system. On the other hand, if the wall
4267fc
24
LTC4267
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APPLICATIO S I FOR ATIO
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267 PD
RJ45
1
2
3
6
TX+
T1
~
TX–
RX+
BR1
HD01
TO PHY
~
RX–
D3
SMAJ58A
TVS
+
C14
0.1µF
100V
RSTART
–
C1
VPORTP
SPARE+
4
~
5
PVCC
+
LTC4267
BR2
HD01
7
SPARE–
8
~
CPVCC
PGND
–
VPORTN POUT
PGND
+
D8
S1B
ISOLATED
WALL
38V TO 57V
TRANSFORMER
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267 PD WITH SIGNATURE DISABLED
RJ45
1
2
3
6
TX+
TX
T1
~
–
RX+
+
~
100k
C14
0.1µF
100V
BR1
HD01
TO PHY
RX–
D3
SMAJ58A
TVS
–
C1
BSS63
VPORTP
SPARE+
4
~
5
7
~
ISOLATED
WALL
TRANSFORMER
100k
SIGDISA
PVCC
LTC4267
PGND
BR2
HD01
SPARE–
8
+
RSTART
–
CPVCC
VPORTN POUT
PGND
D9
S1B
+
–
D10
S1B
OPTION 3: AUXILIARY POWER APPLIED TO LTC4267 PD AND SWITCHING REGULATOR
RJ45
1
2
3
6
TX+
TX
T1
~
–
RX+
+
BR1
HD01
TO PHY
~
RX–
D3
SMAJ58A
TVS
C14
0.1µF
100V
RSTART
–
C1
VPORTP
4
SPARE+
~
5
7
8
+
BR2
HD01
–
SPARE
~
ISOLATED
WALL
TRANSFORMER
LTC4267
CPVCC
PGND
–
VPORTN POUT
PGND
+
38V TO 57V
–
PVCC
D10
S1B
4267 F16
Figure 16. Auxiliary Power Source for PD
4267fc
25
LTC4267
U
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APPLICATIO S I FOR ATIO
transformer voltage is higher than the PSE voltage, the
LTC4267 switching regulator will draw power from the
transformer. In this situation, it is necessary to address the
issue of power cycling that may occur if a PSE is present.
The PSE will detect the PD and apply power. If the switcher
is being powered by the wall transformer, then the PD will
not meet the minimum load requirement and the PSE will
subsequently remove power. The PSE will again detect
the PD and power cycling will start. With a transformer
voltage above the PSE voltage, it is necessary to either
disable the signature, as shown in option 2, or install a
minimum load on the output of the LTC4267 interface to
prevent power cycling.
The third option also applies power directly to the LTC4267
switching regulator, bypassing the LTC4267 interface
controller and omitting diode D9. With the diode omitted, the transformer voltage is applied to the LTC4267
interface controller in addition to the switching regulator.
For this reason, it is necessary to ensure that the transformer maintain the voltage between 38V and 57V to keep
the LTC4267 interface controller in its normal operating
range. The third option has the advantage of automatically
disabling the 25kΩ signature resistor when the external
voltage exceeds the PSE voltage.
to drive the ITH/RUN port below the shutdown threshold
(typically 0.28V). The second example drives PVCC below
the PVCC turn-off threshold. Employing the second example
has the added advantage of adding delay to the switching
regulator start-up beyond the time the power good signal
becomes active. The second example ensures additional
timing margin at start-up without the need for added delay
components. In applications where it is not desirable to
utilize the power good signal, sufficient timing margin can
be achieved with RSTART and CPVCC. RSTART and CPVCC
should be set to a delay of two to three times longer than
the duration needed to charge up C1.
Layout Considerations for the LTC4267
The most critical layout considerations for the LTC4267
are the placement of the supporting external components
associated with the switching regulator. Efficiency, stability,
and load transient response can deteriorate without good
layout practices around critical components.
The LTC4267 consists of two functional cells, the PD
interface and the switching regulator, and the power up
sequencing of these two cells must be carefully considered.
The PD designer should ensure that the switching regulator
does not begin operation until the interface has completed
charging up the load capacitor. This will ensure that the
switcher load current does not compete with the load
capacitor charging current provided by the PD interface
current limit circuit. Overlooking this consideration may
result in slow power supply ramp up, power-up oscillation,
and possibly thermal shutdown.
For the LTC4267 switching regulator, the current loop
through C1, T1 primary, Q1, and RSENSE must be given
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessary to complete the connectivity of this loop,
placing multiple vias lined perpendicular to the flow of
current is essential for minimizing parasitic resistance and
reducing current density. Since the switching frequency
and the power levels are substantial, shielding and high
frequency layout techniques should be employed. A low
current, low impedance alternate connection should be
employed between the PGND pins of the LTC4267 and the
PGND side of RSENSE, away from the high current loop.
This Kelvin sensing will ensure an accurate representation
of the sense voltage is measured by the LTC4267.
The LTC4267 includes a power good signal in the PD interface that can be used to indicate to the switching regulator
that the load capacitor is fully charged and ready to handle
the switcher load. Figure 7 shows two examples of ways
the ⎯P⎯W⎯R⎯G⎯D signal can be used to control the switching
regulator. The first example employs an N-channel MOSFET
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor CC is very important
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and CC should be
placed as close as possible to the error amplifier’s input
Power-Up Sequencing the LTC4267
4267fc
26
LTC4267
U
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APPLICATIO S I FOR ATIO
with minimum trace lengths and minimum capacitance.
In a nonisolated application, R1, and R2 should be placed
as close as possible to the VFB pin of the LTC4267 and
CC should be placed close to the ITH/RUN pin of the
LTC4267.
or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left floating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure successful operation of the LTC4267 in a PD.
Electro Static Discharge and Surge Protection
The PD interface section of the LTC4267 is relatively immune to layout problems. Excessive parasitic capacitance
on the RCLASS pin should be avoided. If using the DHC
package, include an electrically isolated heat sink to which
the exposed pad on the bottom of the package can be
soldered. For optimum thermal performance, make the
heat sink as large as possible. The SIGDISA pin is adjacent
to the VPORTP pin and any coupling, whether resistive
The LTC4267 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VPORTN and VPORTP) can
routinely see peak voltages in excess of 10kV. To protect
the LTC4267, it is highly recommended that a transient
voltage suppressor be installed between the diode bridge
and the LTC4267 (D3 in Figure 2).
4267fc
27
LTC4267
U
TYPICAL APPLICATIO S
Class 3 PD with 5V Nonisolated Power Supply
COILTRONICS
CTX-02-15242
5µF*
MIN
–48V
FROM
DATA PAIR
BAS516
VPORTP
–
FDC2512
RCLASS
+
HD01
–
150pF
200V
PWRGD
10k
–48V
FROM
SPARE PAIR
•
1µF
NGATE
0.1µF
9.1V
PVCC
LTC4267
SMAJ58A
300µF**
•
MMBTA42
+
HD01
UPS840
220k
100k
5V
1.8A
45.3Ω
1%
ITH/RUN
22nF
VPORTN
*1µF CERAMIC + 4.7µF TANTALUM
** THREE 100µF CERAMICS
0.04Ω
1%
42.2k
1%
VFB
SIGDISA
POUT
220Ω
SENSE
PGND
27k
4267 TA03
8.06k
1%
4267fc
28
1
2
3
4
5
6
7
8
TO
PHY
TO
PHY
0.1µF
45.3Ω
SMAJ58A
J1 HALO HFJ11 RP28E-L12 INTEGRATED JACK
T1 COILCRAFT D1766-AL
T2 PULSE PA0184
* TWO 100µF CAPACITORS IN PARALLEL
** 47µF AND 220µF IN PARALLEL
*** 1µF CERAMIC + 4.7µF TANTALUM
J1
9
10
11
12
13
14
PGND
VFB
VPORTN
POUT
ITH/RUN
SENSE
PWRGD
SIGDISA
RCLASS
PVCC
220k
NGATE
LTC4267
VPORTP
5µF***
MIN
4.7µF
PVCC
BCX5616
8.2k
10p
51Ω
BAS516
6.8k
PVCC
10Ω
BAS516
8.2V
220k
0.1µF
2.2k
0.068
1%
MMBT3904
Si3440DV
•
T1
•
T2
1k
2.2nF
250VAC
0.033µF
ZRL431
PH7030DL
Si3442DV
6.8nF
10k
4.7µF
PH7030DL
0.47µF
20Ω
BAT54SLT1
PS2911
•
•
•
•
Class 3 PD with Triple Output Isolated Power Supply
4267 TA04
49.9k
1%
49.9k
1%
PH7030DL
100µF
200µF*
267µF**
CHASSIS
1.8V
AT 2.5A
2.5V
AT 1.5A
3.3V
AT 0.5A
LTC4267
TYPICAL APPLICATIO S
4267fc
29
U
LTC4267
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
9
16
8
1
(DHC16) DFN 1103
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4267fc
30
LTC4267
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
4267fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC4267
TYPICAL APPLICATION
High-Efficiency Class 3 PD with 3.3V Isolated Power Supply
10Ω
PULSE
PA1136
470pF
SBM1040
3.3V
2.6A
•
5µF*
MIN
220k
330Ω
220k
510Ω
570µF**
•
CHASSIS
MMTBA42
MMSD4148
–48V
FROM
DATA PAIR
BAS516
150pF
9.1V
VPORTP
BAS516
PVCC
PVCC
•
4.7µF
LTC4267
SMAJ58A
B1100
(8 PLACES)
Si3440
NGATE
10k
0.1µF
SENSE
RCLASS
–48V
FROM
SPARE PAIR
ITH/RUN
45.3Ω
1%
0.068Ω
1%
PVCC
100k
SIGDISA
PWRGD
10k
VPORTN
POUT
*1µF CERAMIC + 4.7µF TANTALUM
**100µF CERAMIC + 470µF TANTALUM
VFB
PVCC
500Ω
6.8k
33nF
BAS516
2N7002
100k
1%
PS2911
MMSD4148
PGND
TLV431
2200pF
“Y” CAP
250VAC
60.4k
1%
4267 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1737
LTC1871
High Power Isolated Flyback Controller
Wide Input Range, No RSENSETM Current Mode
Flyback, Boost and SEPIC Controller
LTC3803
Current Mode Flyback DC/DC Controller in ThinSOTTM
LTC4257
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
IEEE 802.3af PD Interface Controller
with Dual Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
LTC4259A
Quad IEEE 802.3af Power over Ethernet Controller
Sense Output Voltage Directly from Primary Side Winding
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
®
Optional Burst Mode Operation at Light Load
200kHz Constant Frequency, Adjustable Slope Compensation,
Optimized for High Input Voltage Applications
100V 400mA Internal Switch, Programmable Classification
100V 400mA Internal Switch, Programmable Classification,
Supports Legacy Applications
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
Autonomous Operation or I2CTM Control
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
Autonomous Operation or I2CTM Control
Burst Mode is a registered trademark of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
4267fc
32
Linear Technology Corporation
LT 0107 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
●
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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