ICST ICS9159M-13 Frequency generator and integrated buffer for pentium Datasheet

Integrated
Circuit
Systems, Inc.
ICS9159-13
Frequency Generator and Integrated Buffer for PENTIUM™
General Description
The ICS9159-13 generates all clocks required for high
speed RISC or CISC microprocessor systems such as 486,
Pentium, PowerPC, etc. Four different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions. A test mode is provided to drive all
clocks directly.
•
High drive BCLK outputs provide typically greater than
1V/ns slew rate into 30pF loads. PCLK outputs provide
typically better than 1V/ns slew rate into 20pF loads while
maintaining 50±5% duty cycle.
Features
Generates up to six processor and six bus clocks, plus
two reference clocks
•
Synchronous clocks skew matched to 250ps window
on PCLKs and 500ps window on BCLKs
•
Processor and bus clocks synchronized to each other,
PCLK to BCLK skew window 600ps max
•
Test clock mode eases system design
•
3.0V - 5.5V supply range
•
28-pin SOIC package
Block Diagram
Pin Cnfiguration
28-Pin SOIC
Functionality
OEN
FS1
FS0
PCLK
BCLK
REF
1
0
0
50MHz
25 MHz
14.318 MHz
1
0
1
66.6 MHz
33.3 MHz
14.318 MHz
1
1
0
60 MHz
30 MHz
14.318 MHz
1
1
1
TCLK/2
TCLK/4
TCLK
0
X
X
Tristate
Tristate
Tristate
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of Motorola Corporation.
9159-13 Rev B 060497
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9159-13
Pin Descriptions
PIN NUMBER
1, 8, 14, 20, 26
PIN NAME
VDD
TYPE
PWR
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz.
2
X1
IN
3
X2
OUT
XTAL output which includes XTAL load capacitance.
GND
PWR
Ground for logic, CPU and fixed frequency output buffers.
PCLK(0:3)
OUT
4, 11, 17, 23
6, 7, 9, 10,
24, 25
13, 12
15, 16, 18, 19,
21, 22
5
28, 27
FS(0:1)
BCLK(0:5)
OEN
REF(0:1)
IN
OUT
IN
OUT
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table above.
Frequency multiplier select pins. See table above. These inputs have internal pull-up
devices.
Bus clock outputs are fixed at one half the PCLK frequency.
OEN tristates all outputs when low. This input has an internal pull-up device.
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
2
ICS9159-13
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V
Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature ............................................................. 0°C to +70°C
Storage Temperature ........................................................................... –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
-
-
0.2VDD
V
Input High Voltage
VIH
0.7VDD
-
-
V
Input Low Current
IIL
VIN=0V
-28.0
-10.5
-
µA
Input High Current
IIH
VIN=VDD
-5.0
-
5.0
µA
Output Low Current1
IOL
VOL=0.8V; for PCLKS & BCLKS
30.0
47.0
-
mA
1
IOH
VOL=2.0V; for PCLKS & BCLKS
-
-66.0
-42.0
mA
Output Low Current1
IOL
VOL=0.8V; for REF CLKs
25.0
38.0
-
mA
1
IOH
VOL=2.0V; for REF CLKs
-
-47.0
-30.0
mA
Output Low Voltage1
VOL
IOL=15mA; for PCLKS & BCLKS
-
0.3
0.4
V
1
VOH
IOH=-30mA; for PCLKS & BCLKS
2.4
2.8
-
V
Output Low Voltage1
VOL
IOL=12.5mA; for REF CLKs
-
0.3
0.4
V
Output High Voltage1
VOH
IOH=-20mA; for REF CLKs
2.4
2.8
-
V
Supply Current
IDD
@66.5 MHz; all outputs unloaded
-
55
110
mA
Output High Current
Output High Current
Output High Voltage
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9159-13
Electrical Characteristics at 3.3V
VDD = 3.1 – 3.7 V, TA = 0 – 70° C
AC Characteristics
PARAMETER
Rise Time
SYMBOL
1
Fall Time1
Rise Time
Fall Time
1
1
Duty Cycle
1
Input Frequency
1
-
0.9
1.5
ns
-
0.8
1.4
ns
Tr2
20pF load, 20% to 80% PCLK & BCLK
-
1.5
2.5
ns
Tf2
20pF load, 80% to 20% PCLK & BCLK
-
1.4
2.4
ns
Dt
45
50
55
%
-
50
150
ps
-250
-
250
ps
Tj1s2
20pF load @ VOUT=1.4V
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
REF CLK; Load=20pF
-
1
3
%
Tjab2
REF CLK; Load=20pF
-5
2
5
%
Fi
Logic Input Capacitance1
1
UNITS
20pF load, 2.0 to 0.8V PCLK & BCLK
Tjab1
Jitter, Absolute
MAX
20pF load, 0.8 to 2.0V PCLK & BCLK
Jitter, Absolute1
1
TYP
Tf1
Tj1s1
Jitter, One Sigma
MIN
Tr1
Jitter, One Sigma1
1
TEST CONDITIONS
12.0
14.318
16.0
MHz
CIN
Logic input pins
-
5
-
pF
CINX
-
18
-
pF
-
2.5
4.5
ms
-
2.0
4.0
ms
-
150
250
ps
Clock Skew Window1
Tsk1
X1, X2 pins
From VDD=1.6V to 1 st crossing of 66.5 MHz
VDD supply ramp < 40ms
From 1st crossing of acquisition to <
1% settling
PCLK to PCLK; Load=20pF; @1.4V
Clock Skew Window
1
Tsk2
BCLK to BCLK; Load=20pF; @1.4V
-
300
500
ps
Clock Skew Window
1
Tsk3
PCLK to BCLK; Load=20pF; @1.4V
-
400
600
ps
Crystal Oscillator Capacitance
Power-on Time1
ton
Frequency Settling Time 1
ts
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9159-13
Electrical Characteristics at 5.0V
VDD = 4.5 – 5.5 V, TA = 0 – 70° C
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
-
-
0.8
V
Input High Voltage
VIH
2.4
-
-
V
Input Low Current
IIL
VIN=0V
-45
-15
-
µA
Input High Current
IIH
VIN=VDD
-5.0
-
5.0
µA
Output Low Current1
IOL
VOL=0.8V; for PCLKS & BCLKS
36.0
62.0
-
mA
Output High Current 1
IOH
VOL=2.0V; for PCLKS & BCLKS
-
-152
-90.0
mA
Output Low Current1
IOL
VOL=0.8V; for REF CLKs
30.0
50.0
-
mA
Output High Current 1
IOH
VOL=2.0V; for REF CLKs
-
-110.0
-65.0
mA
1
VOL
IOL=20mA; for PCLKS & BCLKS
-
0.25
0.4
V
Output High Voltage1
VOH
IOH=-70mA; for PCLKS & BCLKS
2.4
4.0
-
V
1
VOL
IOL=15mA; for REF CLKs
-
0.2
0.4
V
Output High Voltage1
VOH
IOH=-50mA; for REF CLKs
2.4
4.7
-
V
Supply Current
IDD
@66.5 MHz; all outputs unloaded
-
80.0
160.0
mA
Output Low Voltage
Output Low Voltage
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9159-13
Electrical Characteristics at 5.5V
VDD = 4.5 – 5.5 V, TA = 0 – 70° C
AC Characteristics
PARAMETER
SYMBOL
1
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Tr1
20pF load, 0.8 to 2.0V PCLK & BCLK
-
0.55
0.95
ns
Tf1
20pF load, 2.0 to 0.8V PCLK & BCLK
-
0.52
0.90
ns
Tr2
20pF load, 20% to 80% PCLK & BCLK
-
1.2
2.1
ns
Tf2
20pF load, 80% to 20% PCLK & BCLK
-
1.1
2.0
ns
Duty Cycle
1
Dt1
20pF load @ VOUT=1.4V
52
57
62
%
Duty Cycle
1
Dt2
45
50
55
%
-
50
150
ps
-250
-
250
ps
Tj1s2
20pF load @ VOUT=50%
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
REF CLKs; Load=20pF RS=33W
-
1
3
%
Tjab2
REF CLKs; Load=20pF RS=33W
-5
2
5
%
12.0
14.318
16.0
MHz
Rise Time
Fall Time
1
Rise Time
1
Fall Time1
Jitter, One Sigma1
Tj1s1
Jitter, Absolute1
Tjab1
Jitter, One Sigma
Jitter, Absolute
1
1
Input Frequency
1
Fi
Logic Input Capacitance
1
Crystal OscillatorCapacitance
1
CIN
Logic input pins
-
5
-
pF
CINX
-
18
-
pF
-
2.5
4.5
ms
-
2.0
4.0
ms
-
150
250
ps
Clock Skew Window1
Tsk1
X1, X2 pins
From VDD=1.6V to 1 st crossing of 66.5
MHz VDD supply ramp < 40ms
From 1st crossing of acquisition to < 1%
settling
PCLK to PCLK; Load=20pF; @1.4V
1
Tsk2
BCLK to BCLK; Load=20pF; @1.4V
-
300
500
ps
Clock Skew Window1
Tsk3
PCLK to BCLK; Load=20pF; @1.4V
-
400
600
ps
Power-on Time
1
ton
Frequency Settling Time1
Clock Skew Window
ts
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9159-13
LEAD COUNT
28L
DIMENSIONL
0.704
SOIC Package
Ordering Information
ICS9159M-13
Example:
ICS XXXX M-PPP
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC, SOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS=Standard Device
7
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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