ON MC74HC574ANG Octal 3-state noninverting d flip-flop Datasheet

MC74HC574A
Octal 3-State Noninverting
D Flip-Flop
High−Performance Silicon−Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
20
1
MC74HC574AN
AWLYYWWG
1
20
SOIC−20
DW SUFFIX
CASE 751D
20
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
20
PDIP−20
N SUFFIX
CASE 738
1
HC574A
AWLYYWWG
1
20
HC
574A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
F SUFFIX
CASE 967
1
20
1
A
WL, L
YY, Y
WW, W
G or G
74HC574A
AWLYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 13
1
Publication Order Number:
MC74HC574A/D
MC74HC574A
OUTPUT
ENABLE
D0
1
20
VCC
2
19
Q0
D1
3
18
Q1
D2
4
17
Q2
D3
5
16
Q3
OE
L
L
L
H
FUNCTION TABLE
Inputs
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
CLOCK
GND
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
Figure 1. Pin Assignment
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
Q0
Q1
Q2
Q3
Q4
NONINVERTING
OUTPUTS
Q5
Q6
Q7
11
PIN 20 = VCC
PIN 10 = GND
1
Figure 2. Logic Diagram
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
Units
Internal Gate Count*
66.5
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
0.0075
pJ
Speed Power Product
*Equivalent to a two−input NAND gate.
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2
Output
Clock
MC74HC574A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 to VCC )0.5
V
*0.5 to VCC )0.5
V
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
(Note 1)
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$35
mA
IO
DC Output Sink Current
$35
mA
ICC
DC Supply Current per Supply Pin
$75
mA
IGND
DC Ground Current per Ground Pin
$75
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
_C
_C
PDIP
SOIC
TSSOP
67
96
128
_C/W
PDIP
SOIC
TSSOP
750
500
450
mW
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
260
)150
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>4000
>300
>1000
V
Above VCC and Below GND at 85_C (Note 5)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI, VO
Parameter
Min
Max
Unit
DC Supply Voltage
(Referenced to GND)
2.0
6.0
V
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
*55
)125
_C
0
0
0
1000
500
400
ns
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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3
MC74HC574A
ORDERING INFORMATION
Package
Shipping†
PDIP−20
(Pb−Free)
18 Units / Box
MC74HC574ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC574ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC574ADTR2G
TSSOP−20*
2500 Tape & Reel
MC74HC574AFG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74HC574AFELG
SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
Device
MC74HC574ANG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
Test Conditions
*55 to 25_C
v85_C
v125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
VOL
Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIL
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
$0.1
$1.0
$1.0
mA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
$0.5
$5.0
$10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
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MC74HC574A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
VCC
V
Guaranteed Limit
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ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
*55 to 25_C
v85_C
v125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and 6)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
60
140
90
28
24
175
120
35
30
210
140
42
36
ns
tTLH,
tTHL
Maximum Output Transition Time, any Output
(Figures 3 and 6)
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three−State Output Capacitance, Output in High−Impedance
State
15
15
15
pF
CPD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, VCC = 5.0 V
24
pF
*Used to determine the no−load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC .
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
– 55 to 25_C
v 85_C
v 125_C
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ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
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ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
Figure
Volts
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
5
2.0
3.0
4.6
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
th
Minimum Hold Time, Clock to Data
5
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
3
2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
Maximum Input Rise and Fall Times
3
2.0
3.0
4.5
6.0
tr, tf
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5
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC574A
tr
CLOCK
SWITCHING WAVEFORMS
tf
VCC
90%
50%
10%
tw
OUTPUT
ENABLE
GND
1/fmax
tPLH
Q
VCC
VM
90%
50%
10%
tPLZ
tPZH
tPHZ
GND
HIGH
IMPEDANCE
VM
Q
tPHL
tPZL
Q
tTLH
10%
VOL
90%
VOH
MC74HC574A: VM = VOH x 0.5
MC74HCT574A: VM = 1.3 V @ VCC = 3 V
tTHL
Figure 3.
Figure 4.
TEST POINT
OUTPUT
VALID
DATA
VCC
50%
tsu
DEVICE
UNDER
TEST
GND
th
CL *
VCC
CLOCK
50%
GND
*Includes all probe and jig capacitance.
Figure 5.
Figure 6.
D0
D1
D2
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
CL *
D3
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
D4
D5
*Includes all probe and jig capacitance.
D6
2
C
Q
D
19
3
C
Q
D
18
4
C
Q
D
17
5
C
Q
D
16
6
C
Q
D
15
7
C
Q
D
14
8
C
Q
D
13
9
C
Q
D
12
Figure 7. Test Circuit
D7
CLOCK
OUTPUT ENABLE
11
1
Figure 8. Expanded Logic Diagram
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6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MC74HC574A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
20 PL
0.25 (0.010)
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
11
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HC574A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
−U−
PIN 1
IDENT
1
SECTION N−N
0.25 (0.010)
N
10
M
0.15 (0.006) T U
S
N
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC574A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
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