INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT162 Presettable synchronous BCD decade counter; synchronous reset Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 • Synchronous counting and loading that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). • Two count enable inputs for n-bit cascading For the “162” the clear function is synchronous. FEATURES • Positive-edge triggered clock A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. • Synchronous reset • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT162 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The 74HC/HCT162 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: fmax = 1 -------------------------------------------------------------------------------------------------------t P ( max ) ( CP to TC ) + t SU (CEP to CP) Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL propagation delay CP to Qn CP to TC CET to TC CL = 15 pF; VCC = 5 V HCT 19 21 11 20 26 15 ns ns ns 19 21 11 20 19 10 ns ns ns maximum clock frequency 63 32 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 37 37 pF tPLH fmax propagation delay CP to Qn CP to TC CET to TC December 1990 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V notes 1 and 2 2 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR synchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D0 to D3 data inputs 7 CEP count enable input 8 GND ground (0 V) 9 PE parallel enable input (active LOW) 10 CET count enable carry input 14, 13, 12, 11 Q0 to Q3 flip-flop outputs 15 TC terminal count output 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE MR CP CEP CET PE Dn Qn TC reset (clear) I ↑ X X X X L L parallel load h h ↑ ↑ X X X X I I I h L H (1) count h ↑ h h h X count (1) hold (do nothing) h h X X I X X I h h X X qn qn (1) Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition December 1990 4 L L Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 Fig.5 State diagram. Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two and three; inhibit. December 1990 5 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset Fig.7 Logic diagram. December 1990 6 74HC/HCT162 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CP to Qn 58 21 17 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay CP to TC 69 25 20 215 43 37 270 54 46 325 65 55 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay CET to TC 39 14 11 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.9 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 8 and 9 tW clock pulse width HIGH or LOW 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 tsu set-up time MR, Dn to CP 100 20 17 28 10 8 125 25 21 150 30 26 ns 2.0 4.5 6.0 Figs 9 and 11 tsu set-up time PE to CP 135 27 23 39 14 11 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.9 tsu set-up time CEP, CET to CP 200 40 34 69 25 20 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.12 th hold time Dn, PE, CEP, CET, MR to CP 0 0 0 −17 −6 −5 0 0 0 0 0 0 ns 2.0 4.5 6.0 Figs 9, 11 and 12 fmax maximum clock pulse frequency 6.0 30 35 19 57 68 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.8 December 1990 7 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT MR 0.95 CP 0.80 CEP 0.25 Dn 0.25 CET 1.50 PE 0.30 December 1990 8 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 AC CHARACTERISTICS FOR HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 typ. max. min. max. min. max. UNIT VCC WAVEFORMS (V) tPHL/ tPLH propagation delay CP to Qn 24 43 54 65 ns 4.5 Fig.8 tPHL propagation delay CP to TC 30 51 64 77 ns 4.5 Fig.8 tPLH propagation delay CP to TC 22 45 56 68 ns 4.5 Fig.8 tPHL propagation delay CET to TC 18 35 44 53 ns 4.5 Fig.9 tPLH propagation delay CET to TC 12 24 30 36 ns 4.5 Fig.9 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 8 and 9 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.8 tsu set-up time Dn to CP 20 9 25 30 ns 4.5 Fig.9 tsu set-up time PE to CP 35 16 44 53 ns 4.5 Fig.9 tsu set-up time CEP, CET to CP 40 23 50 60 ns 4.5 Fig.12 tsu set-up time MR to CP 20 12 25 30 ns 4.5 Fig.11 th hold time Dn, PE, CEP, CET, MR to CP 0 −10 0 0 ns 4.5 Figs 9, 11 and 12 fmax maximum clock pulse frequency 17 29 14 11 MHz 4.5 Fig.8 December 1990 9 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE). December 1990 10 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; synchronous reset 74HC/HCT162 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the MR set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the CEP and CET set-up and hold times. APPLICATION INFORMATION The HC/HCT162 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset. Fig.13 Modulo-5 counter. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 11