Cypress CY62137FV18 2-mbit (128k x 16) static ram Datasheet

CY62137FV18 MoBL®
2-Mbit (128K x 16) Static RAM
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65V–2.25V
■
Pin compatible with CY62137CV18
■
Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 5 µA
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO0 through IO15) are placed
in a high impedance state when:
■
Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Byte power down feature
■
Available in a Pb-free 48-Ball VFBGA package
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
Cypress Semiconductor Corporation
Document #: 001-08030 Rev. *E
BHE
WE
CE
OE
BLE
•
A16
A15
A14
A13
BHE
BLE
A11
CE
A12
POWER DOWN
CIRCUIT
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 01, 2007
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CY62137FV18 MoBL®
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62137FV18LL
Min
Typ [1]
Max
1.65
1.8
2.25
55
Standby ISB2 (µA)
f = fmax
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
1.6
2.5
13
18
1
5
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3]
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
IO8
BHE
A3
A4
CE
IO0
B
IO9
IO10
A5
A6
IO1
IO2
C
VSS
IO11
NC
A7
IO3
VCC
D
VCC
IO12
NC
A16
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
NC
A8
A9
A10
A11
NC
H
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the VBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 001-08030 Rev. *E
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CY62137FV18 MoBL®
DC Input Voltage [4, 5] .....................................–0.2V to 2.45V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage ......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .....................................................–0.2V to + 2.45V
Device
DC Voltage Applied to Outputs
in High Z State [4, 5].........................................–0.2V to 2.45V
CY62137FV18
Range
Ambient
Temperature
VCC [6]
Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –0.1 mA
VOL
Output LOW Voltage
IOL = 0.1 mA
VIH
Input HIGH Voltage
VCC =1.65V to 2.25V
VIL
Input LOW Voltage
VCC =1.65V to 2.25V
IIX
Input Leakage Current
IOZ
ICC
55 ns
Min
Typ [1]
Unit
Max
1.4
V
0.2
V
1.4
VCC + 0.2V
V
–0.2
0.4
V
GND < VI < VCC
–1
+1
µA
Output Leakage Current
GND < VO < VCC, output disabled
–1
+1
µA
VCC Operating Supply
Current
f = fmax = 1/tRC
VCC(max) = 2.25V
IOUT = 0 mA
CMOS levels
13
18
mA
f = 1 MHz
VCC(max) = 2.25V
1.6
2.5
mA
ISB1
VCC(max) = 2.25V
Automatic CE Power Down CE > VCC− 0.2V,
Current–CMOS
VIN>VCC – 0.2V, VIN < 0.2V)
Inputs
f = fmax (address and data only), f
= 0 (OE, WE, BHE and BLE)
1
5
µA
ISB2 [7]
Automatic CE Power Down CE > V – 0.2V,
CC
Current–CMOS
VIN > VCC – 0.2V or
Inputs
VIN < 0.2V, f = 0
VCC(max) = 2.25V
1
5
µA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max)=VCC+0.5V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 001-08030 Rev. *E
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CY62137FV18 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Test Conditions
VFBGA
Unit
75
°C/W
10
°C/W
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.80V
Unit
R1
13500
Ω
R2
10800
Ω
RTH
6000
Ω
VTH
0.80
V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
tR
Conditions
VCC for Data Retention
[7]
tCDR [8]
[9]
Description
Min
Typ [1]
Max
1.0
Data Retention Current
VCC = 1.0V, CE > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
Chip Deselect to Data Retention Time
Operation Recovery Time
Unit
V
1
4
µA
0
ns
tRC
ns
Data Retention Waveform
Figure 3. Data Retention Waveform [10]
VCC
CE or
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0V
VCC(min)
tR
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 001-08030 Rev. *E
Page 4 of 11
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CY62137FV18 MoBL®
Switching Characteristics
Over the Operating Range [11, 12]
Parameter
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
[13]
ns
55
10
ns
ns
5
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z [13, 14]
tLZCE
CE LOW to Low Z [13]
tHZCE
CE HIGH to High Z [13, 14]
tPU
CE LOW to power up
tPD
CE HIGH to power down
55
ns
tDBE
BLE/BHE LOW to data valid
55
ns
tLZBE
BLE/BHE LOW to Low Z [13]
tHZBE
BLE/BHE HIGH to High Z [13, 14]
Write Cycle
18
10
ns
ns
18
0
ns
ns
10
ns
18
ns
[15]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z [13, 14]
tLZWE
WE HIGH to Low Z [13]
18
10
ns
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 001-08030 Rev. *E
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CY62137FV18 MoBL®
Switching Waveforms
Figure 4 shows the read cycle No.1 that is address transition controlled. [16, 17]
Figure 4. Read Cycle No.1
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5 shows the read cycle No.1 that is OE controlled. [17, 18]
Figure 5. Read Cycle No. 2
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 001-08030 Rev. *E
Page 6 of 11
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CY62137FV18 MoBL®
Switching Waveforms (continued)
Figure 6 shows the read cycle No.1 that is WE controlled. [15, 19, 20]
Figure 6. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 21
tHD
DATAIN
tHZOE
Figure 7 shows the read cycle No.1 that is CE controlled. [15, 19, 20]
Figure 7. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 21
tHZOE
Notes
19. Data IO is high impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
21. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-08030 Rev. *E
Page 7 of 11
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CY62137FV18 MoBL®
Switching Waveforms (continued)
Figure 8 shows the read cycle No.1 that is WE controlled, OE LOW. [20]
Figure 8. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA IO
NOTE 21
tHD
DATAIN
tLZWE
tHZWE
Figure 9 shows the read cycle No.1 that is BHE/BLE controlled, OE LOW. [20]
Figure 9. Write Cycle No. 4
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 21
tSD
tHD
DATAIN
tLZWE
Document #: 001-08030 Rev. *E
Page 8 of 11
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CY62137FV18 MoBL®
Truth Table
CE
WE
OE
BHE BLE
Inputs or Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect or Power Down
Standby (ISB)
X
X
X
H
H
High Z
Deselect or Power Down
Standby (ISB)
L
H
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
55
Ordering Code
CY62137FV18LL-55BVXI
Package
Diagram
Package Type
51-85150 48-Ball VFBGA (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of other parts.
Document #: 001-08030 Rev. *E
Page 9 of 11
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CY62137FV18 MoBL®
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
Document #: 001-08030 Rev. *E
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
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CY62137FV18 MoBL®
Document History Page
Document Title: CY62137FV18 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-08030
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
463660
See ECN
NXR
New datasheet
*A
469180
See ECN
NSI
Minor change: moved to external web
*B
569125
See ECN
NXR
Converted from preliminary to final
Replaced 45 ns speed bin with 55 ns speed bin
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 µA to 1 µA
Changed the ISB2(max) value from 2.5 µA to 5 µA
Changed the ICCDR(typ) value from 0.5 µA to 1 µA and ICCDR(max) value from 2.5 µA to
4 µA
*C
869500
See ECN
VKN
Added footnote #12 related to tACE
*D
908120
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
Made footnote #13 applicable to AC parameters from tACE
Changed tWC specification from 45 ns to 55 ns
Changed tSCE, tAW, tPWE, tBW specification from 35 ns to 40 ns
Changed tHZWE specification from 18 ns to 20 ns
*E
1274728 See ECN VKN/AESA Changed tWC specification from 55 ns to 45 ns
Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns
Changed tHZWE specification from 20 ns to 18 ns
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08030 Rev. *E
Revised August 01, 2007
Page 11 of 11
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective
holders.
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