ATMEL AT90S8515-4PI 8-bit microcontroller with 8k bytes in-system programmable flash Datasheet

Features
• AVR - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 8K bytes of In-System Reprogrammable Flash
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– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
512 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
512 bytes Internal SRAM
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
SPI Serial Interface
VCC: 2.7 - 6.0V
Fully Static Operation
– 0 - 8 MHz 4.0 - 6.0V,
– 0 - 4 MHz 2.7 - 4.0V
Up to 8 MIPS Throughput at 8 MHz
One 8-Bit Timer/Counter with Separate Prescaler
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
Dual PWM
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Programming Lock for Software Security
8-Bit
Microcontroller
with 8K bytes
In-System
Programmable
Flash
AT90S8515
Preliminary
Description
The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR ®
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
(continued)
Pin Configurations
Rev. 0841DS–06/98
Note: This is a sumary document. For the complete
76 page document, please visit our Web site at
www.atmel.com or e-mail at [email protected]
and request literature number 0841D.
1
Block Diagram
Figure 1. The AT90S8515 Block Diagram
The AT90S8515 provides the following features: 8K bytes
of In-System Programmable Flash, 512 bytes EEPROM,
512 bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
2
AT90S8515
The device is manufactured using Atmel’s high density
non-volatile memory technology. The on-chip in-system
programmable Flash allows the program memory to be
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S8515 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The AT90S8515 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits.
AT90S8515
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
ALE
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2. Oscillator Connections
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S8515 as listed on page 46.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port C also serves as Address output when using external
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S8515 as listed on page 52.
Figure 3. External Clock Drive Configuration
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Timer/Counter1 Input Capture
function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
3
AT90S8515 Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect
address register pointers for Data Space addressing enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4. The AT90S8515 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S8515 AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 $1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
4
AT90S8515
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory.
With the relative jump and call instructions, the whole 4K
address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
AT90S8515
ize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 512 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector position. The lower the interrupt vector address the higher the
priority.
Figure 5. Memory Maps
5
AT90S8515 Register Summary
6
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
…
$00 ($20)
SREG
SPH
SPL
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
Reserved
ICR1H
ICR1L
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
USR
UCR
UBRR
ACSR
Reserved
Reserved
I
SP15
SP7
T
SP14
SP6
H
SP13
SP5
S
SP12
SP4
V
SP11
SP3
N
SP10
SP2
Z
SP9
SP1
C
SP8
SP0
18
19
19
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1A
OCF1A
-
-
-
-
-
-
OCIE1B
OCF1B
-
TICIE1
ICF1
-
TOIE0
TOV0
-
24
24
24
25
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
26
-
-
-
CS02
CS01
CS00
29
30
CTC1
CS12
PWM11
CS11
PWM10
CS10
32
33
34
34
35
35
35
35
Timer/Counter0 (8 Bit)
COM1A1
COM1A0
COM1B1
COM1B0
ICNC1
ICES1
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
-
-
-
EEPROM Address Register Low Byte
EEPROM Data Register
PORTA7
PORTA6
PORTA5
DDA7
DDA6
DDA5
PINA7
PINA6
PINA5
PORTB7
PORTB6
PORTB5
DDB7
DDB6
DDB5
PINB7
PINB6
PINB5
PORTC7
PORTC6
PORTC5
DDC7
DDC6
DDC5
PINC7
PINC6
PINC5
PORTD7
PORTD6
PORTD5
DDD7
DDD6
DDD5
PIND7
PIND6
PIND5
SPI Data Register
SPIF
WCOL
SPIE
SPE
DORD
UART I/O Data Register
RXC
TXC
UDRE
RXCIE
TXCIE
UDRIE
UART Baud Rate Register
ACD
ACO
AT90S8515
36
36
WDTOE
WDE
WDP2
WDP1
WDP0
38
-
-
-
-
EEAR8
PORTA4
DDA4
PINA4
PORTB4
DDB4
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PIND4
PORTA3
DDA3
PINA3
PORTB3
DDB3
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PIND3
EEMWE
PORTA2
DDA2
PINA2
PORTB2
DDB2
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PIND2
EEWE
PORTA1
DDA1
PINA1
PORTB1
DDB1
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PIND1
EERE
PORTA0
DDA0
PINA0
PORTB0
DDB0
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
PIND0
MSTR
CPOL
CPHA
SPR1
SPR0
FE
RXEN
OR
TXEN
CHR9
RXB8
TXB8
ACI
ACIE
ACIC
ACIS1
ACIS0
39
39
39
40
54
54
54
56
56
56
61
61
61
63
63
63
45
44
44
48
48
49
51
52
AT90S8515
AT90S8515 Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
Operation
Flags
#Clocks
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
2
3
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
7
AT90S8515 Instruction Set Summary
Mnemonics
Operands
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
LDI
Rd, K
LD
Rd, X
LD
Rd, X+
LD
Rd, - X
LD
Rd, Y
LD
Rd, Y+
LD
Rd, - Y
LDD
Rd,Y+q
LD
Rd, Z
LD
Rd, Z+
LD
Rd, -Z
LDD
Rd, Z+q
LDS
Rd, k
ST
X, Rr
ST
X+, Rr
ST
- X, Rr
ST
Y, Rr
ST
Y+, Rr
ST
- Y, Rr
STD
Y+q,Rr
ST
Z, Rr
ST
Z+, Rr
ST
-Z, Rr
STD
Z+q,Rr
STS
k, Rr
LPM
IN
Rd, P
OUT
P, Rr
PUSH
Rr
POP
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
CBI
P,b
LSL
Rd
LSR
Rd
ROL
Rd
ROR
Rd
ASR
Rd
SWAP
Rd
BSET
s
BCLR
s
BST
Rr, b
BLD
Rd, b
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
8
Description
Operation
Flags
#Clocks
Move Between Registers
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
Out Port
Push Register on Stack
Pop Register from Stack
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
AT90S8515
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
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