EMLSI EM641FT8ET-10L 512k x8 bit low power full cmos static ram Datasheet

EM641FT8T Series
Low Power, 512Kx8 SRAM
Document Title
512K x8 bit Low Power Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Nov. 20, 2007
Preliminary
0.1
0.1 Revision
IDR Current from 1.5uA to 7uA
Dec. 5, 2007
tOE from 25nsec to 30nsec with 55ns part
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM641FT8T Series
Low Power, 512Kx8 SRAM
512K x8 Bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
- Very high speed : 45ns
- Process Technology : 0.15um Full CMOS
- Organization : 512K x8
- Power Supply Voltage
=> EM641FT8T : 4.5V~5.5V
- Low Data Retention Voltage : 1.5V (MIN)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
- Package Type: 32-TSOP
The EM641FT8T is fabricated by EMLSI’s advanced full
CMOS process technology. The families support industrial
temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data
retention voltage for battery back-up operation with low
data retention current.
The EM641FT8T is available in KGD, JEDEC standard 32
pin 8.0mm x 20.0mm TSOP package.
PRODUCT FAMILY
Power Dissipation
Operating
Temperature
Vcc Range
Speed
EM641FT8T-45LF
Industrial (-40 ~ 85oC)
4.5V~5.5V
45ns
EM641FT8T-55LF
Industrial (-40 ~ 85oC)
4.5V~5.5V
EM641FT8T-70LF
Industrial (-40 ~ 85oC)
4.5V~5.5V
PIN DESCRIPTION
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Operating
(ICC1.Max)
PKG Type
1.5 µA
7mA
32-TSOP
55ns
1.5 µA
7mA
32-TSOP
70ns
1.5 µA
7mA
32-TSOP
Standby
(ISB1, Typ.)
FUNCTIONAL BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
EM641FT8T
Pre-charge Circuit
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VSS
Row Select
Product
Family
I/O0 ~ I/O7
Data
Cont
Memory Array
512K x 8
I/O Circuit
Column Select
A11 A12 A13 A14 A15 A16 A17 A18
Name
Function
Name
Function
CS
Chip select input
VCC
Power Supply
WE
OE
Output Enable input
VSS
Ground
OE
WE
Write Enable input
A0~A18
Address Inputs
I/O0~I/O7
Data Inputs/Outputs
CS
2
Control Logic
EM641FT8T Series
Low Power, 512Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Voltage on Any Pin Relative to VSS
Minimum
Unit
VIN, VOUT
-0.5 to 6.0V
V
Voltage on Vcc supply relative to VSS
VCC
-0.5 to 6.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
o
C
Note : Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device.
Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
I/O0-7
Mode
Power
H
X
X
High-Z
Deselected/ Power down
Stand by
L
L
H
Data Out
Read
Active
L
X
L
Data In
Write
Active
L
H
H
High-Z
Selected, Output Disabled
Active
Note : X means don’t care. (Must be low or high state)
3
EM641FT8T Series
Low Power, 512Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Symbol
Supply voltage
VCC
2)
Min
Typ
Max
Unit
4.5
-
5.5
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.53)
V
Input low voltage
VIL
-0.54)
-
0.6
V
Notes :
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
Note : Capacitance is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS (TA = -40oC to +85oC)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL
VIO=VSS to VCC
-1
-
1
uA
Operating power supply
ICC
IIO=0mA, CS=VIL, VIN=VIH or VIL
-
-
5
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS<0.2V, VIN<0.2V or VIN>VCC-0.2V
-
-
7
mA
45ns
-
-
65
ICC2
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL, VIN=VIL or VIH
55ns
-
-
55
70ns
-
-
45
Average operating current
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current (TTL)
ISB
CS=VIH, Other inputs=VIH or VIL
-
-
1
mA
-
1.51)
20
uA
CS>VCC-0.2V
Standby Current (CMOS)
ISB1
Other inputs = 0~VCC
(Typ. condition : VCC=5V @ 25oC)
(Max. condition : VCC=5.5V @ 85oC)
NOTES :
1.Typical values are measured at Vcc=5V, TA=25oC and not 100% tested.
4
LF
EM641FT8T Series
Low Power, 512Kx8 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
VTM3)
Input Pulse Level : 0V to VCC
Input Rise and Fall Time : 1V/ns
Input and Output reference Voltage : 0.5VCC
Output Load (See right) : CL1) = 100pF + 1 TTL (70ns)
CL1) = 30pF + 1 TTL (45ns/55ns)
R12)
Output
Notes :
R22)
CL1)
1. Including scope and Jig capacitance
2. R1 = 1800 ohm,
R2 = 990 ohm
3. VTM = VCC
4. CL = 5pF + 1 TTL (measurement with tLZ, tOLZ, tHZ, tOHZ, tWHZ)
READ CYCLE (Vcc = 4.5V to 5.5V, GND = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
45
-
55
-
70
-
ns
Address access time
tAA
-
45
-
55
-
70
ns
Chip select to output
tCO
-
45
-
55
-
70
ns
Output enable to valid output
tOE
-
25
-
30
-
35
ns
Chip select to low-Z output
tLZ
10
-
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
15
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
10
-
ns
WRITE CYCLE (Vcc = 4.5V to 5.5V, GND = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Min
Max
Min
Max
Min
Max
Unit
Write cycle time
tWC
45
-
55
-
70
-
ns
Chip select to end of write
tCW
45
-
45
-
60
-
ns
Address setup time
tAS
0
-
0
-
0
-
ns
Address valid to end of write
tAW
45
-
45
-
60
-
ns
Write pulse width
tWP
35
-
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
15
0
20
0
20
ns
Data to write time overlap
tDW
25
Data hold from write time
tDH
0
-
0
-
0
-
ns
End of write to output low-Z
tOW
5
-
5
-
5
-
ns
5
25
30
ns
EM641FT8T Series
Low Power, 512Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Transition Controlled)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (OE Controlled)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tLZ
High-Z
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM641FT8T Series
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled, OE High During WRITE)
tWC
Address
tCW2)
tWR4)
CS
tAW
tWP1)
WE
tAS3)
OE
Data in
tDH
tDW
High-Z
tOHZ
Data out
High-Z
Data Valid
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS3)
tCW2)
tWR4)
CS
tAW
tWP1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
EM641FT8T Series
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (WE Controlled, OE LOW)
tWC
Address
tWR4)
tCW2)
CS
tAW
tAS3)
tWP1)
WE
tDW
Data in
High-Z
Data Valid
tWHZ
Data out
Data Undefined
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among
CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
tDH
High-Z
EM641FT8T Series
Low Power, 512Kx8 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Operation Recovery Time
tRDR
Test Condition
ISB1 Test Condition
(Chip Disabled) 1)
ISB1 Test Condition
(Chip Disabled) 1)
See data retention wave form
Min
Typ2)
Max
Unit
1.5
-
-
V
-
1
7
µA
0
-
-
tRC
-
-
NOTES
1. See the ISB1 measurement condition of data sheet page 4.
2. Typical value is measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
Vcc
5V
2.2V
VDR
VDR
CS
GND
1.5V
CS > Vcc-0.2V
9
tRDR
ns
EM641FT8T Series
Low Power, 512Kx8 SRAM
PACKAGE DIMENSIONS
32Pin - TSOP Type1
Unit : millimeters/Inches
10
EM641FT8T Series
Low Power, 512Kx8 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Product Type
10. Speed
3. Density
4. Function
9. Package
5. Technology
8. Generation
6. Operating Voltage
7. Organization
1. Memory Component
EM --------------------- Memory
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------F ----------------------G ----------------------
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
1st generation
2nd generation
3rd generation
4th generation
5th generation
6th generation
7th generation
8th generation
9. Package
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V --------------------- 32 SOP
5. Technology
F ------------------------- Full CMOS
10. Speed
45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ----------------------
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
45ns
55ns
70ns
85ns
100ns
120ns
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
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