STMicroelectronics M27C2001-70XB1TR 2 mbit (256kb x 8) uv eprom and otp eprom Datasheet

M27C2001
2 Mbit (256Kb x 8) UV EPROM and OTP EPROM
Features
■
5V ± 10% supply voltage in Read operation
■
Access time: 55ns
■
Low power consumption:
– Active Current 30mA at 5MHz
– Standby Current 100µA
■
Programming voltage: 12.75V ± 0.25V
■
Programming time: 100µs/word
■
Electronic signature
– Manufacturer Code: 20h
– Device Code: 61h
■
32
32
1
1
FDIP32W (F)
PDIP32 (B)
PLCC32 (C)
TSOP32 (N)
8 x 20 mm
Packages
– ECOPACK® packages available.
May 2006
Rev 4
1/25
www.st.com
1
M27C2001
Contents
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Two Line Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
PRESTO II Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
Program Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Program Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Erasure operation (applies to UV EPROM) . . . . . . . . . . . . . . . . . . . . . . . 10
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
List of tables
M27C2001
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
3/25
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance (TA = 25°C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Mode DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) . . . . . . . . . . . . 14
Programming Mode DC Characteristics
(TA = 25°C; VCC = 6.25V ± 0.25V; V PP = 12.75V ± 0.25V) . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) . . . . . . . . . . . . 15
Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming Mode AC Characteristics
(TA = 25°C; VCC = 6.25 ± 0.25V; VPP = 12.75 ± 0.25V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data . . . . . . 19
PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . . 20
PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data. . . . . . . . . . . . 21
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data. . . . 22
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M27C2001
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
LCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programming and Verify Modes AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline . . . . . . . . . . . . . 19
PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline. . . . . . . . . . . . . . . . . . . . . 20
PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline . . . . . . . . . . . . . . . . . . . 21
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline . . . . . . . . . . . 22
4/25
Summary description
1
M27C2001
Summary description
The M27C2001 is a high speed 2 Mbit EPROM offered in the two ranges UV (ultra violet
erase) and OTP (one time programmable). It is ideally suited for microprocessor systems
requiring large programs and is organized as 262,144 by 8 bits.
The FDIP32W (window ceramic frit-seal package) has a transparent lids which allow the
user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be
written to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27C2001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.
In order to meet environmental requirements, ST offers the M27C2001 in ECOPACK ®
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic Diagram
VCC
VPP
18
8
A0-A17
P
Q0-Q7
M27C2001
E
G
VSS
AI00716B
Table 1.
5/25
Signal Names
A0-A17
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
M27C2001
Summary description
Figure 2.
DIP Connections
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
M27C2001
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
P
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
AI00717
A12
A15
A16
VPP
VCC
P
A17
LCC Connections
1 32
9
M27C2001
25
A14
A13
A8
A9
A11
G
A10
E
Q7
17
VSS
Q3
Q4
Q5
Q6
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
Figure 3.
AI00718
6/25
Summary description
Figure 4.
M27C2001
TSOP Connections
A11
A9
A8
A13
A14
A17
P
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
8
9
16
32
M27C2001
(Normal)
25
24
17
AI01153B
7/25
G
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
M27C2001
2
Device operation
Device operation
The operating modes of the M27C2001 are listed in the Table 2. A single power supply is
required in the read mode. All inputs are TTL levels except for V PP and 12V on A9 for
Electronic Signature.
2.1
Read Mode
The M27C2001 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is
available at the output after a delay of tGLQV from the falling edge of G, assuming that E has
been low and the addresses have been stable for at least tAVQV-t GLQV.
2.2
Standby Mode
The M27C2001 has a standby mode which reduces the supply current from 30mA to 100µA.
The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are in a high impedance state, independent of
the G input.
2.3
Two Line Output Control
Because EPROM devices are usually used in larger memory arrays, this product features a
2 line control function which accommodates the use of multiple memory connection. The
two line control function allows:
a)
the lowest possible memory power dissipation,
b)
complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, ICC, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should
8/25
Device operation
M27C2001
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V CC and VSS for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C2001 is in the programming mode when VPP input is at 12.75V, E is at VIL and P is
pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V CC is specified to be
6.25 ± 0.25V.
2.6
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II
consists of applying a sequence of 100µs program pulses to each byte until a correct verify
occurs (see Figure 5). During programming and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Figure 5.
Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
P = 100µs Pulse
NO
++n
= 25
YES
FAIL
NO
VERIFY
++ Addr
YES
Last
Addr
NO
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI00715C
9/25
M27C2001
2.7
Device operation
Program Inhibit
Programming of multiple M27C2001s in parallel with different data is also easily
accomplished. Except for E, all like inputs including G of the parallel M27C2001 may be
common. A TTL low level pulse applied to a M27C2001's P input, with E low and VPP at
12.75V, will program that M27C2001. A high level E input inhibits the other M27C2001s from
being programmed.
2.8
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were
correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at
12.75V and VCC at 6.25V.
2.9
Electronic Signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an
EPROM that will identify its manufacturer and type. This mode is intended for use by
programming equipment to automatically match the device to be programmed with its
corresponding programming algorithm. The ES mode is functional in the 25 ± 5°C ambient
temperature range that is required when programming the M27C2001. To activate the ES
mode, the programming equipment must force 11.5 to 12.5V on address line A9 of the
M27C2001 with V PP = VCC = 5V. Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to V IH. All other address lines must be
held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics
M27C2001, these two identifier bytes are given in Table 3 and can be read-out on outputs
Q7 to Q0.
2.10
Erasure operation (applies to UV EPROM)
The erasure characteristics of the M27C2001 are such that erasure begins when the cells
are exposed to light with wavelengths shorter than approximately 4000Å. It should be noted
that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000Å
range. Data shows that constant exposure to room level fluorescent lighting could erase a
typical M27C2001 in about 3 years, while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the M27C2001 is to be exposed to these types of
lighting conditions for extended periods of time, it is suggested that opaque labels be put
over the M27C2001 window to prevent unintentional erasure. The recommended erasure
procedure for the M27C2001 is exposure to short wave ultraviolet light which has
wavelength of 2537Å. The integrated dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15W-s/cm2. The erasure time with this dosage is approximately 15
to 20 minutes using an ultraviolet lamp with 12000µW/cm2 power rating. The M27C2001
should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be removed before erasure.
10/25
Device operation
M27C2001
Table 2.
Operating Modes
Mode
Note:
E
G
P
A9
VPP
Q7-Q0
Read
VIL
VIL
X
X
VCC or VSS
Data Out
Output Disable
VIL
VIH
X
X
VCC or VSS
Hi-Z
Program
VIL
VIH
VIL Pulse
X
VPP
Data In
Verify
VIL
VIL
VIH
X
VPP
Data Out
Program Inhibit
VIH
X
X
X
VPP
Hi-Z
Standby
VIH
X
X
X
VCC or VSS
Hi-Z
Electronic Signature
VIL
VIL
VIH
VID
VCC
Codes
X = VIH or VIL, VID = 12 ± 0.5V.
Table 3.
11/25
Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex
Data
Manufacturer’s
Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
0
1
1
0
0
0
0
1
61h
M27C2001
3
Maximum ratings
Maximum ratings
Except for the rating "Operating Temperature Range", stresses above those listed in the
Table 4 may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
Table 4.
Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
(1)
Value
Unit
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
Input or Output Voltage (except A9)
–2 to 7
V
Supply Voltage
–2 to 7
V
–2 to 13.5
V
–2 to 14
V
VIO
(2)
VCC
VA9 (2)
VPP
A9 Voltage
Program Supply Voltage
1. Depends on range.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than
20ns. Maximum DCvoltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less
than 20ns.
12/25
DC and AC parameters
4
M27C2001
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5, Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
AC Measurement conditions
High Speed
Standard
Input Rise and Fall Times
≤10ns
≤20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Table 6.
Symbol
Capacitance (1) (TA = 25°C, f = 1 MHz)
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
1. Sampled only, not 100% tested
Figure 6.
AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
2.0V
0.8V
AI01822
13/25
M27C2001
Figure 7.
DC and AC parameters
AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
Table 7.
Symbol
AI01823B
Read Mode DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Parameter
Test Condition
Min
Max
Unit
0V ≤VIN ≤VCC
±10
µA
0V ≤VOUT ≤VCC
±10
µA
E = VIL, G = V IL,
IOUT = 0mA, f = 5MHz
30
mA
E = VIH
1
mA
E > VCC – 0.2V
100
µA
VPP = VCC
10
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
Input High Voltage
2
VCC + 1
V
0.4
V
VIH
(2)
VOL
Output Low Voltage
VOH
Output High Voltage TTL
IOH = –400µA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC – 0.7V
V
IOL = 2.1mA
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
14/25
DC and AC parameters
Table 8.
M27C2001
Programming Mode DC Characteristics (1)
(TA = 25°C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Parameter
Test Condition
Min
0 ≤VIN ≤VIH
Max
Unit
±10
µA
50
mA
50
mA
ILI
Input Leakage Current
ICC
Supply Current
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage TTL
VID
A9 Voltage
E = V IL
IOL = 2.1mA
IOH = –400µA
2.4
V
11.5
12.5
V
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 9.
Read Mode AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C2001
Symbol
Alt
Parameter
Test
Condition
-55 (2)
Min
-70
Max
Min
-80
Max
-90
Min Max
Min
Unit
Max
tAVQV
tACC
Address Valid
to Output
Valid
E = VIL,
G = V IL
55
70
80
90
ns
tELQV
tCE
Chip Enable
Low to Output
Valid
G = V IL
55
70
80
90
ns
tGLQV
tOE
Output Enable
Low to Output
Valid
E = V IL
30
35
40
40
ns
tEHQZ (3)
tDF
Chip Enable
High to Output
Hi-Z
tGHQZ (3)
tDF
tAXQX
tOH
G = V IL
0
30
0
30
0
30
0
30
ns
Output Enable
High to Output
Hi-Z
E = V IL
0
30
0
30
0
30
0
30
ns
Address
Transition to
Output
Transition
E = VIL,
G = V IL
0
0
0
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. In case of 55ns speed see High Speed AC measurement conditions.
3. Sampled only, not 100% tested.
15/25
0
ns
M27C2001
DC and AC parameters
Table 10.
Read Mode AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; V CC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C2001
Symbol
Alt
Parameter
Test Condition
-10
-12
-15/-20/-25
Min Max Min
Max
Min
Unit
Max
tAVQV
tACC
Address Valid to
Output Valid
E = V IL, G = VIL
100
120
150
ns
tELQV
tCE
Chip Enable Low
to Output Valid
G = VIL
100
120
150
ns
tGLQV
tOE
Output Enable
Low to Output
Valid
E = VIL
50
50
60
ns
tEHQZ (2)
tDF
Chip Enable
High to Output
Hi-Z
G = VIL
0
30
0
40
0
50
ns
tGHQZ (2)
tDF
Output Enable
High to Output
Hi-Z
E = VIL
0
30
0
40
0
50
ns
tAXQX
tOH
Address
Transition to
Output Transition
E = V IL, G = VIL
0
0
0
ns
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
16/25
DC and AC parameters
Figure 8.
M27C2001
Read Mode AC Waveforms
VALID
A0-A17
tAVQV
VALID
tAXQX
E
tGLQV
tEHQZ
G
tELQV
tGHQZ
Hi-Z
Q0-Q7
AI00719B
Table 11.
Programming Mode AC Characteristics(1)
(TA = 25°C; VCC = 6.25 ± 0.25V; VPP = 12.75 ± 0.25V)
Test
Condition
Symbol
Alt
Parameter
tAVPL
tAS
Address Valid to Program Low
2
µs
tQVPL
tDS
Input Valid to Program Low
2
µs
tVPHPL
tVPS
VPP High to Program Low
2
µs
tVCHPL
tVCS
VCC High to Program Low
2
µs
tELPL
tCES
Chip Enable Low to Program Low
2
µs
tPLPH
tPW
Program Pulse Width
95
tPHQX
tDH
Program High to Input Transition
2
µs
tQXGL
tOES
Input Transition to Output Enable Low
2
µs
tGLQV
tOE
Output Enable Low to Output Valid
tDFP
Output Enable High to Output Hi-Z
0
tAH
Output Enable High to Address Transition
0
tGHQZ
(2)
tGHAX
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
17/25
Min
Max
105
Unit
µs
100
ns
130
ns
ns
M27C2001
DC and AC parameters
Figure 9.
Programming and Verify Modes AC Waveforms
VALID
A0-A17
tAVPL
Q0-Q7
DATA IN
tQVPL
DATA OUT
tPHQX
VPP
tVPHPL
tGLQV
tGHQZ
VCC
tVCHPL
tGHAX
E
tELPL
P
tPLPH
tQXGL
G
PROGRAM
VERIFY
AI00720
18/25
Package mechanical data
5
M27C2001
Package mechanical data
Table 12.
FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical
Data
mm
inches
Symbol
Typ
Min
Max
A
Typ
Min
5.72
Max
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
0.41
0.56
0.016
0.022
—
—
—
—
B
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
41.73
42.04
1.643
1.655
D2
38.10
—
—
1.500
—
—
E
15.24
—
—
0.600
—
—
13.06
13.36
0.514
0.526
—
—
0.100
—
—
—
—
0.590
—
—
16.18
18.03
0.637
0.710
2.49
0.060
E1
e
2.54
eA
14.99
eB
L
3.18
S
1.52
∅
7.11
0.125
—
—
α
4°
11°
N
32
0.280
0.098
—
—
4°
11°
32
Figure 10. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
B1
B
A
L
e
α
eA
D2
C
eB
D
S
N
∅
E1
E
1
FDIPW-a
1. Drawing is not to scale.
19/25
M27C2001
Package mechanical data
Table 13.
PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
A
—
A1
A2
Min
Max
5.08
—
0.200
0.38
—
0.015
—
3.56
4.06
0.140
0.160
0.38
0.51
0.015
0.020
—
—
—
—
C
0.20
0.30
0.008
0.012
D
41.78
42.04
1.645
1.655
B
B1
1.52
Typ
0.060
D2
38.10
—
—
1.500
—
—
E
15.24
—
—
0.600
—
—
13.59
13.84
0.535
0.545
—
—
0.100
—
—
0.600
E1
e1
2.54
eA
15.24
—
—
—
—
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
α
0°
10°
0°
10°
N
32
32
Figure 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
1. Drawing is not to scale.
20/25
Package mechanical data
Table 14.
M27C2001
PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
2.54
3.56
0.100
0.140
A1
1.52
2.41
0.060
0.095
A2
0.38
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
F
0.00
0.25
0.000
0.010
e
1.27
R
0.050
0.89
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
A1
A2
1 N
B1
E2
e
E1 E
E3
F
B
0.51 (.020)
E2
1.14 (.045)
A
Nd
R
D2
CP
D2
PLCC-B
1. Drawing is not to scale.
21/25
M27C2001
Package mechanical data
Table 15.
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package
Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
Typ
Min
1.20
Max
0.047
A1
0.05
0.15
0.002
0.007
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
e
—
—
—
—
L
0.50
0.50
0.70
0.020
0.020
0.028
α
0°
5°
0°
5°
N
32
32
CP
0.10
0.004
Figure 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
N
1
e
E
B
N/2
A
D1
CP
D
DIE
C
TSOP-a
A1
α
L
1. Drawing is not to scale.
22/25
Part numbering scheme
6
M27C2001
Part numbering scheme
Table 16.
Ordering Information Scheme
Example:
M27C2001
-55 X
C
1 TR
Device Type
M27
Supply Voltage
C = 5V
Device Function
2001 = 2 Mbit (256Kb x 8)
Speed
– 55 (1) = 55 ns
– 70 = 70 ns
– 80 = 80 ns
– 90 = 90 ns
– 10 = 100 ns
Not For New Design (2)
– 12 = 120 ns
– 15 = 150 ns
– 20 = 200 ns
– 25 = 250 ns
VCC Tolerance
X = ± 5%
blank = ± 10%
Package
F = FDIP32W
B = PDIP32
C = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Options
TR = Tape & Reel Packing
1. High Speed, see AC Characteristics section for further information.
2. These speeds are replaced by the 100ns.
For a list of available options (Speed, Package, etc....) or for further information on any
aspect of this de-vice, please contact the STMicroelectronics Sales Office nearest to you.
23/25
M27C2001
7
Revision history
Revision history
Structure
Table 17.
Document revision history
Date
Revision
Changes
June 1998
1
First Issue.
20-Sep-2000
2
AN620 Reference removed.
29-Nov-2000
3
PLCC codification changed (Table 14).
10-May-2006
4
Structure modified, ECOPACK text added.
LCCC32W package and the additional burn-in option (X) from
Ordering information scheme removed.
24/25
M27C2001
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