IDT ICS844801I-24 Femtoclocksâ ¢ crystal-to-lvds 400mhz frequency synthesizer Datasheet

PRELIMINARY
ICS844801I-24
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
400MHZ FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844801I-24 is a 400MHz Frequency
ICS
Synthesizer and a member of the HiPerClocksTM
HiPerClockS™
family of high performance devices from IDT.
The ICS844801I-24 uses an 18pF par allel
resonant crystal over the range of 21.5625MHz 25.3125MHz. The ICS844801I-24 has excellent <1ps phase
jitter performance, over the 12kHz - 20MHz integration range.
The ICS844801I-24 is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
• One differential LVDS output
• Crystal oscillator interface, 18pF parallel resonant crystal
(21.5625MHz - 25.3125MHz)
• Output frequency range: 172.5MHz - 202.5MHz, and
345MHz - 405MHz
• VCO range: 690MHz - 810MHz
• RMS phase jitter @ 400MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.57ps (typical) @ 3.3V
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
COMMON CONFIGURATION TABLE
Inputs
Crystal Frequency (MHz)
FREQ_SEL
M
N
25
0
32
2
Multiplication
Value M/N
16
25
1
32
4
8
Output Frequency
(MHz)
400
200
BLOCK DIAGRAM
PIN ASSIGNMENT
FREQ_SEL Pullup
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
690MHz - 810MHz
FREQ_SEL N
0
÷2
1
÷4
Q
nQ
VDDA
XTAL_OUT
XTAL_IN
GND
1
2
3
4
8
7
6
5
VDD
Q
nQ
FREQ_SEL
ICS844801I-24
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷32 (fixed)
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
Power
4
VDDA
XTAL_OUT,
XTAL_IN
GND
5
FREQ_SEL
Input
6, 7
nQ, Q
Output
Differential clock outputs. LVDS interface levels.
8
VDD
Power
Core supply pin.
2, 3
Type
Description
Analog supply pin.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Power supply ground.
Input
Power
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
2
Minimum
Typical
Maximum
Units
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Power Supply Voltage
3.135
3.3
3.465
V
VDD – 0.07
3.3
VDD
VDDA
Analog Supply Voltage
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
7
mA
V
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Power Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
VDD – 0.07
2.5
VDD
V
IDD
Power Supply Current
75
mA
IDDA
Analog Supply Current
7
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
VDD = 3.465V or 2.625V, VIN = 0V
Typical
5
-150
µA
µA
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Minimum
Typical
415
Maximum
Units
mV
∆ VOD
VOD Magnitude Change
40
mV
VOS
Offset Voltage
∆ VOS
VOS Magnitude Change
1.22
V
50
mV
NOTE: Please refer to Parameter Measurement Information for output information.
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Minimum
Typical
380
Maximum
Units
mV
∆ VOD
VOD Magnitude Change
40
mV
VOS
Offset Voltage
∆ VOS
VOS Magnitude Change
1.17
V
50
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25.3125
MHz
Equivalent Series Resistance (ESR)
21.5625
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
172.5
202.5
MHz
345
405
MHz
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
tR / tF
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Minimum
200MHz @ Integration Range:
12kHz - 20MHz
400MHz @ Integration Range:
12kHz - 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
Typical
0.62
ps
0.57
ps
305
ps
50
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
fOUT
tjit(Ø)
tR / tF
Parameter
Test Conditions
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
200MHz @ Integration Range:
12kHz - 20MHz
400MHz @ Integration Range:
12kHz - 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
4
Minimum
Maximum
Units
172.5
Typical
202.5
MHz
345
405
MHz
0.64
ps
0.57
ps
310
ps
50
%
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 400MHZ @ 3.3V
ä
400MHz
SONET Filter
RMS Phase Noise Jitter
12kHz to 20MHz = 0.57ps (typical)
-40
-50
-60
-70
-80
-90
-100
-110
-120
Raw Phase Noise Data
ä
ä
NOISE POWER dBc
Hz
0
-10
-20
-30
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
a SONET Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
3.3V±5%
POWER SUPPLY
Float GND
+
–
2.5V±5%
POWER SUPPLY
Float GND
+
–
LVDS
Qx
SCOPE
LVDS
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQ
Q
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VVDD
DD
out
80%
DC Input
VSW I N G
Clock
Outputs
LVDS
➤
80%
➤
20%
20%
tR
out
tF
VOS/∆ VOS
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
VDD
V
DD
out
➤
➤
LVDS
100
VOD/∆ VOD
out
➤
DC Input
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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APPLICATION INFORMATION
POWER SUPPLY F ILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to r andom noise. The ICS844801I-24
provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA
should be individually connected to the pow er supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how a 10Ω
resistor along with a 10µF and a .01µF bypass capacitor
should be connected to each VDDA pin. The 10Ω resistor can
also be replaced by a ferrite bead.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844801I-24 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM
FOR
LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS dr ivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V or 2.5V
VDD
LVDS
+
R1
100
-
100 Ω Differential Transmission
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844801I-24.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844801I-24 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
·
Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 277.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.277W * 90.5°C/W = 110.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ JA FOR 8 LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
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RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS844801I-24 is: 1622
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
8
A
--
1.2 0
A1
0.05
0.1 5
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
E
E1
3.1 0
6.40 BASIC
4.30
e
4.5 0
0.65 BASIC
L
0.45
0.7 5
α
0°
8°
aaa
--
0.1 0
Reference Document: JEDEC Publication 95, MO-153
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TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844801AGI-24
4AI24
8 Lead TSSOP
tube
-40°C to 85°C
ICS844801AGI-24T
4AI24
8 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS844801AGI-24LF
AI24L
8 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS844801AGI-24LFT
AI24L
8 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ LVDS 400MHZ FREQUENCY SYNTHESIZER
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
[email protected]
480-763-2056
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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