Cypress CY29948AIT 2.5v or 3.3v, 200-mhz, 1:12 clock distribution buffer Datasheet

CY29948
2.5V or 3.3V, 200-MHz, 1:12 Clock
Distribution Buffer
Features
Description
• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 150 ps typical output-to-output skew
• Pin compatible with MPC948, MPC948L, MPC9448
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
The CY29948 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or
LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:24. The outputs can also be
three-stated via the three-state input TS#. Low
output-to-output skews make the CY29948 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
The CY29948 also provides a synchronous output enable
input for enabling or disabling the output clocks. Since this
input is internally synchronized to the input clock, potential
output glitching or runt pulse generation is eliminated.
Block Diagram
Cypress Semiconductor Corporation
Document #: 38-07288 Rev. *C
•
198 Champion Court
•
VSS
Q0
VDDC
Q1
VSS
Q2
VDDC
Q3
29
28
27
26
25
16
VSS
TS#
CY29948
14
15
SYNC_OE
1
2
3
4
5
6
7
8
VDDC
Q8
TCLK_SEL
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
12
13
Q0-Q11
VSS
Q9
12
31
30
1
9
TCLK
10
11
0
Q11
PECL_CLK
PECL_CLK#
VDDC
VDDC
Q10
VDD
32
Pin Configuration
24
23
22
21
20
19
18
17
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2006
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CY29948
Pin Description[1]
Pin
Name
PWR
3
PECL_CLK
I, PU
PECL Input Clock
4
PECL_CLK#
I, PD
PECL Input Clock
2
TCLK
I, PU
External Reference/Test Clock Input
9, 11, 13, 15,
17, 19, 21, 23,
25, 27, 29, 31
Q(11:0)
1
TCLK_SEL
I, PU
Clock Select Input. When LOW, PECL clock is selected. When HIGH
TCLK is selected.
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled.
When set LOW the outputs are disabled in a LOW state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output buffers
are three-stated. When set HIGH, the output buffers are enabled.
10, 14, 18, 22,
26, 30
VDDC
7
VDD
2.5V or 3.3V Power Supply
8, 12, 16, 20,
24, 28, 32
VSS
Common Ground
VDDC
I/O
O
Description
Clock Outputs
2.5V or 3.3V Power Supply for Output Clock Buffers
Output Enable/Disable
The CY29948 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are
disabled in a LOW state. When SYNC_OE is set HIGH, the
outputs are enabled as shown in Figure 1.
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
Note:
1. PD = Internal pull-down, PU = Internal pull-up.
Document #: 38-07288 Rev. *C
Page 2 of 8
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CY29948
Maximum Ratings[2]
Storage Temperature: ................................ –65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
Operating Temperature: ................................ –40°C to +85°C
VSS < (Vin or Vout) < VDD
Maximum ESD protection: .............................................. 2 kV
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
DC Parameters VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range.
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min.
Typ.
Max.
Unit
VDD = 3.3V, PECL_CLK single ended
1.49
–
1.825
V
VDD = 2.5V, PECL_CLK single ended
1.10
–
1.45
All other inputs
VSS
–
0.8
VDD = 3.3V, PECL_CLK single ended
2.135
–
2.42
VDD = 2.5V, PECL_CLK single ended
1.75
–
2.0
All other inputs
V
2.0
–
VDD
IIL
Input Low Current[3]
–
–
–100
IIH
Input High
Current[3]
–
–
100
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
–
1000
mV
VCMR
Common Mode Range[4]
PECL_CLK
VDD = 3.3V
VDD – 2.0
–
VDD – 0.6
V
VDD = 2.5V
VDD – 1.2
–
VDD – 0.6
–
0.4
V
IOH = –20 mA, VDD = 3.3V
2.5
–
–
V
IOH = –20 mA, VDD = 2.5V
1.8
–
–
–
5
7
mA
VDD = 3.3V, Outputs @ 100 MHz,
CL = 30 pF
–
180
–
mA
VDD = 3.3V, Outputs @ 160 MHz,
CL = 30 pF
–
270
–
VDD = 2.5V, Outputs @ 100 MHz,
CL = 30 pF
–
125
–
VDD = 2.5V, Outputs @ 160 MHz,
CL = 30 pF
–
190
–
VDD = 3.3V
12
15
18
VDD = 2.5V
14
18
22
–
4
–
Voltage[5]
VOL
Output Low
VOH
Output High Voltage[5]
IDDQ
Quiescent Supply
Current
IDD
Dynamic Supply
Current
Zout
Cin
Output Impedance
Input Capacitance
IOL = 20 mA
µA
Ω
pF
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07288 Rev. *C
Page 3 of 8
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CY29948
AC Parameters[6] VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified operating range.
Parameter
Fmax
Tpd
Description
Conditions
Input Frequency[7]
Typ.
Max.
Unit
VDD = 3.3V
–
200
MHz
VDD = 2.5V
–
170
4.0
–
8.0
4.4
–
8.9
6.0
–
10.0
6.4
–
10.9
45
–
55
%
[7]
VDD = 3.3V
PECL_CLK to Q Delay[7]
VDD = 2.5V
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
TCLK to Q Delay[7]
[7, 8, 9]
Measured at VDD/2
Min.
ns
FoutDC
Output Duty Cycle
tpZL, tpZH
Output Enable Time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
–
10
ns
–
150
250
ps
–
–
1.5
ns
Tskew
Output-to-Output Skew
Tskew(pp)
Part-to-Part Skew
Ts
Set-up Time[7, 10]
[7, 9]
[11]
PECL_CLK to Q
TCLK to Q
[7, 10]
Th
Hold Time
Tr/Tf
Output Clocks Rise/Fall Time[9]
–
–
2.0
SYNC_OE to PECL_CLK
1.0
–
–
SYNC_OE to TCLK
0.0
–
–
PECL_CLK to SYNC_OE
0.0
–
–
TCLK to SYNC_OE
1.0
–
–
0.8V to 2.0V, VDD = 3.3V
0.20
–
1.0
0.6V to 1.8V, VDD = 2.5V
0.20
–
1.3
ns
ns
ns
CY29948 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
VTT
R T = 50 ohm
VTT
Figure 2. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29948 DUT
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 3. PECL_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. See Figures 2 and 3.
10. Setup and hold times are relative to the falling edge of the input clock
11. Part-to-Part skew at a given temperature and voltage.
Document #: 38-07288 Rev. *C
Page 4 of 8
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CY29948
PEC L_C LK
V CMR
VPP
PEC L_C LK
VCC
Q
V C C /2
t
PD
GND
Figure 4. Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
t PD
GND
Figure 5. LVCMOS Propagation Delay (TPD) Test Reference
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 6. Output Duty Cycle (FoutDC)
VCC
VCC /2
GND
VCC
VCC /2
GND
t SK(0)
Figure 7. Output-to-Output Skew tsk(0)
Document #: 38-07288 Rev. *C
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CY29948
Ordering Information
Part Number
Package Type
Production Flow
CY29948AI
32 Pin TQFP
Industrial, -40°C to +85°C
CY29948AIT
32 Pin TQFP - Tape and Reel
Industrial, -40°C to +85°C
CY29948AC
CY29948ACT
32 Pin TQFP
Commercial, 0°C to +70°C
32 Pin TQFP - Tape and Reel
Commercial, 0°C to +70°C
32 Pin TQFP
Industrial, -40°C to +85°C
Lead-free
CY29948AXI
CY29948AXIT
32 Pin TQFP - Tape and Reel
Industrial, -40°C to +85°C
CY29948AXC
32 Pin TQFP
Commercial, 0°C to +70°C
32 Pin TQFP - Tape and Reel
Commercial, 0°C to +70°C
CY29948AXCT
Document #: 38-07288 Rev. *C
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CY29948
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-B
All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-07288 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY29948
Revision History
Document Title: CY29948 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
Document Number: 38-07288
ECN NO.
Issue
Date
**
111099
02/13/02
BRK
New datasheet
*A
116782
08/14/02
HWT
Added Commercial Temperature Range
REV.
Orig. of
Change
Description of Change
*B
122880
12/22/02
RBI
Added power up requirements to Maximum Ratings
*C
428221
See ECN
RGL
Added Lead-free devices
Document #: 38-07288 Rev. *C
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