NSC CLC5623IN Triple, high output, video amplifier Datasheet

N
CLC5623
Triple, High Output, Video Amplifier
General Description
Features
The CLC5623 has a new output stage that delivers high output
drive current (130mA), but consumes minimal quiescent supply
current (3.0mA/ch) from a single 5V supply. Its current feedback
architecture, fabricated in an advanced complementary bipolar
process, maintains consistent performance over a wide range of
gains and signal levels, and has a linear-phase response up to
one half of the -3dB frequency.
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Applications
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The CLC5623 offers superior dynamic performance with a
148MHz small-signal bandwidth, 370V/µs slew rate and 4.4ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5623 well suited for many battery-powered personal
communication/computing systems.
The ability to drive low-impedance, highly capacitive loads,
with minimum distortion, makes the CLC5623 ideal for cable
applications. The CLC5623 will drive a 100Ω load with only
-78/-94dBc second/third harmonic distortion (Av = +2, Vout =
2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it
produces only -82/-96dBc second/third harmonic distortion.
The CLC5623 can also be used for driving differential-input stepup transformers for applications such as Asynchronous Digital
Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber
Lines (HDSL).
When driving the input of high-resolution A/D converters, the
CLC5623 provides excellent -86/-96dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast
settling time.
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■
■
■
■
Video line driver
ADSL/HDSL driver
Coaxial cable driver
UTP differential line driver
Transformer/coil driver
High capacitive load driver
Portable/battery-powered applications
Differential A/D driver
Maximum Output Voltage vs. RL
10
9
Output Voltage (Vpp)
The CLC5623 offers 0.1dB gain flatness to 15MHz and differential gain and phase errors of 0.06% and 0.06°. These features are
ideal for professional and consumer video applications.
130mA output current
0.06%, 0.06° differential gain, phase
3.0mA/ch supply current
148MHz bandwidth (Av = +2)
-86/-96dBc HD2/HD3 (1MHz)
18ns settling to 0.05%
370V/µs slew rate
Stable for capacitive loads up to 1000pf
Single 5V or ±5V supplies
8
VCC = ±5V
7
6
5
4
3
Vs = +5V
2
1
10
100
Typical Application
Pinout
DIP & SOIC
6.8µF
+
5kΩ
5kΩ
5
6
+
4
0.1µF
1/3
CLC5623
-
11
1kΩ
1kΩ
0.1µF
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
75Ω
7
0.1µF
10m of 75Ω
Coaxial Cable
Vo
75Ω
NC
1
14 OUT2
NC
2
13 -IN2
- +
+5V
0.1µF
1000
RL (Ω)
Single Supply Cable Driver
Vin
CLC5623
Triple, High Output, Video Amplifier
June 1999
NC
3
12 +IN2
+Vs
4
11 -Vs
+IN1
5
10 +IN3
-IN1
6
OUT1
7
- +
+ -
9
-IN3
8
OUT3
http://www.national.com
+5V Characteristics (A
1
v = +2, Rf = 750Ω, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC),Vs = +5V ,Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC5623IN
TYP
+25°C
MIN/MAX RATINGS
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.5Vpp
-0.1dB bandwidth
Vo = 0.5Vpp
gain peaking
<200MHz, Vo = 0.5Vpp
gain rolloff
<30MHz, Vo = 0.5Vpp
linear phase deviation
<30MHz, Vo = 0.5Vpp
differential gain
NTSC, RL = 150Ω to -1V
differential phase
NTSC, RL = 150Ω to -1V
107
14
0
0.3
1.0
0.03
0.08
85
13
0.5
0.7
2.0
–
–
75
10
0.9
0.8
2.4
–
–
75
10
0.9
0.8
2.4
–
–
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
4.5
17
11
280
6.0
25
15
195
6.4
40
18
165
6.8
60
18
150
ns
ns
%
V/µs
2V step
1V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
crosstalk, all hostile (input referred) 10MHz, 1Vpp
-76
-85
-63
-88
-96
-65
–
–
-58
–
–
-62
–
–
-56
–
–
-60
–
–
-56
–
–
-60
dBc
dBc
dBc
dBc
dBc
dBc
4.9
6.6
11.1
-51
-49
5.9
8.5
14.7
–
–
6.4
9.3
15.8
–
–
6.4
9.3
15.8
–
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
dB
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current per channel
1
8
6
40
6
25
48
45
3.0
4
–
18
–
14
–
45
43
3.4
6
–
22
–
16
–
43
41
3.6
6
–
24
–
17
–
43
41
3.6
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
mA
0.86
1.8
4.2
0.8
4.0
1.0
4.1
0.9
100
70
0.50
2.75
4.1
0.9
3.9
1.1
4.0
1.0
80
105
0.45
2.75
4.1
0.9
3.9
1.1
4.0
1.0
65
105
0.45
2.75
4.0
1.0
3.8
1.2
3.9
1.1
40
140
MΩ
pF
V
V
V
V
V
V
mA
mΩ
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
input voltage range, High
input voltage range, Low
output voltage range, High
RL = 100Ω
output voltage range, Low
RL = 100Ω
output voltage range, High
RL = ∞
output voltage range, Low
RL = ∞
output current
output resistance, closed loop
DC
NOTES
A
A
A
A
B
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Notes
A) J-level: spec is 100% tested at +25°C.
B) The short circuit current can exceed the maximum safe
output current.
1) Vs = VCC - VEE
supply voltage (VCC - VEE)
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
Reliability Information
Transistor Count
http://www.national.com
147
2
+14V
140mA
VEE to VCC
+150°C
-65°C to +150°C
+300°C
±5V Characteristics (A
v
= +2, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC), RL = 100Ω, VCC = ±5V, unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC5623IN
TYP
+25°C
GUARANTEED MIN/MAX
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.5Vpp
Vo = 4.0Vpp
-0.1dB bandwidth
Vo = 1.0Vpp
gain peaking
<200MHz, Vo = 1.0Vpp
gain rolloff
<30MHz, Vo = 1.0Vpp
linear phase deviation
<30MHz, Vo = 1.0Vpp
differential gain
NTSC, RL=150Ω
differential phase
NTSC, RL=150Ω
148
72
15
0
0.1
0.08
0.06
0.06
110
55
12
0.5
0.3
1.6
0.12
0.1
105
52
9
0.9
0.5
2.0
–
–
85
52
9
1.3
0.5
2.0
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
4.4
18
19
370
5.8
25
21
280
6.2
40
23
260
6.8
60
24
240
ns
ns
%
V/µs
2V step
2V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
crosstalk, all hostile (input referred) 10MHz, 1Vpp
-78
-86
-65
-94
-96
-73
–
–
-60
–
–
-60
–
–
-58
–
–
-58
–
–
-58
–
–
-58
dBc
dBc
dBc
dBc
dBc
dBc
4.9
6.6
11.1
-51
-49
5.9
8.5
14.7
–
–
6.4
9.3
15.8
–
–
6.4
9.3
15.8
–
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
dB
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current (per channel)
1
10
8
40
9
30
48
47
3.2
6
–
18
–
24
–
45
43
3.8
7
–
23
–
28
–
43
41
4.0
8
–
25
–
28
–
43
41
4.0
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
mA
0.88
1.45
±4.2
±3.8
±4.0
130
60
0.52
2.15
±4.1
±3.6
±3.8
100
90
0.47
2.15
±4.1
±3.6
±3.8
80
90
0.47
2.15
±4.0
±3.5
±3.7
50
120
MΩ
pF
V
V
V
mA
mΩ
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common-mode input range
output voltage range
RL = 100Ω
output voltage range
RL = ∞
output current
output resistance, closed loop
DC
Notes
Model
CLC5623IN
CLC5623IM
CLC5623IMX
Package Thermal Resistance
Package
B
Ordering Information
B) The short circuit current can exceed the maximum safe
output current.
Plastic (IN)
Surface Mount (IM)
NOTES
θJC
θJA
60°C/W
55°C/W
110°C/W
125°C/W
3
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Description
8-pin PDIP
8-pin SOIC
8-pin SOIC tape and reel
http://www.national.com
+5V Typ. Perform. (A
v
= +2, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC), RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
-90
-180
Av = +5
Rf = 402Ω
-270
Av = +10
Rf = 200Ω
-360
-450
1M
10M
Gain
Av = -2
Rf = 499Ω
Phase
135
45
Av = -10
Rf = 250Ω
Gain
Phase
0
-90
RL = 25Ω
-180
-270
-360
0
-450
-45
10M
1M
100M
10M
100M
Frequency (Hz)
Gain Flatness & Linear Phase
Open Loop Transimpedance Gain, Z(s)
0
140
-0.2
120
225
Magnitude (0.05dB/div)
Vo = 2Vpp
10M
10
135
80
90
-0.8
60
45
20
-1.0
40
1k
30
Noise Voltage (nV/√Hz)
CMRR
40
30
20
10
12.5
3.25
Inverting Current 11pA/√Hz
10.5
3.2
3.15
3.1
Voltage 3.08nV/√Hz
3.05
Non-Inverting Current 7.5pA/√Hz
3.0
0
1M
10M
6.5
10k
100M
8.5
100k
1M
-50
Noise Current (pA/√Hz)
PSRR
2nd & 3rd Harmonic Distortion, RL = 25Ω
2nd
RL = 100Ω
-60
0
100M
3rd
RL = 100Ω
-70
-80
2nd
RL = 1kΩ
-90
3rd
RL = 1kΩ
-100
10M
1M
10M
Frequency (Hz)
2nd & 3rd Harmonic Distortion, RL = 1kΩ
2nd & 3rd Harmonic Distortion, RL = 100Ω
-40
10M
Vo = 2Vpp
Frequency (Hz)
Frequency (Hz)
1M
2nd & 3rd Harmonic Distortion
3.3
60
100k
Frequency (Hz)
Equivalent Input Noise
100k
10k
Frequency (MHz)
Frequency (Hz)
PSRR & CMRR
10k
100
-0.6
0
100M
180
Gain
Distortion (dBc)
1M
-0.4
Phase
-50
-50
2nd, 10MHz
-55
-60
-65
2nd, 1MHz
-70
-60
-60
2nd, 10MHz
3rd, 10MHz
Distortion (dBc)
3rd, 10MHz
-50
Distortion (dBc)
Distortion (dBc)
-45
-70
2nd, 1MHz
-80
-90
3rd, 1MHz
-80
0
0.5
1.5
2
2.5
0
Output Amplitude (Vpp)
0.5
1
1.5
2
Output Impedance vs. Frequency
1
1.5
2
2.5
IBI, IBN, VIO vs. Temperature
0
Offset Voltage VIO (mV)
Output Impedance (Ω)
0.5
40
30
20
10
4
3
IBI
IBN
-0.5
2
VIO
1
-1
0
1k
10k
100k
1M
Frequency (Hz)
4
10M
100M
0
-60
-20
20
60
Temperature (°C)
100
140
IBI, IBN (µA)
Output Voltage (0.5V/div)
3rd, 1MHz
Output Amplitude (Vpp)
Large Signal
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2nd, 1MHz
0
2.5
50
Time (10ns/div)
-90
Output Amplitude (Vpp)
Large & Small Signal Pulse Response
Small Signal
-80
-110
-100
1
2nd, 10MHz
-100
-75
3rd, 1MHz
3rd, 10MHz
-70
Phase (deg)
Vo = 1Vpp
Phase
Phase (deg)
Magnitude (1dB/div)
Vo = 0.1Vpp
Magnitude (dBΩ)
Gain
PDIP Package
1k
RL = 100Ω
RL = 1kΩ
Frequency (Hz)
Frequency Response vs. Vo
PSRR & CMRR (dB)
90
Av = -5
Rf = 402Ω
Frequency (Hz)
50
Vo = 0.5Vpp
PDIP Package
180
1M
100M
Av = -1
Rf = 549Ω
Magnitude (1dB/div)
0
Frequency Response vs. RL
Phase (deg)
Av = +2
Rf = 750Ω
Vo = 0.5Vpp
PDIP Package
Phase (deg)
Gain
Phase
Normalized Magnitude (1dB/div)
Inverting Frequency Response
Av = +1
Rf = 1kΩ
Vo = 0.5Vpp
PDIP Package
Phase (deg)
Normalized Magnitude (1dB/div)
Frequency Response
±5V Typical Performance (A
v
= +2, Rf = 1kΩ (PDIP), RL = 100Ω, VCC = ±5V, unless specified)
-45
Av = +10
Rf = 200Ω
-90
-135
Av = +5
Rf = 402Ω
-180
-225
10M
100M
Av = -10
Rf = 250Ω
180
135
Av = -2
Rf = 449Ω
90
1M
RL = 100Ω
Phase
0
-90
10M
-360
-450
1M
100M
10M
Frequency (Hz)
Magnitude (0.02dB/div)
Vo = 2Vpp
Small Signal Pulse Response
Vo = 1.5Vpp
PDIP package
Av = +1
-0.2
Gain
-0.4
-0.6
Phase (deg)
Vo = 5Vpp
100M
0
Phase
Vo = 1Vpp
-270
0
Gain Flatness & Linear Phase
Vo = 0.1Vpp
-180
RL = 25Ω
Frequency (Hz)
Frequency Response vs. Vo
Magnitude (1dB/div)
Gain
-45
Frequency (Hz)
PDIP Package
45
Av = -10
Rf = 250Ω
RL = 1kΩ
Amplitude (0.2V/div)
1M
Gain
Phase
Vo = 1.5Vpp
PDIP Package
Magnitude (1dB/div)
0
Frequency Response vs. RL
Av = -5
Rf = 402Ω
Phase (deg)
Av = +1
Rf = 750Ω
Vo = 1.5Vpp
PDIP Package
Phase (deg)
Av = +2
Rf = 750Ω
Gain
Phase
Normalized Magnitude (1dB/div)
Inverting Frequency Response
Vo = 1.5Vpp
PDIP Package
Phase (deg)
Normalized Magnitude (1dB/div)
Frequency Response
-0.8
Av = -1
-1.0
1M
10M
0
100M
10
5
Frequency (Hz)
15
20
25
Time (10ns/div)
30
Frequency (MHz)
Differential Gain & Phase
Large Signal Pulse Response
2nd & 3rd Harmonic Distortion
-0.01
-0.02
-60
f = 3.58MHz
Gain Pos Sync
Amplitude (0.5V/div)
Gain (%)
-0.06
Phase Neg Sync
-0.08
-0.05
-0.1
Gain Neg Sync
-0.06
-0.12
Phase (deg)
-0.03
-0.04
Phase Pos Sync
Av = -2
-0.07
-0.14
-0.08
-0.16
Time (20ns/div)
1
Vo = 2Vpp
-0.04
Distortion (dBc)
-0.02
Av = +2
2
3
-70
-80
3rd
RL = 1kΩ
-90
2nd
RL = 1kΩ
-100
4
1
10
Number of 150 Ω Loads
-50
2nd, 10MHz
2nd, 10MHz
-60
-60
3rd, 10MHz
-80
2nd, 1MHz
-90
-100
3rd, 10MHz
-70
-80
2nd, 1MHz
-90
3rd, 1MHz
-100
3rd, 1MHz
Distortion (dBc)
-70
Distortion (dBc)
Distortion (dBc)
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-50
-60
0
1
2
3
4
0.5
1
1.5
2
2.5
0.15
0.1
0
-0.05
-0.1
Time (ns)
10000
3
4
5
IBI, IBN, VOS vs. Temperature
1.6
0.1
0.05
0
-0.05
-0.1
7
IBI
1.4
5
1.2
3
1.0
1
VOS
0.8
-1
0.6
-3
IBN
-0.2
-0.2
2
Output Amplitude (Vpp)
-0.15
-0.15
1
IBI, IBN (µA)
0.05
1000
3rd, 1MHz
0
Offset Voltage VOS(mV)
0.15
Vo (% Output Step)
0.2
100
-90
Long Term Settling Time
Short Term Settling Time
0.2
10
2nd, 1MHz
2nd, 10MHz
-80
Output Amplitude (Vpp)
Output Amplitude (Vpp)
1
-70
-110
0
5
3rd, 10MHz
-100
-110
-110
Vo (% Output Step)
Frequency (MHz)
2nd & 3rd Harmonic Distortion, RL = 100Ω
2nd & 3rd Harmonic Distortion, RL = 25Ω
-50
3rd
RL = 100Ω
2nd
RL = 100Ω
0.4
1µ
10µ
100µ
Time (s)
5
1m
10m
-5
-60
-20
20
60
100
Temperature (°C)
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±5V Typical Channel Matching Performance (A
Channel Matching
v
= +2, Rf = 1kΩ (PDIP), RL = 100Ω, VCC = ±5V, unless specified)
Pulse Crosstalk
Input Referred Crosstalk
-20
PDIP Package
Vo = 1Vpp
Active Channel
Amplitude (0.2V/div)
Channel 1
Magnitude (dB)
Magnitude (0.5dB/div)
Channel 2
Active Output
Channel
-35
-45
-55
-65
Inactive Output
Channel 2
Inactive Output
Channel 3
Inactive Channel
Amplitude (20mV/div)
Channel 3
Active Output
Channel 1
-75
1M
10M
100M
10M
1M
Frequency (Hz)
Time (20ns/div)
100M
Frequency (Hz)
CLC5623 OPERATION
The CLC5623 is a current feedback amplifier built in an
advanced complementary bipolar process. The CLC5623
operates from a single 5V supply or dual ±5V supplies.
Operating from a single supply, the CLC5623 has the
following features:
■
■
■
Vo
=
Vin
Av
Rf
1+
Z(jω )
Equation 1
where:
■
Provides 100mA of output current while
consuming 15mW of power
Offers low -85/-96dB 2nd and 3rd harmonic
distortion
Provides BW > 100MHz and 1MHz distortion
< -70dBc at Vo = 2Vpp
■
■
■
The CLC5623 performance is further enhanced in ±5V
supply applications as indicated in the ±5V Electrical
Characteristics table and ±5V Typical Performance plots.
Av is the closed loop DC voltage gain
Rf is the feedback resistor
Z(jω) is the CLC5623’s open loop
transimpedance gain
Z( jω )
is the loop gain
Rf
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rf and Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
Current Feedback Amplifiers
Some of the key features of current feedback technology
are:
■ Independence of AC bandwidth and voltage gain
■ Inherently stable at unity gain
■ Adjustable frequency response with feedback resistor
■ High slew rate
■ Fast settling
■
■
■
■
■
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
Refer to the Feedback Resistor Selection section for
more details on selecting a feedback resistor value.
CLC5623 DESIGN INFORMATION
Single Supply Operation (VCC = +5V, VEE = GND)
The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the
output voltages are specified.
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5623 is typically +0.8V to
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6
VCC
DC Coupled Single Supply Operation
Figures 1 and 2 show the recommended non-inverting
and inverting configurations for input signals that remain
above 0.8V DC.
6.8µF
+
VCC
2
VCC
Note: Rt, RL and Rg are tied
to Vcm for minimum power
consumption and maximum
output swing.
Vin
6.8µF
5
1/3
CLC5623
6
Rt
Vcm
-
11
RL
Rf
low frequency cutoff =
R
Vo
= A v = 1+ f
Vin
Rg
Vin
Vcm
6
-
11
7
Vo
Rf
1
2πR gC c
Dual Supply Operation
The CLC5623 operates on dual supplies as well as
single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6.
VCC
6.8µF
VCC
+
6.8µF
+
+
4
0.1µF
1/3
CLC5623
-
Rg
11
Vo
7
Vin
RL
Rf
5
Rt
6
+
Rt
R
Vo
= Av = − f
Vin
Rg
4
-
7
Vo
Rf
11
0.1µF
Rg
Select Rt to yield
desired Rin = Rt || Rg
0.1µF
1/3
CLC5623
Vcm
Vcm
1/3
CLC5623
Figure 4: AC Coupled Inverting Configuration
Figure 1: Non-Inverting Configuration
Rb
6
0.1µF
4
 R 
Vo = Vin  − f  + 2.5
 Rg 
Vo
7
Vcm
Vcm
5
Rg
+
R
Rg
Note: Rb, provides DC bias
for non-inverting input.
Rb, RL and Rt are tied
to Vcm for minimum power
consumption and maximum
output swing.
5
0.1µF
4
+
Cc
Vin
+
R
R
Vo
= A v = 1+ f
Vin
Rg
+
6.8µF
Figure 2: Inverting Configuration
VEE
Figure 5: Dual Supply Non-Inverting Configuration
AC Coupled Single Supply Operation
Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V
DC. The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC ÷ 2
= 2.5V (For VCC = +5V).
VCC
6.8µF
+
Rb
5
VCC
6
6.8µF
+
Vin
R
Cc
5
VCC
2

R 
Vo = Vin 1 + f  + 2.5
R

g
low frequency cutoff =
R
6
+
4
11
7
-
11
0.1µF
7
Rf
0.1µF
Vo
Vo
Note: Rb provides DC bias
for the non-inverting input.
Select Rt to yield desired
Rin = Rt || Rg.
+
R
Vo
= Av = − f
Vin
Rg
Rf
Rg
C
1
R
, where: Rin =
2πRinC c
2
Rg
4
1/3
CLC5623
Rt
0.1µF
1/3
CLC5623
-
Vin
+
6.8µF
VEE
Figure 6: Dual Supply Inverting Configuration
R >> R source
Figure 3: AC Coupled Non-Inverting Configuration
7
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■
■
Figure 8 illustrates the channel matching performance of
the surface mount version of the CLC5623. Once again,
the surface mount package performs better. If optimum
performance is desired, use the surface mount version of
the CLC5623.
Magnitude (0.5dB/div)
Feedback Resistor Selection
The feedback resistor, Rf, affects the loop gain and
frequency response of a current feedback amplifier.
Optimum performance of the CLC5623, at a gain of
+2V/V, is achieved with Rf equal to 750Ω for the SOIC
package and 1kΩ for the PDIP package. The frequency
response plots in the Typical Performance sections
illustrate the recommended Rf for several gains. These
recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be
adjusted to optimize the frequency response.
Decrease Rf to peak frequency response and
extend bandwidth
Increase Rf to roll off frequency response and
compress bandwidth
Channel 3
Channel 2
Channel 1
Av = 2, Rf =750Ω
Vo =
VCC = ±5V
SOIC Package
1M
As a rule of thumb, if the recommended Rf is doubled,
then the bandwidth will be cut in half.
100M
Figure 8: Channel Matching Perfomance
Unity Gain Operation
The recommended Rf for unity gain (+1V/V) operation
is 750Ω (for the PDIP package). Rg is left open. Parasitic
capacitance at the inverting node may require a slight
increase in Rf to maintain a flat frequency response.
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC5623 will
improve stability and settling performance. The
Frequency Response vs. CL plot, shown below in
Figure 9, gives the recommended series resistance value
for optimum flatness at various capacitive loads.
Load Termination
The CLC5623 can source and sink near equal amounts
of current. For optimum performance, the load should be
tied to Vcm.
Additional parasitics and limitations on decoupling in the
CLC5623IN combine to provide a lower level of performance
than the CLC5623IM. The specifications in the Electrical
Characteristics tables are based on the performance of
the DIP package (CLC5623IN). For optimum performance, use the CLC5623IM (SOIC package). Proper
supply decoupling and board layout are critical factors for
obtaining optimum performance of the CLC5623IN.
Board layout is less critical for the SOIC package. Use
the evaluation boards as a guide to proper layout.
Magnitude (1dB/div)
Vo = 1Vpp
CL = 10pF
Rs = 68.1Ω
CL = 100pF
Rs = 17.4Ω
CL = 1000pF
Rs = 6.7Ω
+
Rs
-
1k
CL
1k
1k
1M
10M
100M
Frequency (Hz)
Figure 7 illustrates the frequency response versus output
amplitude for the CLC5623IM. Compare the Frequency
Response vs. Vo plot, in the ±5V Typical Performance
section, with Figure 7. Notice that gain flatness and bandwidth improve when the SOIC package is used.
Magnitude (1dB/div)
10M
Frequency (Hz)
Figure 9: Frequency Response vs. CL
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 10 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
Vo = 0.1Vpp
Vo = 1Vpp
Non-inverting gain applications:
Vo = 1.5Vpp
Av = 2, Rf =750Ω
Vo =
VCC = ±5V
SOIC Package
1M
Vo = 2Vpp
■
Vo = 2.5Vpp
■
■
10M
100M
Frequency (Hz)
Figure 7: Frequency Response vs. Vo
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8
Connect Rg directly to ground.
Make R1, R2, R6, and R7 equal to Zo.
Use R3 to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Z0
R1
R3
V1 +-
R2
Z0
R4
1/3
CLC5623
-
Z0
R6
Vo
R7
Rf
Rg
V2 +-
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC5623 (CLC730075-DIP,
CLC730074-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
C6
+
R5
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
Figure 10: Transmission Line Matching
Inverting gain applications:
■
■
■
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to Zo.
Make R5 II Rg = Zo.
■
■
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6 to match the output transmission line over a
greater frequency range. C6 compensates for the increase
of the amplifier’s output impedance with frequency.
■
■
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5623:
■
■
1. Calculate the quiescent (no-load) power:
Pamp = ICC (VCC - VEE)
2. Calculate the RMS power at the output stage:
Po = (VCC - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
Pt = Pamp + Po
Evaluation Board Information
A data sheet is available for the CLC730075/ CLC730074
evaluation boards. The evaluation board data sheet
provides:
■
■
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 11. The power derating curve for any CLC5623
package can be derived by utilizing the following
equation:
(175° − Tamb )
θ JA
where
■
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
■
1.0
■
Power (W)
Evaluation board schematics
Evaluation board layouts
General information about the boards
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient,
for a given package (°C/W
IN
0.8
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75 inches
of the power pins.
Place the 0.1µF capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
IM
■
0.6
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise
performance
Support room temperature simulations
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
0.4
0.2
0
-40 -20
0
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
Figure 11: Power Derating Curves
9
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Application Circuits
Gain = K = 1 +
Single Supply Cable Driver
The typical application shown below shows one of the
CLC5623 amplifiers driving 10m of 75Ω coaxial cable.
The CLC5623 is set for a gain of +2V/V to compensate
for the divide-by-two voltage drop at Vo.
Corner frequency = ω c =
R 2C 2
+
R1C1
6.8µF
+
0.1µF
5kΩ
6
+
4
0.1µF
1/3
CLC5623
-
11
R1C2
R1C1
+ (1− K)
R 2C1
R 2C 2
For R1 = R 2 = R and C1 = C2 = C
5kΩ
5
1
R1R 2C1C2
1
Q=
+5V
Vin
Rf
Rg
75Ω
7
1kΩ
10m of 75Ω
Coaxial Cable
0.1µF
ωc =
Vo
75Ω
Q=
1kΩ
0.1µF
1
RC
1
(3 − K)
Figure 15: Design Equations
This example illustrates a lowpass filter with Q = 0.707
and corner frequency fc = 10MHz. A Q of 0.707 was
chosen to achieve a maximally flat, Butterworth
response. Figure 16 indicates the filter response.
Figure 12: Single Supply Cable Driver
Magnitude (dB)
100mV/div
Vin = 10MHz, 0.5Vpp
20ns/div
3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
Figure 13: Response After 10m of Cable
1M
Single Supply Lowpass Filter
Figures 14 and 15 illustrate a lowpass filter and design
equations. The circuit operates from a single supply of
+5V. The voltage divider biases the non-inverting input to
2.5V. And the input is AC coupled to prevent the need for
level shifting the input signal at the source. Use the
design equations to determine R1, R2, C1, and C2 based
on the desired Q and corner frequency.
Differential Line Driver With Load
Impedance Conversion
The circuit shown in the Typical Application schematic
on the front page and in Figure 17, operates as a
differential line driver. The transformer converts the load
impedance to a value that best matches the CLC5623’s
output capabilities. The single-ended input signal is
converted to a differential signal by the CLC5623. The
line’s characteristic impedance is matched at both the
input and the output. The schematic shows Unshielded
Twisted Pair for the transmission line; other types of lines
can also be driven.
0.1µF
5kΩ
0.1µF
R1
R2
5
158Ω 158Ω
5kΩ
C2
100pF
6
+
4
1/3
CLC5623
-
11
C1
7
0.1µF
Rf
Vo
100Ω
1kΩ
1.698kΩ Rg
0.1µF
Figure 14: Lowpass Filter Topology
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100M
Figure 16: Lowpass Response
+5V
Vin
10M
Frequency (Hz)
10
Bandpass Filter
Figure 18 illustrates a low-sensitivity bandpass filter and
design equations. This topology utilizes the CLC5623’s
closely matched amplifiers to obtain low op-amp
sensitivity at high frequencies. The third CLC5623 is
used as a buffer to obtain low output impedance. The
overall circuit gain is unity. For additional gain, the third
CLC5623 can be configured as a non-inverting amplifier.
Rf2
Rg2
Vd/2
Vin
+
1/3
CLC5623
Rt1
1/3
CLC5623
Rf1
Rg1
Rm/2
-Vd/2
Io
1:n
Zo
Req
+
RL
UTP
+
Vo
-
Rm/2
Rt2
Figure 17: Differential Line Driver wtih
Load Impedance Conversion
To design the filter, choose C and then determine values for
R and R1 based on the desired resonant frequency (fr)
and Q factor.
Set up the CLC5623 as a difference amplifier:
C

Vd
R 
R
= 2 ⋅ 1 + f1  = 2 ⋅ f2
Vin
R g2
 R g1 
+
1/3
CLC5623
R
R
Make the best use of the CLC5623’s output drive
capability as follows:
Rm + Req =
-
R
2 ⋅ Vmax
Imax
1/3
CLC5623
+
R1
Vin
Vo
1/3
CLC5623
-
1
R=
2πfr C
Match the line’s characteristic impedance:
Rf
R1 = QR
Figure 18: Bandpass Filter Topology
RL = Z o
Instrumentation Amplifier
An instrumentation circuit is shown on the front page and
reproduced in Figure 19. The DC CMRR can be fine
tuned by adjusting R1.
Rm = Req
RL
Req
V1
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5623 also affects the match. With
an ideal transformer we obtain:
+
1/3
CLC5623
750Ω
750Ω
750Ω
Vout = 3(V2 - V1)
-
750Ω
750Ω
n ⋅ Z o(5623) ( jω )
,dB
Zo
2
Return Loss = −20 ⋅ log10
+
C
where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
n=
R
750Ω
1/3
CLC5623
+
V2
where Zo(5623)(jω) is the output impedance of the
CLC5623 and |Zo(5623)(jω)| << Rm.
1/3
CLC5623
+
R1
750Ω
Figure 19: Instrumentation Amplifier
The load voltage and current will fall in the ranges:
Vo
≤ n ⋅ Vmax
Io ≤
Imax
n
The CLC5623’s high output drive current and low
distortion make it a good choice for this application.
11
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CLC5623
Triple, High Output, Video Amplifier
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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