OKI ML670100 Okis high-performance cmos 32-bit single chip microcontroller Datasheet

Semiconductor
ML670100
Version 2
Aug., 1999
OKI’s High-Performance CMOS 32-Bit Single Chip Microcontroller
GENERAL DESCRIPTION
The ML670100 is a high-performance 32-bit microcontroller combining a RISC based, 32-bit CPU core the ARM7TDMITM - with memory and such peripheral circuits as timers, serial ports, and analog-todigital converter. This combination of 32-bit data processing, built-in memory, and on-chip peripherals
make it ideal for controlling equipment requiring both high speed and high functionality. An external
memory controller supports direct connection to memory and peripheral devices for adding even more
functionality.
FEATURES
Operating Voltage
2.7 to 3.6V
Operating Frequency 25MHz maximum(3.0 to 3.6V)
On-chip memory
-ROM: 128 kilobytes
-RAM: 4 kilobytes
I/O Function
I/O ports: 8 bits x 9, I/O directions are specified at the bit level
Timer
-Flexible timer (16-bit multi-function timer with six channels)
Choice of operating modes: auto-reload timer, compare output, PWM
and capture
-Time base counter with WDT function
Serial Port
-One asynchronous serial port (UART) with baud rate generator
-Two clock synchronous serial port
A-to-D Converter
-8-bit resolution A-to-D converter with eight analog input ports
Interrupt
-Support for 28 interrupt sources: 9 external and 19 internal
Controller
-Choice of eight priority levels for each source
External Memory
-Direct connection to ROM, SRAM, DRAM and peripheral devices
Controller
-Support for four banks: two for ROM, SRAM and I/O devices plus two for
DRAM
-User-configurable bus width (8/16 bits) and wait control and other
parameters for accessing memory and external devices
Clock Generator
-Built-in crystal oscillation circuit and PLL
-Choice of divider ratio (1/1, 1/2, 1/4) for adjusting operating clock frequency
to match the load of processing
Package
144-pin LQFP ( LQFP144-P-2020-0.50-K)
ARM POWERED logo is the registered trademark of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
The Information contained herein can change without notice owing to product and/or technical improvement.
The signal name of negative logic is being changed to nXXX from XXX in this data sheet.
1 / 27
Semiconductor
ML670100
BLOCK DIAGRAM
TDI*
TDO*
nTRST*
TMS*
TCK*
DBGEN*
DBGRQ*
DBGACK*
4 kilobytes
of RAM
ARM7TDMI
Core address bus
Core data bus (32b)
TMCLK[1:0]*
ASI_TXD*
ASI_RXD*
CSI1_TXD*
CSI1_RXD*
CSI1_SCLK*
CSI0_TXD*
CSI0_RXD*
CSI0_SCLK*
External Memory
Controller (XMC)
Internal
Bus
Controller
Time Base
Generator
(TBG)
Interrupt
Controller
(INT)
Flexible
Timer
Analog-to-digital
VREF
Converter
AI[7:0]
Asynchronous
Serial Interface
(ASI)
Clock
Synchronous
Interface
(CSI0 and CSI1)
Clock
Control
Asterisks indicate signals that aresecondary functions of I/O ports.
2 / 27
PIO0[7:0]
PIO1[7:0]
PIO2[7:0]
PIO3[7:0]
PIO4[7:0]
PIO5[7:0]
PIO6[7:0]
PIO7[7:0]
PIO8[7:0]
I/O Ports
Brackets indicate bit ranges.
nEFIQ
nEIR[7:0]*
(ADC)
Peripheral data bus 16b)
TMIN/TMOUT[5:0]*
128 kilobytes
of ROM
Peripheral address bus
nRST
nEA
DBSEL
TEST
VDD
GND
AVDD
AGND
XA23-16*
XA15-1
nLB/XA0
XD15-8*
XD7-0
nCS0
nRD
nWRE/nWRL
nXWAIT*
nCS1*
nHB/nWRH*
nRAS1*
nWH/nCASH*
nRAS0*
nCAS/nCASL*
nWL/nWE*
nBREQ*
nBACK*
OSC0
OSC1
CLKOUT
FSEL
PLLEN
VCOM
Semiconductor
ML670100
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PIO3[4]/nEIR[4]
PIO3[3]/nEIR[3]
PIO3[2]/nEIR[2]
PIO3[1]/nEIR[1]
PIO3[0]/nEIR[0]
VDD
GND
PIO2[7]/nXWAIT
PIO2[6]/nCS1
PIO2[5]/nHB/nWRH
PIO2[4]/nRAS1
PIO2[3]/nWH/nCASH
PIO2[2]/nRAS0
PIO2[1]/nCAS/nCASL
PIO2[0]/nWL/nWE
VDD
GND
nWRE/nWRL
nRD
nCS0
PIO1[7]/XD15
PIO1[6]/XD14
PIO1[5]/XD13
PIO1[4]/XD12
PIO1[3]/XD11
PIO1[2]/XD10
PIO1[1]/XD9
PIO1[0]/XD8
VDD
GND
XD7
XD6
XD5
XD4
XD3
XD2
PIN CONFIGURATION (TOP VIEW)
Top View
INDEX
MARK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AI[4]
AI[3]
AI[2]
AI[1]
AI[0]
VREF
AVDD
VDD
TEST
DBSEL
PIO6[0]
PIO6[1]
PIO6[2]
PIO6[3]
PIO6[4]
PIO6[5]]
PIO6[6]]
PIO6[7]
PIO7[0]
PIO7[1]
PIO7[2]
GND
VDD
PIO7[3]
PIO7[4]
PIO7[5]
PIO7[6]/nBREQ
PIO7[7]/nBACK
PIO8[0]/DBGACK
PIO8[1]/DBGRQ
PIO8[2]/DBGEN
PIO8[3]/TCK
PIO8[4]/TMS
PIO8[5]/nTRST
PIO8[6]/TDO
PIO8[7]/TDI
PIO3[5]/nEIR[5]
PIO3[6]/nEIR[6]
PIO3[7]/nEIR[7]
GND
PIO4[0]/TMIN[0]/TMOUT[0]
PIO4[1]/TMIN[1]/TMOUT[1]
PIO4[2]/TMIN[2]/TMOUT[2]
PIO4[3]/TMIN[3]/TMOUT[3]
PIO4[4]/TMIN[4]/TMOUT[4]
PIO4[5]/TMIN[5]/TMOUT[5]
PIO4[6]/TMCLK[0]
PIO4[7]/TMCLK[1]
GND
VDD
PIO5[0]/CSI0_SCLK
PIO5[1]/CSI0_RXD
PIO5[2]/CSI0_TXD
PIO5[3]/CSI1_SCLK
PIO5[4]/CSI1_RXD
PIO5[5]/CSI1_TXD
PIO5[6]/ASI_RXD
PIO5[5]/ASI_TXD
CLKOUT
GND
OSC0
OSC1
VDD
VCOM
FSEL
PLLEN
nRST
GND
AGND
AI[7]
AI[6]
AI[5]
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72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
XD1
XD0
VDD
GND
nEA
nEFIQ
PIO0[7]/XA23
PIO0[6]/XA22
PIO0[5]/XA21
PIO0[4]/XA20
PIO0[3]/XA19
PIO0[2]/XA18
PIO0[1]/XA17
PIO0[0]/XA16
VDD
GND
XA15
XA14
XA13
XA12
XA11
XA10
XA9
XA8
VDD
GND
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0/nLB
VDD
GND
Semiconductor
ML670100
PIN DESCRIPTIONS
Type
Signal
Name
Address XA23 bus
XA16
XA15 XA0
Data bus XD15 XD8
XD7- -XD0
Bus
nCS0
control nCS1
signals
nRD
nWRL
nWRH
nWRE
nLB
nHB
nRAS0
nRAS1
nCASL
nCASH
nWE
nCAS
nWH
nWL
nXWAIT
I/O Direction Description
Output
Output
These are bits 23-16 of the external address bus. They represent
secondary functions for I/O port PIO0[7:0].
These are bits 15 - 0 of the external address bus.
Bidirectional These are bits 15-8 of the external data bus. They represent
secondary functions for I/O port PIO1[7:0].
Bidirectional These are bits 7-0 of the external data bus.
Output
This output is the chip select signal for bank 0.
Output
This output is the chip select signal for bank 1. It represents a
secondary function for I/O port PIO2[6].
Output
This output is the read signal for SRAM banks (0 and 1).
Output
This output is the Write Enable Low signal for SRAM banks (0
and 1).
Output
This output is the Write Enable High signal for SRAM banks (0
and 1). It represents a secondary function for I/O port
PIO2[5].
Output
This output is the Write Enable signal for SRAM banks (0 and
1).
Output
This output is the Low Byte Select signal for SRAM banks (0
and 1).
Output
This output is the High Byte Select signal for SRAM banks (0
and 1). It represents a secondary function for I/O port PIO2[5].
Output
This output is the Row Address Strobe signal for bank 2.
It represents a secondary function for I/O port PIO2[2].
Output
This output is the Row Address Strobe signal for banks 3.
It represents a secondary function for I/O port PIO2[4].
Output
This output is the Column Address Strobe Low signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[1].
Output
This output is the Column Address Strobe High signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[3].
Output
This output is the Write Enable signal for DRAM banks (2 and
3). It represents a secondary function for I/O port PIO2[0].
Output
This output is the Column Address Strobe signal for DRAM
banks (2 and 3). It represents a secondary function for I/O port
PIO2[1].
Output
This output is the Write Enable High signal for DRAM banks
(2 and 3). It represents a secondary function for I/O port
PIO2[3].
Output
This output is the Write Enable Low signal for DRAM banks (2
and 3). It represents a secondary function for I/O port PIO2[0].
Input
This input pin controls insertion of wait cycles. It represents a
secondary function for I/O port PIO2[7].
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Semiconductor
ML670100
PIN DESCRIPTIONS (Cont.)
Type Signal Name I/O Direction
Bus
nBREQ
Input
control
signals nBACK
Output
Description
This input is a bus request signal from an external device.
It represents a secondary function for I/O port PIO7[6].
This output is an acknowledgment signal to a bus request signal
from an external device. It represents a secondary function for
I/O port PIO7[7].
Interru- nEFIQ
Input
This input is an external fast interrupt request (FIQ). When
pts
accepted, the request is processed as an FIQ exception.
nEIR[7:0]
Input
This inputs are external interrupt requests. They represent
secondary functions for I/O port PIO3[7:0].
Timers TMIN[5:0]
Input
These pins function as capture trigger input pins for Flexible
Timer channels 5-0 in capture mode. They represent secondary
functions for I/O port PIO4[5:0].
TMOUT[5:0] Output
These pins function as output pins for Flexible Timer channels
5-0 in compare output or PWM mode. They represent
secondary functions for I/O port PIO4[5:0].
TMCLK[1:0] Input
These pins function as Flexible Timer channels 1 and 0 clock
input pins. They represent secondary functions for I/O port
PIO4[7:6].
Serial ASI_TXD
Output
This output is the transmit data for the Asynchronous Serial
ports
Interface. It represents a secondary function for I/O port
PIO5[7].
ASI_RXD
Input
This input is the receive data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[6].
CSI0_TXD Output
This output is the transmit data for the Clock Synchronous
Serial Interface 0. It represents a secondary function for I/O
port PIO5[2].
CSI0_RXD Input
This input is the receive data for the Clock Synchronous Serial
Interface 0. It represents a secondary function for I/O port
PIO5[1].
CSI0_SCLK Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 0. It represents a secondary
function for I/O port PIO5[0].
CSI1_TXD Output
This output is the transmit data for the Clock Synchronous
Serial Interface 1. It represents a secondary function for I/O
port PIO5[5].
CSI1_RXD Input
This input is the receive data for the Clock Synchronous Serial
Interface 1. It represents a secondary function for I/O port
PIO5[4].
CSI1_SCLK Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 1. It represents a secondary
function for I/O port PIO5[3].
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Semiconductor
ML670100
PIN DESCRIPTIONS (Cont.)
Type
Signal
Name
Analog- VREF
to-digital
converter AI[7:0]
I/O Direction Description
Debugg- TDI
ing
interface TDO
Input
Input
Input
Output
nTRST
Input
TMS
Input
TCK
Input
DBGEN
Input
DBGRQ
Input
DBGACK
Output
I/O ports PIO8[7:0]
Bidirectional
PIO7[7:0]
Bidirectional
PIO6[7:0]
Bidirectional
PIO5[7:0]
Bidirectional
PIO4[7:0]
Bidirectional
PIO3[7:0]
Bidirectional
PIO2[7:0]
Bidirectional
PIO1[7:0]
Bidirectional
PIO0[7:0]
Bidirectional
This input is the reference voltage for the analog-to-digital
converter channels 7-0. Connect it to VDD.
These are analog signal input pins for analog-to-digital
converter channels 7-0.
This input is the serial data input for the debugging scan circuit.
It represents a secondary function for I/O port PIO8[7].
This output is the serial data output for the debugging scan
circuit. It represents a secondary function for I/O port
PIO8[6].
"L" level input to this pin resets the debugging scan circuit.
It represents a secondary function for I/O port PIO8[5].
This input selects the mode for the debugging scan circuit.
It represents a secondary function for I/O port PIO8[4].
This input is the serial clock input for the debugging scan
circuit. It represents a secondary function for I/O port
PIO8[3].
"H" level input to this pin enables the CPU's debugging
function. It represents a secondary function for I/O port
PIO8[2].
This input is a debugging request signal from an external
device. It represents a secondary function for I/O port
PIO8[1].
This output is an acknowledgment signal to a debugging
request signal from an external device. It represents a secondary
function for I/O port PIO8[0].
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
These form an 8-bit I/O port. I/O directions are specified at the
bit level.
6 / 27
Semiconductor
ML670100
PIN DESCRIPTIONS (Cont.)
Type
Clock
control
System
control
Power
Supply
Signal
Name
OSC0
I/O
Direction
Input
OSC1
Output
CLKOUT
FSEL
Output
Input
PLLEN
Input
VCOM
Input
nRST
Input
DBSEL
Input
nEA
Input
TEST
Input
VDD
Input
GND
Input
AVDD
Input
AGND
Input
Description
This pin is for connecting a crystal oscillator. If an external
clock is used, supply it to this pin.
This pin is for connecting a crystal oscillator. If an external
clock is used, leave this pin open.
This output is the internal system clock signal.
Connect this pin to VDD or ground to indicate the frequency
range for the basic clock.
Connect this pin to VDD to enable the built-in phase-looked
loop. If the PLL is not used because an external clock with a
guaranteed duty is available, connect this pin to ground.
This input controls the oscillation frequency of the PLL's
voltage-controlled oscillator. Connect it to ground.
"L" level input to this pin produces an external system reset for
this LSI. "H" level input then causes execution to resume from
address 0x000000.
During a system reset of this LSI, this input specifies the width
of the external data bus for bank 0. Connect this pin to VDD for
a data bus width of 16bits and to ground for 8bits.
During a system reset of this LSI, this input controls the use of
the internal ROM. Connect this pin to VDD to enable the ROM
and to ground to disable it.
During a system reset of this LSI, this input controls the initial
pin functions for the I/O port 8 pins(PIO8[7:0]). Connect this
pin to VDD to initialize the port for its secondary function, the
debugging interface, and to ground for I/O.
These pins are this LSI's power supply pins. Connect them all to
VDD.
These pins are this LSI's ground pins. Connect them all to
ground.
This pin is the analog-to-digital converter's power supply.
Connect it to VDD.
This pin is the analog-to-digital converter's ground pin.
Connect it to ground.
7 / 27
Semiconductor
ML670100
OUTLINE of PERIPHERAL FUNCTIONS
I/O Ports
The I/O ports consist of nine 8-bit ports: PIOn(n=0 - 8). I/O directions are specified at the bit level. When
configured for input, the pins use high-impedance input.
Flexible Timer
The flexible timer consists of six 16-bit timer channels. Each channel offers independent choice of four
operating modes and of eight count clocks.
-Timer operating modes
- Auto-reload timer
- Compare output
- Pulse width modulation (PWM)
- Capture input
-Timer synchronization
- Timer channels can be started and stopped in union.
-External clocks
- Timer channels 0 and 1 accept external clock signals.
Time Base Generator
The time base generator consists of the time base counter, a frequency divider which derives the time base
signals for the on-chip peripherals from the system clock signals, and watchdog timer, which counts time
base clock cycles and produces a system reset signal when its internal counter overflows.
Asynchronous Serial Interface
The asynchronous serial interface is a serial port that frames each character of information with start and
stop elements. Parameters control transfer speed (using a dedicated baud rate generator), character length,
number of stop bits and use of parity.
-Built-in baud rate generator
-Character length: 7 or 8 bits
-Stop bits: 1 or 2
-Parity: none, odd, or even
-Error detection for receiving: parity, framing and overrun errors
-Full duplex operation
Clock Synchronous Serial Interface
The clock synchronous serial interface are two channels of serial ports that transmit 8-bit data
synchronized with internal or external clock signals.
8 / 27
Semiconductor
ML670100
Analog-to-Digital Converter
The analog-to-digital converter is an 8-bit successive approximation analog-to-digital converter with
eight input channels and four result registers. It offers two operating mode: scan mode, which
sequentially converts the inputs from the selected set of four input channels, and select mode, which
converts the input from a single input channel.
-Resolution: 8 bits
-Eight analog input channels
-Four result registers for holding conversion results
-Operating modes
- Scan modes: Sequential conversion of the analog inputs from the upper or lower set of four
input channels
- Select mode: Conversion of the analog inputs from a single input channel
Interrupt Controller
The interrupt controller manages interrupt requests from 9 external sources and 19 internal ones and
passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. It
supports eight interrupt levels for each source for use in priority control.
-The interrupt controller supports 9 external interrupt sources connected to nEFIQ and nEIR[7:0] pins
and 19 internal interrupt sources, including the serial ports and the flexible timer channels.
-The interrupt controller simplifies interrupt priority control with a choice of eight interrupt levels for
each source.
-The interrupt controller assigns a unique interrupt number to each source to permit rapid branching
to the appropriate routine.
External Memory Controller
The external memory controller generates control signals for accessing external memory (ROM, SRAM,
DRAM, etc.), and other devices with address in the external memory space.
-Support for direct connection of ROM, SRAM and I/O devices
- Strobe signal outputs for a variety of memory and I/O devices
-Support for direct connection of DRAM
- Multiplexed row and column addresses
- Random access and high-speed paged modes
- Programmable wait cycle insertion
-Memory space divided into four banks
- Two banks for ROM, SRAM and I/O devices
- Two banks for DRAM
- Address space of 16 megabytes for each bank
- Separate data bus width (8 or 16 bits), wait cycle, and off time setting for each bank
-Single-stage store buffer permitting internal access during a wait cycle to external memory or device
-Arbitration of external bus requests from external devices
9 / 27
Semiconductor
ML670100
Clock Controller
The clock controller controls the oscillator circuit based on a crystal oscillator and a built-in phase-locked
loop which together generate and control the system clock signal. It offers a choice of divider ratio (1/1,
1/2 and 1/4) for adjusting operating clock frequency to match the load of processing. It also controls the
transitions to and from a stand-by mode, HALT mode.
10 / 27
Semiconductor
ML670100
CONFIGURATIONS of PINS and I/O PORTS
Input Pins (nRST, nEA, DBSEL, TEST, nEFIQ, FSEL, PLLEN, VCOM)
VDD
Input pins
(high impedance)
GND
Output Pin (CLKOUT)
VDD
Output pin
(CMOS output)
GND
Tri-state output pins (XA23 - XA1, nLB/XA0, nCS0, nRD, nWRE/nWRL)
Output pins
(CMOS output when enabled)
Output enable
signal
Bidirectional pins (XD7 - XD0)
Bidirectional pins
(CMOS output when enabled)
Output enable
signal
Read signal
11 / 27
Semiconductor
ML670100
I/O port A (I/O ports without second functions)
PIO6[7:0], PIO7[5:0]
PMm [n]
Peripheral bus
POm [n]
PIOm [n]
Read PIm [n]
I/O port B (I/O ports with second functions of input)
PIO2[7], PIO3[7:0] , PIO4[7:6] , PIO5[6] , PIO5[4], PIO5[1] , PIO7[6] , PIO8[7] , PIO8[5:1]
PMm [n]
POm [n]
Secondary function
input signal
PFSm [n]
Peripheral bus
PIOm [n]
Read PIm [n]
12 / 27
Semiconductor
ML670100
I/O port C (I/O ports with second functions of output)
PIO5[7], PIO5[5], PIO5[2], PIO7[7], PIO8[6], PIO8[0]
PMm [n]
POm [n]
Secondary function
output signal
PFSm [n]
Peripheral bus
PIOm [n]
Read PIm [n]
13 / 27
Semiconductor
ML670100
I/O port D (I/O ports with second functions of tri-state output)
PIO0[7:0], PIO2[6:0]
PMm [n]
Secondary function output
enable signal
POm [n]
Secondary function
output signal
PFSm [n]
Peripheral bus
PIOm [n]
Read PIm [n]
14 / 27
Semiconductor
ML670100
I/O port E (I/O ports with second functions of input and output)
PIO1[7:0], PIO4[5:0], PIO5[3], PIO5[0]
PMm [n]
Secondary function output
enable signal
POm [n]
Secondary function
output signal
Secondary function
input signal
PFSm [n]
Peripheral bus
PIOm [n]
Read PIm [n]
15 / 27
Semiconductor
ML670100
ELECTRICAL CHARACTERISTICS
Absolute Maximum ratings
Item
Power supply
Input voltage
Analog input voltage
Output current
Power dissipation
Storage temperature
Symbol
VDD
VIN
Condition
VDD=AVDD=VREF
GND=AGND=0V
VAI
IO
PD
TSTG
Ta=25V
-
Recommended Operating Conditions
(Condition: GND=AGND=0V)
Item
Symbol
Power supply
Analog power supply
Analog reference
voltage
Analog input voltage
Operating Frequency 1
Operating Frequency 2
Ambient temperature
Condition
VDD=AVDD
VDD
AVDD
VREF
VAI
fC1
fC2
Ta
VDD =3.0 to 3.6V, 1
VDD =2.7 to 3.6V, 2
-
Rated Value
-0.3 to 4.6
-0.3 to VDD +0.3
-0.3 to AVDD +0.3
12
850
-55 to +150
Min.
2.7
2.7
AVDD-0.3
Typ.
3.3
3.3
-
Max.
3.6
3.6
AVDD
AGND
4
4
-40
25
VREF
25
20
+85
Unit
V
V
mA
mW
°C
Unit
V
MHz
°C
1
Basic clock frequency
from the oscillator
circuit or an external
clock signal
4 - 6.25MHz
8 - 12.5MHz
4 - 25MHz
(External clock only)
PLLEN Input
FSEL Input
Operating Frequency 1
fC1
“H” level
(Connect to VDD)
“L” level
(Connect to GND)
“H” level (Connect to VDD)
“L” level (Connect to GND)
“H” level (Connect to VDD)
or
“L” level (Connect to GND)
4 - 25MHz
4 - 25MHz
4 - 25MHz
PLLEN Input
FSEL Input
Operating Frequency 2
2
Basic clock frequency
from the oscillator
circuit or an external
clock signal
4 - 5MHz
8 - 10MHz
4 - 20MHz
(External clock only)
fC2
“H” level
(Connect to VDD)
“L” level
(Connect to GND)
“H” level (Connect to VDD)
“L” level (Connect to GND)
“H” level (Connect to VDD)
or
“L” level (Connect to GND)
16 / 27
4 - 20MHz
4 - 20MHz
4 - 20MHz
Semiconductor
ML670100
DC Characteristics
(Condition: VDD=AVDD=VREF=2.7V to 3.6V, GND=AGND=0V, Ta=-40 to +85°C)
Item
Symbo
Condition
Min.
Typ.
Max.
l
High level input voltage 1
VIH1
1
0.65x VDD
VDD+0.3
High level input voltage 2
VIH2
2
2
VDD+0.3
Low level input voltage 1
VIL1
1
-0.3
0.3x VDD
Low level input voltage 2
VIL2
2
-0.3
0.8
High level output voltage
VOH
IOH=-4mA
2.2(*2)
V
-0.2
DD
IOH=-100uA
Low level output voltage
VOL
IOL= 4mA
0.4
Input leak current 1
|ILI|
VI=0/VDD ,3
2.0(*3)
Input leak current 2
|IL2|
VI=0/VDD ,4
10.0(*3)
Output leak current
|ILO|
VO=0/VDD
2.0(*3)
Input capacity
CI
6
Output capacity
CO
9
Input/output capacity
CIO
10
Power consumption
IDDH
fC= 25MHz
30
50
(in HALT mode)
No load
Power consumption
IDD
60
100
1
2
3
4
Applied to PIO8 - PIO0, XD7 - XD0, nEFIQ
Applied to nRST, nEA, DBSEL, TEST, FSEL, PLLEN, VCOM
Applied to Input pins other than OSC0
Applied to OSC0
(*1): Typ. means that VDD=3.3V, Ta=25 °C
(*2): 2.4V in case of that VDD=AVDD=VREF=3.0 to 3.6V
(*3): 20µA in case of that Ta is equal or greater than 50 °C
17 / 27
Unit
V
µA
µF
mA
Semiconductor
ML670100
AC Characteristics
(Condition: VDD=AVDD=VREF=2.7V to 3.6V, GND=AGND=0V,Ta=-40 to +85°C)
Clock timing
Item
Max.
Unit
Clock frequency
Symbol
fC
Condition
4
-
25
MHz
Clock cycle time
tC
40
-
250
Clock high level pulse width
tCH
16
-
-
Clock low level pulse width
tCL
16
-
-
External clock frequency
fEXC
4
-
25
VDD =3.0 to 3.6V
Min. Typ.
External clock cycle time
tEXC
40
-
250
External clock high level pulse width
tEXCH
16
-
-
External clock low level pulse width
tEXCL
16
-
-
Clock frequency
fC
4
-
20
Clock cycle time
tC
50
-
250
Clock high level pulse width
tCH
20
-
-
Clock low level pulse width
tCL
20
-
-
External clock frequency
fEXC
4
-
20
External clock cycle time
tEXC
50
-
250
External clock high level pulse width
tEXCH
20
-
-
External clock low level pulse width
tEXCL
20
-
-
Clock rise time
Clock fall time
VDD =2.7 to 3.6V
tR
-
-
-
5
tF
-
-
-
5
External clock rise time
tEXR
-
-
-
5
External clock fall time
tEXF
-
-
-
5
18 / 27
ns
MHz
ns
MHz
ns
MHz
ns
Semiconductor
Control Signals Timing
Item
ML670100
Symbol
Condition
Min.
Typ.
Max.
Unit
*
tRSTW1
-
2tC
-
-
ns
*
tRSTW2
Oscillation
-
-
-
nRST pulse width( 1)
nRST pulse width( 2)
stable time
nEFIQ pulse width
tEFIQW
-
2tC
-
-
nEIR pulse width
tEIRW
-
2tC
-
-
TMIN pulse width
tTMINW
-
2tC
-
-
tTMCLKW
-
2tC
-
-
fSC
-
-
-
1/8fC
SCLK high level pulse width
tSCLKH
-
4tC
-
-
SCLK low level pulse width
TMCLK pulse width
SCLKfrequency
tSCLKL
-
4tC
-
-
TXD delay time
tTXD
CL=50pF
-
-
1tC+22
RXD set-up time
tRXS
-
0.5tC
-
-
RXD hold time
tRXH
-
1.5tC
-
-
DBGRQ set-up time
tRQS
-
1.0
-
-
DBGRQ hold time
tRQH
-
2.6
-
-
DBGACK delay time
tDBGD
CL=50pF
2.4
-
15.2
(*1): Not applied to power-on.
(*2): Applied to power-on.
19 / 27
ns
MHz
ns
Semiconductor
External Bus Timing
Item
Symbol
XA[23:1],nLB/XA0 delay time
tXAD
XD[15:0] output delay time
tXDOD
XD[15:0] input set-up time
tXDIS
XD[15:0] input hold time
tXDIH
nXWAIT set-up time
tXWAITS
nXWAIT hold time
tXWAITH
nHB delay time
tHBD
nCS[1:0] delay time
tCSD
nWRE,nWRH,nWRL delay time tWRD
nRD delay time
tRDD
nRAS[1:0] delay time
tRASD
nCAS delay time
tCASD
nWE,nWH,nWL delay time
tWED
nBREQ set-up time
tBREQS
nBREQ hold time
tBREQH
nBACK delay time
tBACKD
High-impedance delay time
tXHD
ML670100
Condition
CL=50pF
20 / 27
Min.
3
5
11
0
3
0
2
2
3
4
3
3
2
5
3
4
4
Typ.
-
Max.
14
20
12
11
12
11
12
13
12
13
13
Unit
ns
Semiconductor
ML670100
Clock Timing
tC
tCH
tEXC
tEXCH tEXCL
tCL
tR
tF
tEXR
tEXF
CLKOUT
External
Clock
Control Signals Timing
tRSTW1, tRSTW2
nRST
tEFIQW, tEIRW
nEFIQ
nEIR
tTMINW, tTMCLKW
TMIN
TMCK
tSCLKH
tSCLKL
SCLK
tTXD
TXD
tRXS
RXD
21 / 27
tRXH
Semiconductor
ML670100
Control Signals Timing (Cont.)
CLKOUT
tDBGD
DBGACK
tRQS
DBGRQ
22 / 27
tRQH
Semiconductor
ML670100
External Bus Timing
Bank 0 and Bank 1 Write Cycle Timing
CLKOUT
tXAD
tXAD
XA23-1
nLB/XA
tHBD
tHBD
tCSD
tCSD
nHB
nCS0
nCS1
tWRD
tWRD
nWRE
nWRL
nWRH
tXDOD
tXDOD
Write Data
XD15-0
23 / 27
Semiconductor
ML670100
Bank 0 and Bank 1 Read Cycle Timing
CLKOUT
tXAD
tXAD
XA23-1
nLB/XA
tHBD
tHBD
tCSD
tCSD
nHB
nCS0
nCS1
tRDD
tRDD
nRD
tXDIS
Read Data
XD15-0
24 / 27
tXDIH
Semiconductor
ML670100
Bank 2 and Bank 3 Read/Write Cycle Timing
CLKOUT
tXAD
tXAD
XA23-1
nLB/XA
tRASD
tRASD
nRAS0
nRAS1
tCASD tCASD
nCAS
nCASL
nCASH
tXDIS tXDIH
XD15-0
(Read cycle)
tXDOD
tXDOD
XD15-0
(Write cycle)
tWED
tWED
nWE, nWL
nWH
(Write cycle)
CAS before RAS (CBR) Refresh
CLKOUT
tRASD
tRASD
nRAS
tCASD
tCASD
nCAS
25 / 27
Semiconductor
ML670100
Self Refresh
CLKOUT
tRASD
tRASD
nRAS
tCASD
tCASD
nCAS
nXWAIT Input Timing
CLKOUT
tXWAITS
tXWAITH
nXWAIT
External Bus Release Timing
CLKOUT
tBREQS
tBREQH
nBREQ
CLKOUT
tBACKD
nBACK
tXHD
tBACKD
tXHD
XA
XD
Control
Signals
26 / 27
Semiconductor
ML670100
A-to-D Converter Characteristics
(Condition: VDD=AVDD=VREF=2.7V to 3.6V, GND=AGND=0V,Ta=-40 to +85°C )
Item
Resolution
Linearity error
Differential
linearity error
Zero scale error
Full scale error
Conversion time
Symbol
n
EL
ED
EZS
EFS
Condition
Refer to the following
recommended circuit.
Analog input source impedance
RI is equal or less than 5K Ω
tCONV
Definitions of terms
Resolution
Linearity error
Differential
linearity error
Zero scale error
Full scale error
fC=25MHz
Min.
-3.0
-1.0
Typ.
-
Max.
8
+3.0
+1.0
Unit
bit
LSB
LSB
-
10.68
+2.0
-2.0
-
LSB
LSB
µS/CH
The minimum distinguishable analog value.
For 8 bits, 28=256, i.e.(VREF-AGND)/256.
Variance between the ideal conversion characteristics as an 8-bit A-to-D
converter and actual conversion characteristics (does not include
quantatized error).
Indicates the smoothness of the conversion. The width of analog input
voltage corresponding to the change by one bit of digital output is
1LSB=(VREF-AGND)/256 ideally. The variance between this ideal bit
size and bit size at arbitrary point in the conversion range.
Variance between the ideal conversion characteristics at the switching
point of digital output ”0x00” - ”0x01” and actual conversion
characteristics.
Variance between the ideal conversion characteristics at the switching
point of digital output ”0xFE” - ”0xFF” and actual conversion
characteristics.
3.3V
+
VRE
AVDD
3.3V
VDD
+
F
0.1
µF
Analog
input
-
47
µF
ML670100
0.1 0.1
µF µF
47
µF
RI
AI[7:0]
+
0.1
µF
GND
AGND
RI (Analog input source impedance) is equal or less than 5KΩ
27 / 27
0V
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