Renesas HM62V8100LTTI-5SL Wide temperature range version 8 m sram (1024-kword â´ 8-bit) Datasheet

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Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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April 1, 2003
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HM62V8100I Series
Wide Temperature Range Version
8 M SRAM (1024-kword × 8-bit)
ADE-203-1278B (Z)
Rev. 1.0
Mar. 12, 2002
Description
The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-word × 8-bit. HM62V8100I
Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS
process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch or standard 44-pin TSOP II
for high density surface mounting.
Features
•
•
•
•
•
•
•
•
Single 3.0 V supply: 2.7 V to 3.6 V
Fast access time: 55 ns (Max)
Power dissipation:
 Active: 6.0 mW/MHz (Typ)
 Standby: 1.5 µW (Typ)
Completely static memory.
 No clock or timing strobe required
Equal access and cycle times
Common data input and output.
 Three state output
Battery backup operation.
 2 chip selection for battery backup
Temperature range: –40 to +85°C
HM62V8100I Series
Ordering Information
Type No.
Access time
Package
HM62V8100LTTI-5
55 ns
400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE)
HM62V8100LTTI-5SL
55 ns
HM62V8100LBPI-5
55 ns
HM62V8100LBPI-5SL
55 ns
2
48-bumps CSP with 0.75 mm bump pitch (TBP-48A)
HM62V8100I Series
Pin Arrangement
44-pin TSOP
A4
A3
A2
A1
A0
CS1
NC
NC
I/O0
I/O1
VCC
VSS
I/O2
I/O3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
NC
NC
I/O7
I/O6
VSS
VCC
I/O5
I/O4
NC
NC
A9
A10
A11
A12
A13
A14
(Top view)
Pin Description (TSOP)
Pin name
Function
A0 to A19
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
3
HM62V8100I Series
48-bumps CSP
1
2
3
4
5
6
A
NC
OE
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1
NC
C
I/O0
NC
A5
A6
NC
I/O4
D
VSS
I/O1
A17
A7
I/O5
VCC
E
VCC
I/O2
NC
A16
I/O6
VSS
F
I/O3
NC
A14
A15
NC
I/O7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
(Top view)
Pin Description (CSP)
Pin name
Function
A0 to A19
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
4
HM62V8100I Series
Block Diagram (TSOP)
LSB
A5
A6
A7
A4
A3
A9
A10
A11
A12
A13
MSB A14
V CC
V SS
•
•
•
•
•
Row
decoder
I/O0
Memory matrix
2,048 x 4,096
Column I/O
•
•
Input
data
control
•
•
Column decoder
I/O7
LSB
MSB
A16 A17A18 A19 A0 A1 A2 A15A8
•
•
CS2
CS1
Control logic
WE
OE
5
HM62V8100I Series
Block Diagram (CSP)
LSB
A6
A15
A11
A16
A7
A13
A10
A2
A4
A1
MSB A3
V CC
V SS
•
•
•
•
•
Row
decoder
I/O0
Memory matrix
2,048 x 4,096
Column I/O
•
•
Input
data
control
Column decoder
I/O7
LSB
MSB
A12 A9 A18 A8 A14 A17 A5A0A19
•
•
CS2
CS1
Control logic
WE
OE
6
•
•
HM62V8100I Series
Operation Table
CS1
CS2
WE
OE
I/O0 to I/O7
Operation
H
×
×
×
High-Z
Standby
×
L
×
×
High-Z
Standby
L
H
H
L
Dout
Read
L
H
L
×
Din
Write
L
H
H
H
High-Z
Output disable
Note: H: V IH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to V SS
VCC
–0.5 to + 4.6
1
V
2
Terminal voltage on any pin relative to V SS
VT
–0.5* to V CC + 0.3*
V
Power dissipation
PT
1.0
W
Storage temperature range
Tstg
–55 to +125
°C
Storage temperature range under bias
Tbias
–40 to +85
°C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
3.6
V
VSS
0
0
0
V
Input high voltage
VIH
2.2
—
VCC + 0.3
V
Input low voltage
VIL
–0.3
—
0.6
V
Ambient temperature range
Ta
–40
—
85
°C
Note:
Note
1
1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
7
HM62V8100I Series
DC Characteri stics
Parameter
Symbol Min
Typ* 1 Max
Unit
Test conditions
Input leakage current
|ILI|
—
—
1
µA
Vin = VSS to V CC
Output leakage current
|ILO |
—
—
1
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL, or
VI/O = VSS to V CC
Operating current
I CC
—
—
20
mA
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL, I I/O = 0 mA
Average operating current
I CC1
—
14
25
mA
Min. cycle, duty = 100%,
I I/O = 0 mA, CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
I CC2
—
2
4
mA
Cycle time = 1 µs, duty = 100%,
I I/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ V CC – 0.2 V
VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V
Standby current
I SB
—
0.1
0.3
mA
CS2 = VIL
2
—
0.5
25
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ V CC – 0.2 V,
CS2 ≥ V CC – 0.2 V
I SB1*3
—
0.5
10
µA
Output high voltage
VOH
2.2
—
—
V
I OH = –1 mA
Output low voltage
VOL
—
—
0.4
V
I OL = 2 mA
Standby current
Note:
I SB1*
1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L version.
3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Note
Input capacitance
Cin
—
—
8
pF
Vin = 0 V
1
Input/output capacitance
CI/O
—
—
10
pF
VI/O = 0 V
1
Note:
8
1. This parameter is sampled and not 100% tested.
HM62V8100I Series
AC Characteristics (Ta = –40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: VIL = 0.4 V, VIH = 2.2 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
VTM
R1
Dout
R1 = 3070 Ω
30pF
R2
R2 = 3150 Ω
VTM = 2.8 V
9
HM62V8100I Series
Read Cycle
HM62V8100I
-5
Parameter
Symbol
Min
Max
Unit
Read cycle time
t RC
55
—
ns
Address access time
t AA
—
55
ns
Chip select access time
t ACS1
—
55
ns
t ACS2
—
55
ns
Output enable to output valid
t OE
—
35
ns
Output hold from address change
t OH
10
—
ns
Chip select to output in low-Z
t CLZ1
10
—
ns
2, 3
t CLZ2
10
—
ns
2, 3
Output enable to output in low-Z
t OLZ
5
—
ns
2, 3
Chip deselect to output in high-Z
t CHZ1
0
20
ns
1, 2, 3
t CHZ2
0
20
ns
1, 2, 3
t OHZ
0
20
ns
1, 2, 3
Output disable to output in high-Z
10
Notes
HM62V8100I Series
Write Cycle
HM62V8100I
-5
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t WC
55
—
ns
Address valid to end of write
t AW
50
—
ns
Chip selection to end of write
t CW
50
—
ns
5
Write pulse width
t WP
40
—
ns
4
Address setup time
t AS
0
—
ns
6
Write recovery time
t WR
0
—
ns
7
Data to write time overlap
t DW
25
—
ns
Data hold from write time
t DH
0
—
ns
Output active from end of write
t OW
5
—
ns
2
Output disable to output in High-Z
t OHZ
0
20
ns
1, 2
Write to output in high-Z
t WHZ
0
20
ns
1, 2
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest
transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest
transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the
beginning of write to the end of write.
5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. t AS is measured from the address valid to the beginning of write.
7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
11
HM62V8100I Series
Timing Waveform
Read Cycle
t RC
Address
Valid address
tAA
tACS1
CS1
tCLZ1*2, 3
CS2
tCHZ1*1, 2, 3
tACS2
tCLZ2*2, 3
tCHZ2*1, 2, 3
tOHZ*1, 2, 3
tOE
OE
tOLZ*2, 3
Dout
12
High impedance
tOH
Valid data
HM62V8100I Series
Write Cycle (1) (WE Clock)
tWC
Valid address
Address
tWR*7
tCW*5
CS1
tCW*5
CS2
tAW
tWP*4
WE
tAS*6
tDW
tDH
Valid data
Din
tWHZ*1, 2
tOW*2
High impedance
Dout
13
HM62V8100I Series
Write Cycle (2) (CS Clock, OE = VIH)
tWC
Valid address
Address
tAW
tAS*6
tWR*7
tCW*5
CS1
tCW*5
CS2
tWP*4
WE
tDW
Valid data
Din
High impedance
Dout
14
tDH
HM62V8100I Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ* 4
Max
Unit
Test conditions*3
VCC for data retention
VDR
2.0
—
3.6
V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V
CS1 ≥ V CC – 0.2 V
Data retention current
I CCDR*1
—
0.5
25
µA
VCC = 3.0 V, Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V,
CS1 ≥ V CC – 0.2 V
I CCDR*2
—
0.5
10
µA
Chip deselect to data
retention time
t CDR
0
—
—
ns
Operation recovery time
tR
t RC* 5
—
—
ns
See retention waveform
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for L-SL version.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1
controls data retention mode, CS2 must be CS2 ≥ V CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other
input levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.
5. t RC = read cycle time.
15
HM62V8100I Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR
Data retention mode
tR
VCC
2.7 V
2.2 V
VDR
CS1
0V
CS1 ≥ VCC – 0.2 V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR
Data retention mode
VCC
2.7 V
CS2
VDR
0.6 V
0V
16
0 V < CS2 < 0.2 V
tR
HM62V8100I Series
Package Dimensions
HM62V8100LTTI Series (TTP-44DE)
As of July, 2001
Unit: mm
18.41
18.81 Max
23
10.16
44
0.80
*0.27 ± 0.07
0.25 ± 0.05
22
0.80
0.13 M
11.76 ± 0.20
1.005 Max
*Dimension including the plating thickness
Base material dimension
0.13 ± 0.05
0.10
*0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0˚ – 5˚
0.50 ± 0.10
Hitachi Code
JEDEC
JEITA
Mass (reference value)
0.68
1
TTP-44DE
—
—
0.43 g
17
HM62V8100I Series
HM62V8100LBPI Series (TBP-48A)
As of July, 2001
6.50
0.20 S A
2.275
0.20 S B
Unit: mm
A
INDEX
MARK
A
6
5
4
3
2
1
Pin#1 INDEX
A
B
9.80
C
D
E
F
0.75
G
4×
0.75
0.15
0.2 S
1.375
48 × φ0.35 ± 0.05
φ0.08 M S A B
1.2 Max
0.25 ± 0.05
S
0.10 S
H
Details of the part A
Hitachi Code
JEDEC
JEITA
Mass (reference value)
18
TBP-48A
–
–
0.13 g
B
HM62V8100I Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
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