Intersil HSP9520CP Multilevel pipeline register Datasheet

HSP9520, HSP9521
Data Sheet
May 1999
Multilevel Pipeline Registers
Features
These devices are multilevel pipeline registers implemented
using a low power CMOS process. They are pin for pin
compatible replacements for industry standard multilevel
pipeline registers such as the L29C520 and L29C521. The
HSP9520 and HSP5921 are direct replacements for the
AM29520 and AM29521 and WS59520 and WS59521.
• Four 8-Bit Registers
File Number
2811.5
• Hold, Transfer and Load Instructions
• Single 4-Stage or Dual-2 Stage Pipelining
• All Register Contents Available at Output
• Fully TTL Compatible
They consist of four 8-bit registers which are dual ported.
They can be configured as a single four level pipeline or a
dual two level pipeline. A single 8-bit input is provided, and
the pipelining configuration is determined by the instruction
code input to the I0 and I1 inputs (see instruction control).
• Three-State Outputs
• High Speed, Low Power CMOS
Applications
The contents of any of the four registers is selectable at the
multiplexed outputs through the use of the S0 and S1
multiplexer control inputs (see register select. The output is 8
bits wide and is three-stated through the use of the OE input.
• Array Processor
The HSP9520 and HSP9521 differ only in the way data is
loaded into and between the registers in dual two-level
operation. In the HSP9520 when data is loaded into the first
level the existing data in the first level is moved to the second
level. In the HSP9521 loading the first level simply causes
the current data to be overwritten. Transfer of data to the
second level is achieved using the single four level mode (I1,
I0 = ‘0’). This instruction also causes the first level to be
loaded. The HOLD instruction (I1, I0 = ‘1’) provides a means
of holding the contents of all registers.
• Telecommunication
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
• Digital Signal Processor
• A/D Buffer
• Byte Wide Shift Register
• Mainframe Computers
Pinout
HSP9520, HSP9521 (SOIC, PDIP)
TOP VIEW
I0 1
24 VCC
I1 2
23 S0
D0 3
22 S1
D1 4
21 Y0
D2 5
20 Y1
D3 6
19 Y2
D4 7
18 Y3
HSP9520CP
0 to 70
24 Ld PDIP
E24.3
HSP9520CS
0 to 70
24 Ld SOIC
M24.3
D5 8
17 Y4
E24.3
D6 9
16 Y5
D7 10
15 Y6
CLK 11
14 Y7
GND 12
13 OE
HSP9521CP
HSP9521CS
0 to 70
24 Ld PDIP
0 to 70
24 Ld SOIC
1
M24.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HSP9520, HSP9521
Block Diagram
I0
D0 - D7
REG. A1
8
REG. A2
CLK
MUX
MUX
I1
REG. B1
REG. B2
8
Y0 - Y7
OE
S0
S1
Pin Descriptions
NAME
DIP PIN
TYPE
DESCRIPTION
VCC
24
The +5V Power Supply Pin. A 0.1µF capacitor between the VCC and GND pin is recommended.
GND
12
The device ground.
CLK
11
I
Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and hold times with
respect to the clock must be met for proper operation.
D0-7
3-10
I
Data Input Port. These inputs are used to supply the 8 bits of data which will be latched into the selected
register on the next rising clock edge.
Y0-7
21-14
O
Data Output Port. This 8-bit port provides the output data from the four internal registers. They are provided in
a multiplexed fashion, and are controlled via the multiplexer control inputs (S0 and S1).
I0, I1
1, 2
I
Instruction Control Inputs. These inputs are used to provide the instruction code which determines the internal
register pipeline configuration. Refer to the Instruction Control Table for the specific codes and their associated
configurations.
S0, S1
23, 22
I
Multiplexer Control Inputs. These inputs select which of the four internal registers contents will be available at
the output port. Refer to the Register Select Table for the codes to select each register.
OE
13
I
Output Enable. This input controls the state of the output port (Y0 - Y7). A LOW on this control line enables
the port for output. When OE is HIGH, the output drivers are in the high impedance state. Internal latching or
transfer of data is not affected by this pin.
2
HSP9520, HSP9521
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input or Output Voltage Applied . . . . . . . . . . GND -0.5 to VCC +0.5V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
67
SOIC Package . . . . . . . . . . . . . . . . . . .
77.0
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to 5.25V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
VCC = 5.0V ±5%, TA = 0oC to 70oC
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Logical One Input Voltage
VIH
VCC = 5.25V
2.0
-
V
Logical Zero Input Voltage
VIL
VCC = 4.75V
-
0.8
V
Output HIGH Voltage
VOH
IOH = -6.5mA, VCC - 4.75V
2.4
-
V
Output LOW Voltage
VOL
IOH = +20.0mA, VCC = 4.75V
-
0.5
V
Input Leakage Current
II
VIN = VCC or GND, VCC = 5.25V
-10
-10
µA
Output Leakage Current
IO
VOUT = VCC or GND, VCC = 5.25V
-10
-10
µA
Standby Power Supply Current
ICCSB
VIN = VCC or GND, VCC = 5.25V Outputs Open
-
500
µA
Operating Power Supply Current
ICCOP
f = 5.0MHz, VIN = VCC or GND, VCC = 5.25V, Outputs
Open (Note 2)
-
12
mA
FREQ = 1MHZ, VCC = Open, All Measurements are
Referenced to Device Ground
-
12
pF
-
12
pF
MIN
MAX
UNITS
tPD
-
21
ns
tSELD
-
20
ns
Input Setup Time (DO-7/10-7)
tS
10
-
ns
Input Hold Time (DO-7/10-7)
tH
3
-
ns
Output Enable Time
tENA
-
20
ns
Output Disable Time
tDIS
-
13
ns
Clock Pulse Width
tPW
10
-
ns
Input Capacitance
CIN
Output Capacitance
CO
AC Electrical Specifications
PARAMETER
VCC = 5.0V ±5%, TA = 0oC to 70oC (Note 3)
SYMBOL
Clock to Data Out
Mux Select to Data Out
TEST CONDITIONS
(Note 4)
NOTES:
2. Power supply current is proportional to frequency. Typical rating for ICCOP is 2.4mA/MHz.
3. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output
load CL = 40pF.
4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major design and/or process
changes.
3
HSP9520, HSP9521
Timing Waveform
t PW
CLOCK
(CLK)
tH
tS
t PW
INST
(I0 - I1)
tH
tS
DATA
(S0 - D7)
MUX SEL
(S0 - S1)
t PD
OUT
(Y0 - Y7)
1.5V
t SELD
OE
THREE STATE
CONTROL
t DIS
THREE STATE
OUTPUT
(Y0 - Y7)
t ENA
(HIGH IMPEDANCE)
TABLE 1. INSTRUCTION CONTROL
I1
0
0
1
1
I0
HSP9520
TABLE 2. REGISTER SELECT
HSP9521
A1
B1
A1
B1
A2
B2
A2
B2
A1
B1
A1
B1
A2
B2
A2
B2
A1
B1
A1
B1
A2
B2
A2
B2
0
1
1.7V
1.3V
S1
S0
HSP9520 OR HSP9521
0
0
B2
0
1
B1
1
0
A2
1
1
A1
0
1
All Registers Hold
All Registers Hold
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