CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Features Benefits ■ High-accuracy PLL with 12-bit multiplier and 10-bit divider ■ Enables synthesis of highly accurate and stable output clock frequencies with zero PPM ■ EPROM programmability ■ Enables quick turnaround of custom frequencies ■ 3.3V or 5V operation ■ Supports industry standard design platforms ■ Operating frequency ❐ 390 kHz–133 MHz at 5V ❐ 390 kHz–100 MHz at 3.3V ■ Services most PC, networking, and consumer applications ■ Lowers cost of oscillator as PLL can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock ■ Duty cycle centered at 1.5V or VDD/2 ■ Provides flexibility to service most TTL or CMOS applications ■ Provides flexibility in output configurations and testing ■ Enables low-power operation or output enable function and flexibility for system applications, through selectable instantaneous or synchronous change in outputs ■ Suitable for most PC, consumer, and networking applications ■ Has lower EMI than oscillators ■ Suitable to fit most applications ■ Easy customization and fast turnaround ■ Reference input from either a 10–30 MHz fundamental toned crystal or a 1–75 MHz external clock ■ EPROM selectable TTL or CMOS duty cycle levels ■ Sixteen selectable post-divide options, using either PLL or reference oscillator/external clock ■ Programmable PWR_DWN or OE pin, with asynchronous or synchronous modes ■ Low jitter outputs typically ❐ 80 ps at 3.3V/5V ■ Controlled rise and fall times and output slew rate ■ Available in both commercial and industrial temperature ranges ■ Factory programmable device options Logic Block Diagram XTALIN or external clock Q 10 bits Phase Detector XTALOUT[1] Crystal Oscillator PWR_DWN or OE Charge Pump Configuration EPROM VCO P 12 bits HIGH ACCURACY PLL MUX / 1, 2, 4, 8, 16, 32, 64, 128 CLKOUT Note 1. When using an external clock source, leave XTALOUT floating. Cypress Semiconductor Corporation Document Number: 38-07210 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 15, 2008 [+] Feedback CY2077 Pin Configuration Figure 1. Pin Diagram - 8 Pin Top View VDD XTALOUT XTALIN PD/OE 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS Table 1. Pin Definition - 8 Pin Pin Name VDD VSS XD XG PWR_DWN / OE CLKOUT Pin # 1 5,6,7 2 3 4 8 Pin Description Voltage supply Ground (all the pins must be grounded) Crystal output (leave this pin floating when external reference is used) Crystal input or external input reference EPROM programmable power down or output enable pin. Weak pull up Clock output. Weak pull down Functional Description EPROM Configuration Block CY2077 is an EPROM-programmable, high-accuracy, general-purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. Table 2. EPROM Adjustable Features CY2077 can generate a clock output up to 133 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. TTL or CMOS duty cycles can be selected. Power management with the CY2077 is also very flexible. The user can choose either a PWR_DWN, or an OE feature with which both have integrated pull up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. There is a weak pull down on the output that pulls CLKOUT LOW when either the PWR_DWN or OE signal is active. This weak pull down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. EPROM Adjustable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) Adjust Freq. PLL Output Frequency CY2077 contains a high-resolution PLL with 12-bit multiplier and 10-bit divider.[2] The output frequency of the PLL is determined by the following formula: 2 • (P + 5) F PLL = --------------------------- • F REF (Q + 2) where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyberClocks™ software. Refer to ““Programming Procedures” on page 12” for details. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications that require low jitter and accurate reference frequencies. Note 2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5V VDD supply, and 50 MHz to 180 MHz for 3V VDD supply. The output frequency is determined by the selected output divider. Document Number: 38-07210 Rev. *C Page 2 of 14 [+] Feedback CY2077 Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both the PLL and oscillator circuit must relock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back HIGH. Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode prevents output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN, or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT. Table 3. Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition VDD = 4.5–5.5V VDD = 3.0–3.6V Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage .................................................. –0.5 to +7.0V Min 0.39 0.39 Max 133 100 Unit MHz MHz Input voltage ........................................... –0.5V to VDD +0.5V Storage temperature (non-condensing)...... –55°C to +150°C Junction temperature.................................................. 150°C Static discharge voltage........................................... > 2000V (per MIL-STD-883, method 3015) Operating Conditions for Commercial Temperature Device Parameter Description VDD Supply voltage Operating temperature, ambient TA Max. capacitive load on outputs for TTL levels CTTL VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz CCMOS XREF tPU Max. capacitive load on outputs for CMOS levels VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz VDD = 3.0 – 3.6V, output frequency = 1 – 40 MHz VDD = 3.0 – 3.6V, output frequency = 40 – 100 MHz Reference frequency, input crystal with Cload = 10 pF Reference frequency, external clock source Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Document Number: 38-07210 Rev. *C Min 3.0 0 Max 5.5 +70 Unit V °C 50 25 15 pF pF pF 10 1 50 25 15 30 15 30 75 pF pF pF pF pF MHz MHz 0.05 50 ms Page 3 of 14 [+] Feedback CY2077 Electrical Characteristics TA = 0°C to +70°C Parameter Description Test Conditions Min Typ Max Unit VIL Low-level input voltage VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V 0.8 0.2VDD V V VIH High-level input voltage VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V VOL Low-level output voltage VDD = 4.5 – 5.5V, IOL= 16 mA VDD = 3.0 – 3.6V, IOL= 8 mA VOHCMOS High-level output voltage CMOS levels VDD = 4.5 – 5.5V, IOH= –16 mA VDD = 3.0 – 3.6V, IOH= –8 mA VDD – 0.4 VDD – 0.4 V V VOHTTL High-level output voltage TTL levels VDD = 4.5 – 5.5V, IOH= –8 mA 2.4 V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input low current VIN = 0V 10 μA IIH Input high current VIN = VDD 5 μA IDD Power supply current Unloaded VDD = 4.5 – 5.5V, output frequency <= 133 MHz VDD = 3.0 – 3.6V, output frequency <= 100 MHz 45 25 mA mA IDDS[3] Stand-by current (PD = 0) VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V 25 10 100 50 μA RUP Input pull up resistor VDD = 4.5 – 5.5V, VIN = 0V VDD = 4.5 – 5.5V, VIN = 0.7VDD 3.0 100 8.0 200 MΩ kΩ IOE_CLKOUT CLKOUT pull down current VDD = 5.0 1.1 50 20 μA Note 3. If external reference is used, it is required to stop the reference (set reference to LOW) during power down. Document Number: 38-07210 Rev. *C Page 4 of 14 [+] Feedback CY2077 Output Clock Switching Characteristics Commercial Over the Operating Range[4] Parameter Description Test Conditions Min Typ Max Unit t1w Output duty cycle at 1.4V, VDD = 4.5 – 5.5V t1w = t1A ÷ t1B 1 – 40 MHz, CL <= 50 pF 40 – 125 MHz, CL <= 25 pF 125 – 133 MHz, CL <= 15 pF 45 45 45 55 55 55 % % % t1x Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 50 pF VDD = 4.5 – 5.5V 40 – 125 MHz, CL <= 25 pF t1x = t1A ÷ t1B 125 – 133 MHz, CL <= 15 pF 45 45 45 55 55 55 % % % t1y Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 30 pF VDD = 3.0 – 3.6V 40 – 100 MHz, CL <= 15 pF t1y = t1A ÷ t1B 45 40 55 60 % % t2 Output clock rise time Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 50 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 25 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 50 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 30 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output clock fall time Between 0.8V –2.0V, VDD = 4.5V – 5.5V, CL = 50 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 25 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 50 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 30 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 15 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Start-up time out of power down PWR_DWN pin LOW to HIGH[5] 1 2 ms t5a Power down delay time (synchronous setting) PWR_DWN pin LOW to output LOW (T= period of output CLK) T/2 T+ 10 ns t5b Power down delay time (asynchronous setting) PWR_DWN pin LOW to output LOW 10 15 ns t6 Power up time From power on[5] 1 2 ms t7a Output disable time (synchronous setting) OE pin LOW to output high-Z (T= period of output CLK) T/2 T+ 10 ns t7b Output disable time (asynchronous setting) OE pin LOW to output high-Z 10 15 ns t8 Output enable time (always synchronous enable) OE pin LOW to HIGH (T= period of output CLK) T 1.5T + 25ns ns t9 Peak-to-peak period jitter VDD = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0V – 5.5V, Fo < 33 MHz 80 150 0.3% 1% ps % of FO Notes 4. Not all parameters measured in production testing. 5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70Ω. Document Number: 38-07210 Rev. *C Page 5 of 14 [+] Feedback CY2077 Operating Conditions for Industrial Temperature Device Parameter Description Min Max Unit VDD Supply voltage 3.0 5.5 V TA Operating temperature, ambient –40 +85 °C CTTL Max. capacitive load on outputs for TTL levels VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz 35 15 10 pF pF pF CCMOS Max. capacitive load on outputs for CMOS levels VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz VDD = 3.0 – 3.6V, output frequency = 1 – 40 MHz VDD = 3.0 – 3.6V, output frequency = 40 – 100 MHz 35 15 10 20 10 pF pF pF pF pF XREF tPU Reference frequency, input crystal with Cload = 10 pF 10 30 MHz Reference frequency, external clock source 1 75 MHz 0.05 50 ms Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Electrical Characteristics TA = –40°C to +85°C Parameter Description Test Conditions Min Typ. Max Unit 0.8 0.2VDD V V VIL Low-level input voltage VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V VIH High-level input voltage VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V VOL Low-level output voltage VDD = 4.5 – 5.5V, IOL= 16 mA VDD = 3.0 – 3.6V, IOL= 8 mA VOHCMOS High-level output voltage, CMOS levels VDD = 4.5 – 5.5V, IOH= –16 mA VDD = 3.0 – 3.6V, IOH= –8 mA VDD – 0.4 VDD – 0.4 V V VOHTTL High-level output voltage, TTL levels VDD = 4.5 – 5.5V, IOH= –8 mA 2.4 V V V 2.0 0.7VDD 0.4 0.4 V V IIL Input low current VIN = 0V 10 μA IIH Input high current VIN = VDD 5 μA IDD Power supply current, Unloaded VDD = 4.5 – 5.5V, output frequency <= 133 MHz VDD = 3.0 – 3.6V, output frequency <= 100 MHz 45 25 mA mA IDDS[3] Stand-by current (PD = 0) VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V 25 10 100 50 μA RUP Input pull up resistor VDD = 4.5 – 5.5V, VIN = 0V VDD = 4.5 – 5.5V, VIN = 0.7VDD 3.0 100 8.0 200 MΩ kΩ IOE_CLKOUT CLKOUT pull down current Document Number: 38-07210 Rev. *C VDD = 5.0 1.1 50 20 μA Page 6 of 14 [+] Feedback CY2077 Output Clock Switching Characteristics Industrial Over the Operating Range[4] Parameter Description Test Conditions Min Typ. Max Unit t1w Output duty cycle at 1.4V, 1 – 40 MHz, CL <= 35 pF VDD = 4.5 – 5.5V 40 – 125 MHz, CL <= 15 pF t1w = t1A ÷ t1B 125 – 133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1x Output duty cycle at 1 – 40 MHz, CL <= 35 pF VDD/2, VDD = 4.5 – 5.5V 40 – 125 MHz, CL <= 15 pF t1x = t1A ÷ t1B 125 – 133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1y Output duty cycle at 1– 40 MHz, CL <= 20 pF VDD/2, VDD = 3.0 – 3.6V 40 – 100 MHz, CL <= 10 pF t1y = t1A ÷ t1B 45 40 55 60 % % t2 Output clock rise time Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 35 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 10 pF Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 35 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 20 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 10 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output clock fall time Between 0.8V – 2.0V, VDD = 4.5V – 5.5V, CL = 35 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 15 pF Between 0.8 – 2.0V, VDD = 4.5V – 5.5V, CL = 10 pF Between 0.2VDD – 0.8VDD, VDD= 4.5V – 5.5V, CL = 35 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 20 pF Between 0.2VDD – 0.8VDD, VDD= 3.0V – 3.6V, CL = 10 pF 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Start-up time out of Power down PWR_DWN pin LOW to HIGH[5] 1 2 ms t5a Power down delay time (synchronous setting) PWR_DWN pin LOW to output LOW (T= period of output clk) T/2 T+10 ns t5b Power down delay time (asynchronous setting) PWR_DWN pin LOW to output LOW 10 15 ns t6 Power up time From power on[5] 1 2 ms t7a Output Disable time (synchronous setting) OE pin LOW to output high-Z (T= period of output clk) T/2 T + 10 ns t7b Output Disable time (asynchronous setting) OE pin LOW to output high-Z 10 15 ns t8 Output Enable time (always synchronous enable) OE pin LOW to HIGH (T = period of output clk) T 1.5T + 25ns ns t9 Peak-to-peak period jitter VDD = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0V – 5.5V, Fo < 33 MHz 80 150 ps 0.3% 1% % of FO Document Number: 38-07210 Rev. *C Page 7 of 14 [+] Feedback CY2077 Switching Waveforms Figure 2. Duty Cycle Timing (t1w, t1x, t1y) t1A OUTPUT t1B Figure 3. Output Rise/Fall Time VDD OUTPUT 0V t3 t2 Figure 4. Power down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL t4 0V CLKOUT (synchronous[6]) T t5a 1/f CLKOUT (asynchronous[7]) t5b 1/f Figure 5. Power up Timing VDD POWER UP 0V VDD – 10% t6 min 30 μs max 30 ms CLKOUT 1/f Figure 6. Output Enable Timing (synchronous and asynchronous modes) OUTPUT ENABLE VDD VIH VIL 0V T CLKOUT High Impedance (synchronous[6]) t7a CLKOUT t8 High Impedance (asynchronous[7]) t7b t8 Notes 6. In synchronous mode, the power down or output three-state is not initiated until the next falling edge of the output clock. 7. In asynchronous mode, the power down or output three-state occurs within 25 ns regardless of position in the output clock cycle. Document Number: 38-07210 Rev. *C Page 8 of 14 [+] Feedback CY2077 Typical Rise/Fall Time[8] Trends for CY2077 Figure 7. Rise/Fall Time vs. VDD over Temperatures Rise Time vs. VDD -- CMOS duty Cycle Cload = 15pF Rise Time (ns) 2.00 1.80 -40C 25C 85C 1.60 1.40 1.20 Fall Time (ns) Fall Time vs. VDD -- CMOS duty Cycle Cload = 15pF 1.00 2.7 3.0 3.3 3.6 2.00 1.80 1.60 1.40 1.20 1.00 -40C 25C 85C 2.7 3.9 3.0 0.70 0.60 0.50 0.40 0.30 0.20 -40C 25C 85C 5.0 3.9 Fall Time vs. VDD -- TTL duty Cycle Cload = 15pF 5.5 Fall Time (ns) Rise Time (ns) Rise Time vs. VDD -- TTL duty Cycle Cload = 15pF 4.5 3.6 VDD (V) VDD (V) 4.0 3.3 0.70 0.60 0.50 0.40 0.30 0.20 6.0 -40C 25C 85C 4.0 4.5 VDD (V) 5.0 5.5 6.0 VDD (V) Figure 8. Rise/Fall Time vs. Output Loads over Temperatures Fall Time vs. CLoad over Temperature VDD = 3.3v, CMOS output 2.50 -40C 25C 85C 2.00 1.50 1.00 10 15 20 25 Cload (pF) 30 35 Fall Time (ns) Rise Time (ns) Rise Time vs. CLoad over Temperature VDD = 3.3v, CMOS output 2.00 -40C 25C 85C 1.50 1.00 10 15 20 25 30 35 Cload (pF) Note 8. Rise/Fall time for CMOS output is measured between 1.2 VDD and 0.8 VDD. Rise/Fall time for TTL output is measured between 0.8V and 2.0V. Document Number: 38-07210 Rev. *C Page 9 of 14 [+] Feedback CY2077 Typical Duty Cycle[9] Trends for CY2077 Figure 9. Duty Cycle vs. VDD over Temperatures 55.00 53.00 51.00 49.00 47.00 45.00 Duty Cycle vs. VDD over Temperature (CMOS Duty Cycle Ouput, Fout=50MHz, Cload=50pF) -40C 25C 85C 4.0 4.5 5.0 5.5 Duty Cycle (%) Duty Cycle (%) Duty Cycle vs. VDD over Temperature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) 55.00 53.00 51.00 49.00 47.00 45.00 6.0 -40C 25C 85C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (v) Figure 10. Duty Cycle vs. Output Load Duty Cycle (%) Duty Cycle vs. CLoad with Various VDD (Fout = 50MHz, Temp = 25C) 55.00 53.00 51.00 49.00 47.00 45.00 VDD=4.5V VDD=5.0V VDD=5.5V 10 15 20 25 30 35 40 45 50 55 Cload (pF) Output DC (%) Figure 11. Duty Cycle vs. Output Frequency over Temperatures Output Duty Cycle vs. Fout over Temperature (Vdd = 5V, Cload = 15pF) 55.00% 54.00% 53.00% 25C 52.00% 85C 51.00% -40C 50.00% 20 30 40 50 60 70 80 Output Frequency (MHz) Note 9. Duty cycle is measured at 1.4V for TTL output and 0.5 VDD for CMOS output. Document Number: 38-07210 Rev. *C Page 10 of 14 [+] Feedback CY2077 Typical Jitter Trends for CY2077 Figure 12. Period Jitter (pk-pk) vs. VDD over Temperatures Period Jitter (pk-pk) vs. VDD over Temperatures (Fout=40MHz, Cload = 30pF) Period JItter (ps) 100 80 60 -40C 40 25C 20 85C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures Output Jitter (pk-pk) vs. Output Frequency (VDD=3.3V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) Output Jitter(pk-pk) vs. Output Frequency (VDD=5.0V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) Document Number: 38-07210 Rev. *C Page 11 of 14 [+] Feedback CY2077 Programming Procedures Currently the CY2077 is available only as a field-programmable device, as indicated by an “F” in the ordering code. Devices may be programmed using the CY3670 programmer, or via programmers available from third party programmer manufacturers such as Hi-Lo Systems and BP Micro. Programming services are also available from third parties, including some Cypress distribution partners. To generate a JEDEC format programming file, customers should use CyClocks software. This software automatically calculates the output frequencies that can be generated by CY2077 devices. The CyClocks software is a subset of the larger software tool CyberClocks, which is available free of charge from the Cypress web site (http://www.cypress.com). CyberClocks is installed on a PC and should not be confused with the web-based application CyberClocks Online. For high volume designs, factory programming of customer-specific configurations is available on other 8-pin devices such as the CY22180, CY22801 and CY22381. Factory programming is no longer offered for new designs using the CY2077. Ordering Information Order Code[11] CY2077FS Package Name Package Type Operating Temp. Range Operating Voltage S8 8-pin SOIC Commercial (T = 0°C to 70°C) 3.3V or 5V CY2077FSXC S8 8-pin SOIC Commercial (T = 0°C to 70°C) 3.3V or 5V CY2077FSXCT S8 8-pin SOIC–Tape & Reel Commercial (T = 0°C to 70°C) 3.3V or 5V CY2077FZZ Z8 8-pin TSSOP Commercial (T = 0°C to 70°C) 3.3V or 5V Pb-Free Table 4. Obsolete or Not For New Designs Original Device Order Code[10, 11] Replacement Device Description Order Code CY2077SC-xxx none CY2077SC-xxxT none CY2077SI-xxx none CY2077SI-xxxT none CY2077SXC-xxx none CY2077SXC-xxxT none CY2077ZC-xxx none CY2077ZC-xxxT none CY2077ZI-xxx none CY2077ZI-xxxT none CY2077ZXC-xxx none CY2077ZXC-xxxT CY2077FSI Description none SOIC, Industrial (T = –40°C to 85°C) CY2077FSXC Pb-free SOIC, Commercial CY2077FZ TSSOP, Commercial (T = 0°C to 70°C) CY2077FZZ Pb-free TSSOP, Commercial CY2077FZI TSSOP, Industrial (T = –40°C to 85°C) CY2077FZZ Pb-free TSSOP, Commercial Notes 10. The CY2077SC-xxx(T), CY2077SI-xxx(T), CY2077SXC-xxx(T), CY2077ZC-xxx(T), CY2077ZI-xxx(T) andCY2077ZXC-xxx(T), are factory programmed configurations. Factory programming is available for high-volume design opportunities. For more details, contact your local Cypress FAE or Cypress Sales Representative. 11. The CY2077F are field programmable. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document Number: 38-07210 Rev. *C Page 12 of 14 [+] Feedback CY2077 Package Diagrams Figure 14. 8-pin (150 mil Body) SOIC (Small Outline IC) PIN 1 ID 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] X 45° 0.016[0.406] SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.0075[0.190] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0138[0.350] 0.0192[0.487] 51-85066 *C Figure 15. 8-pin (4.40-mm Body) TSSOP (Thin Shrunk Small Outline Package) PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PART # Z08.173 STANDARD PKG. ZZ08.173 LEAD FREE PKG. 8 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093 *A Document Number: 38-07210 Rev. *C Page 13 of 14 [+] Feedback CY2077 Document History Page Document Title: CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Document Number: 38-07210 REV. ECN NO. Issue Date Orig. of Change ** 111727 02/07/02 DSG Convert from Spec number: 38-01009 to 38-07210 *A 114938 07/24/02 CKN Added table and notes to page 11 *B 121843 12/14/02 RBI Power up requirements added to Operating Conditions Information *C 2104546 See ECN Description of Change PYG/KVM Updated Ordering Information table /AESA Replaced the “Custom Configuration Request Procedure” section with “Programming Procedures” Updated package diagrams © Cypress Semiconductor Corporation, 2002-2008. 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Document Number: 38-07210 Rev. *C Revised February 15, 2008 Page 14 of 14 CyberClocks is a trademark of Cypress Semiconductor. All product or company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback