Elpida HM5165165FJ-6 64m edo dram (4-mword ã 16-bit) 8k refresh/4k refresh Datasheet

HM5164165F Series
HM5165165F Series
E0099H10 (1st edition)
(Previous ADE-203-1058C(Z))
Jan. 31, 2001
L
EO
64M EDO DRAM (4-Mword × 16-bit)
8k refresh/4k refresh
Description
Features
Pr
The HM5164165F S erie s, HM5165165F S erie s ar e 64M-bit dynamic R AMs orga nized as 4, 194,304-w ord
× 16-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology.
HM5164165F Series, HM5165165F Series offer Extended Data Out (EDO) Page Mode as a high speed access
mode. They have the package variations of standard 50-pin plastic SOJ and standerd 50-pin plastic TSOPII
od
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 50 ns/60 ns (max)
• Power dissipation
⎯ Active: 432 mW/396 mW (max) (HM5164165F Series)
: 504 mW/432 mW (max) (HM5165165F Series)
⎯ Standby : 1.8 mW (max) (CMOS interface)
: 1.1 mW (max) (L-version)
• EDO page mode capability
• Refresh cycles
⎯ RAS-only refresh
8192 cycles /64 ms (HM5164165F, HM5164165FL)
4096 cycles /64 ms (HM5165165F, HM5165165FL)
⎯ CBR/Hidden refresh
4096 cycles /64 ms (HM5164165F, HM5164165FL, HM5165165F, HM5165165FL)
t
uc
This product became EOL in December, 2006.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5164165F Series, HM5165165F Series
EO
• 4 variations of refresh
⎯ RAS-only refresh
⎯ CAS-before-RAS refresh
⎯ Hidden refresh
⎯ Self refresh (L-version)
• 2CAS-byte control
• Battery backup operation (L-version)
Ordering Information
Access time
Package
HM5164165FJ-5
HM5164165FJ-6
50 ns
60 ns
400-mil 50-pin plastic SOJ (CP-50DA)
HM5164165FLJ-5
HM5164165FLJ-6
50 ns
60 ns
HM5165165FJ-5
HM5165165FJ-6
50 ns
60 ns
HM5165165FLJ-5
HM5165165FLJ-6
50 ns
60 ns
L
Type No.
HM5164165FLTT-5
HM5164165FLTT-6
HM5165165FLTT-5
HM5165165FLTT-6
50 ns
60 ns
400-mil 50-pin plastic TSOP II (TTP-50DB)
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
od
HM5165165FTT-5
HM5165165FTT-6
Pr
HM5164165FTT-5
HM5164165FTT-6
t
uc
Data Sheet E0099H10
2
HM5164165F Series, HM5165165F Series
Pin Arrangement (HM5164165F Series)
50-pin TSOP
50-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
L
EO
Pin Description
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
A12
A11
A10
A9
A8
A7
A6
VSS
Function
Address input
— Row/Refresh address A0 to A12
— Column address
A0 to A8
I/O0 to I/O15
Data input/output
RAS
Row address strobe
UCAS, LCAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
t
uc
A0 to A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(Top view)
(Top view)
Pin name
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
Pr
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
A12
A11
A10
A9
A8
A7
A6
VSS
od
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
Data Sheet E0099H10
3
HM5164165F Series, HM5165165F Series
Pin Arrangement (HM5165165F Series)
50-pin TSOP
50-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
L
EO
Pin Description
Function
Address input
— Row/Refresh address A0 to A11
— Column address
A0 to A9
I/O0 to I/O15
Data input/output
RAS
Row address strobe
UCAS, LCAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
Data Sheet E0099H10
4
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
NC
A11
A10
A9
A8
A7
A6
VSS
t
uc
A0 to A11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(Top view)
(Top view)
Pin name
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
Pr
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
NC
A11
A10
A9
A8
A7
A6
VSS
od
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
HM5164165F Series, HM5165165F Series
Block Diagram (HM5164165F Series)
RAS
UCAS LCAS
EO
Row
address
buffers
I/O buffers
I/O0
to
I/O15
od
A9
to
A12
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
Pr
•
•
•
buffers
Row decoder
A8
address
L
to
Column decoder
Column
•
•
•
OE
Timing and control
A0
A1
WE
t
uc
Data Sheet E0099H10
5
HM5164165F Series, HM5165165F Series
Block Diagram (HM5165165F Series)
RAS
UCAS LCAS
EO
Column decoder
Column
address
Row
address
buffers
A10
I/O buffers
I/O0
to
I/O15
od
A11
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
Pr
•
•
•
buffers
Row decoder
A9
•
•
•
L
to
OE
Timing and control
A0
A1
WE
t
uc
Data Sheet E0099H10
6
HM5164165F Series, HM5165165F Series
Operation Table
LCAS
UCAS WE
OE
I/O 0 to I/O 7
I/O 8 to I/O 15 Operation
H
×
×
×
×
High-Z
High-Z
Standby
L
L
H
H
L
Dout
High-Z
Read cycle
L
H
L
H
L
High-Z
Dout
L
L
L
H
EO
RAS
L
L
L
L
H
L
L
H
Dout
Dout
L*
×
Din
×
L*
2
×
×
Din
L*
2
×
Din
Din
L*
2
H
Din
×
L*
2
H
×
Din
L
L*
2
H
Din
Din
H
H to L
L to H
Dout/Din
High-Z
L
H to L
L to H
High-Z
Dout/Din
H
L
L
H
L
L
L
L
L
2
Early write cycle
Delayed write cycle
L
L
L
L
H
L
L
L
H to L
L to H
Dout/Din
Dout/Din
L
H
H
×
×
High-Z
High-Z
RAS-only refresh cycle
H to L
H
L
H
×
High-Z
High-Z
CAS-before-RAS refresh cycle or
H to L
L
H
H
×
High-Z
High-Z
Self refresh cycle (L-version)
H to L
L
L
H
×
High-Z
High-Z
L
L
L
H
H
High-Z
High-Z
Read-modify-write cycle
Read cycle (Output disabled)
od
Pr
L
Notes: 1. H: VIH (inactive) L: VIL (active) ×: VIH or VIL
2. t WCS ≥ 0 ns: Early write cycle
t WCS < 0 ns: Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS
and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write
operation and output High-Z control are done independently by each UCAS, LCAS.
ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
t
uc
Data Sheet E0099H10
7
HM5164165F Series, HM5165165F Series
Absolute Maximum Ratings
Symbol
Value
Unit
Terminal voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
V
Power supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Storage temperature
Tstg
–55 to +125
°C
EO
Parameter
DC Operating Conditions
L
Parameter
Min
Typ
Max
Unit
Notes
VCC
3.0
3.3
3.6
V
1, 2
VSS
0
0
0
V
2
Input high voltage
VIH
2.0
—
VCC + 0.3
V
1
Input low voltage
VIL
–0.3
—
0.8
V
1
Ta
0
—
70
˚C
Supply voltage
Ambient temperature range
Pr
Symbol
Notes: 1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
od
t
uc
Data Sheet E0099H10
8
HM5164165F Series, HM5165165F Series
DC Characteristics (HM5164165F Series)
HM5164165F
-5
Symbol Min
Max
Min
Max
Unit
Test conditions
I CC1
—
120
—
110
mA
t RC = min
I CC2
—
2
—
2
mA
TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
0.5
—
0.5
mA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
I CC2
—
300
—
300
µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
120
—
110
mA
t RC = min
I CC5
—
5
—
5
mA
RAS = VIH
UCAS, LCAS = VIL
Dout = enable
I CC6
—
120
—
110
mA
t RC = min
EDO page mode current* 1, * 3
I CC7
—
120
—
110
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
Battery backup current* 4
(Standby with CBR refresh)
(L-version)
I CC10
—
Self refresh mode current
(L-version)
I CC11
—
Input leakage current
I LI
Output leakage current
EO
Parameter
-6
1,
Operating current* *
2
Standby current
L
Standby current
(L-version)
RAS-only refresh current* 2
CAS-before-RAS refresh
current
od
Pr
Standby current*
1
1.2
—
1.2
mA
CMOS interface
Dout = High-Z
CBR refresh: t RC = 15.6 µs
t RAS ≤ 0.3 µs
500
—
500
µA
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
–5
5
–5
5
I LO
–5
5
–5
5
Output high voltage
VOH
2.4
VCC
2.4
VCC
Output low voltage
VOL
0
0.4
0
0.4
0 V ≤ Vin ≤ VCC + 0.3 V
µA
0 V ≤ Vout ≤ VCC
Dout = disable
V
High Iout = –2 mA
V
Low Iout = 2 mA
t
uc
µA
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
Data Sheet E0099H10
9
HM5164165F Series, HM5165165F Series
DC Characteristics (HM5165165F Series)
HM5165165F
-5
Parameter
-6
Max
Min
Max
Unit
Test conditions
I CC1
—
140
—
120
mA
t RC = min
I CC2
—
2
—
2
mA
TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
0.5
—
0.5
mA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
I CC2
—
300
—
300
µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
140
—
120
mA
t RC = min
I CC5
—
5
—
5
mA
RAS = VIH
UCAS, LCAS = VIL
Dout = enable
I CC6
—
140
—
120
mA
t RC = min
EDO page mode current* 1, * 3
I CC7
—
120
—
110
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
Battery backup current* 4
(Standby with CBR refresh)
(L-version)
I CC10
—
Self refresh mode current
(L-version)
I CC11
—
Input leakage current
I LI
–5
Output leakage current
I LO
Output high voltage
Output low voltage
EO
Symbol Min
1,
Operating current* *
2
Standby current
L
Standby current
(L-version)
RAS-only refresh current* 2
CAS-before-RAS refresh
current
od
Pr
Standby current*
1
—
1.2
mA
CMOS interface
Dout = High-Z
CBR refresh: t RC = 15.6 µs
t RAS ≤ 0.3 µs
500
—
500
µA
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
5
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
–5
5
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
VOH
2.4
VCC
2.4
VCC
V
High Iout = –2 mA
VOL
0
0.4
0
0.4
V
Low Iout = 2 mA
t
uc
1.2
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
Data Sheet E0099H10
10
HM5164165F Series, HM5165165F Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Symbol
Min
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
—
5
pF
1
Input capacitance (Clocks)
CI2
—
—
7
pF
1
CI/O
—
—
7
pF
1, 2
EO
Parameter
Output capacitance (Data-in, Data-out)
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable Dout.
L
od
Pr
t
uc
Data Sheet E0099H10
11
HM5164165F Series, HM5165165F Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)*1, *2, *19, *26
Test Conditions
Input rise and fall time: 2 ns
Input pulse levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
EO
•
•
•
•
•
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
L
Parameter
HM5164165F/HM5165165F
-5
-6
Min
Max
Min
Max
Unit
Random read or write cycle time
t RC
84
—
104
—
ns
RAS precharge time
t RP
30
—
40
—
ns
t CP
8
—
10
—
ns
t RAS
50
10000
60
10000
ns
t CAS
8
10000
10
10000
ns
t ASR
0
—
0
—
ns
t RAH
8
—
10
—
ns
CAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
t ASC
Column address hold time
t CAH
RAS to CAS delay time
t RCD
RAS to column address delay time
t RAD
RAS hold time
t RSH
CAS hold time
t CSH
CAS to RAS precharge time
Notes
30
0
—
0
—
ns
27
8
—
10
—
ns
27
12
37
14
45
ns
3
10
25
12
30
ns
4
13
—
15
—
ns
38
—
40
—
ns
t CRP
5
—
5
—
ns
28
OE to Din delay time
t OED
13
—
15
—
ns
5
OE delay time from Din
t DZO
0
—
0
—
ns
6
CAS delay time from Din
t DZC
0
—
0
—
ns
6
Transition time (rise and fall)
tT
2
50
2
50
ns
7
Data Sheet E0099H10
12
t
uc
Column address setup time
od
Pr
Symbol
HM5164165F Series, HM5165165F Series
Read Cycle
HM5164165F/HM5165165F
-5
-6
Symbol
Min
Max
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
50
—
60
ns
8, 9
Access time from CAS
t CAC
—
13
—
15
ns
9, 10, 17
Access time from address
t AA
—
25
—
30
ns
9, 11, 17
Access time from OE
t OEA
—
13
—
15
ns
9
Read command setup time
t RCS
0
—
0
—
ns
27
Read command hold time to CAS
t RCH
0
—
0
—
ns
12, 28
Read command hold time from RAS
t RCHR
50
—
60
—
ns
Read command hold time to RAS
t RRH
0
—
0
—
ns
Column address to RAS lead time
t RAL
25
—
30
—
ns
Column address to CAS lead time
t CAL
15
—
18
—
ns
CAS to output in low-Z
t CLZ
0
—
0
—
ns
t OH
3
—
3
—
ns
Output data hold time from OE
t OHO
3
—
3
—
ns
Output buffer turn-off time
t OFF
—
13
—
15
ns
13, 21
t OEZ
—
13
—
15
ns
13
t CDD
13
—
15
—
ns
5
L
EO
Parameter
Output buffer turn-off to OE
CAS to Din delay time
Output data hold time from RAS
t OHR
Output buffer turn-off to RAS
t OFR
Output buffer turn-off to WE
t WEZ
WE to Din delay time
t WED
RAS to Din delay time
t RDD
od
Pr
Output data hold time
12
21
3
—
3
—
ns
21
—
13
—
15
ns
13, 21
—
13
—
15
ns
13
13
—
15
—
ns
13
—
15
—
ns
t
uc
Data Sheet E0099H10
13
HM5164165F Series, HM5165165F Series
Write Cycle
HM5164165F/HM5165165F
-5
-6
Symbol
Min
Max
Min
Max
Unit
Notes
Write command setup time
t WCS
0
—
0
—
ns
14, 27
Write command hold time
t WCH
8
—
10
—
ns
27
Write command pulse width
t WP
8
—
10
—
ns
Write command to RAS lead time
t RWL
13
—
15
—
ns
Write command to CAS lead time
t CWL
8
—
10
—
ns
29
Data-in setup time
t DS
0
—
0
—
ns
15, 29
Data-in hold time
t DH
8
—
10
—
ns
15, 29
Notes
L
EO
Parameter
Read-Modify-Write Cycle
Pr
HM5164165F/HM5165165F
-5
Parameter
-6
Min
Max
Min
Max
Unit
Read-modify-write cycle time
t RWC
116
—
140
—
ns
RAS to WE delay time
t RWD
67
—
79
—
ns
14
t CWD
30
—
34
—
ns
14
42
—
49
—
ns
14
13
—
15
—
ns
CAS to WE delay time
Column address to WE delay time
t AWD
OE hold time from WE
t OEH
Refresh Cycle
od
Symbol
-5
t
uc
HM5164165F/HM5165165F
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
CAS setup time (CBR refresh cycle)
t CSR
5
—
5
—
ns
27
CAS hold time (CBR refresh cycle)
t CHR
8
—
10
—
ns
28
WE setup time (CBR refresh cycle)
t WRP
0
—
0
—
ns
WE hold time (CBR refresh cycle)
t WRH
8
—
10
—
ns
RAS precharge to CAS hold time
t RPC
5
—
5
—
ns
Data Sheet E0099H10
14
27
HM5164165F Series, HM5165165F Series
EDO Page Mode Cycle
HM5164165F/HM5165165F
-5
-6
Symbol
Min
Max
Min
Max
Unit
Notes
EDO page mode cycle time
t HPC
20
—
25
—
ns
20
EDO page mode RAS pulse width
t RASP
—
100000 —
100000 ns
16
Access time from CAS precharge
t CPA
—
28
—
35
ns
9, 17, 28
RAS hold time from CAS precharge
t CPRH
28
—
35
—
ns
Output data hold time from CAS low
t DOH
3
—
3
—
ns
CAS hold time referred OE
t COL
8
—
10
—
ns
CAS to OE setup time
t COP
5
—
5
—
ns
Read command hold time from
CAS precharge
t RCHC
28
—
35
—
ns
Write pulse width during CAS precharge t WPE
8
—
10
—
ns
OE precharge time
8
—
10
—
ns
L
EO
Parameter
t OEP
9, 22
Pr
EDO Page Mode Read-Modify-Write Cycle
HM5164165F/HM5165165F
-5
Symbol
EDO page mode read-modify-write cycle t HPRWC
time
WE delay time from CAS precharge
od
Parameter
t CPW
Min
Max
Min
Max
Unit
57
—
68
—
ns
45
—
54
—
ns
Parameter
Symbol
Max
Refresh period
t REF
64
Notes
14, 28
t
uc
Refresh (HM5164165F Series)
-6
Unit
Note
ms
8192 cycles
Data Sheet E0099H10
15
HM5164165F Series, HM5165165F Series
Refresh (HM5165165F Series)
Parameter
Symbol
Max
Unit
Note
Refresh period
t REF
64
ms
4096 cycles
EO
Self Refresh Mode (L-version)
HM5164165FL/HM5165165FL
-5
-6
Symbol
Min
Max
Min
Max
Unit
Notes
RAS pulse width (self refresh)
t RASS
100
—
100
—
µs
25
RAS precharge time (self refresh)
t RPS
90
—
110
—
ns
25
CAS hold time (self refresh)
t CHS
–50
—
–50
—
ns
29
L
Parameter
od
Pr
Notes: 1. AC measurements assume t T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a
reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is
controlled exclusively by t CAC .
4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a
reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled
exclusively by t AA .
5. Either t OED or t CDD must be satisfied.
6. Either t DZO or t DZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times
are measured between VIH (min) and VIL (max).
8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max).
11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max).
12. Either t RCH or t RRH must be satisfied for a read cycles.
13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data
out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥
t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a
read-modify-write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
15. t DS and t DH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge
in delayed write or read-modify-write cycles.
t
uc
Data Sheet E0099H10
16
HM5164165F Series, HM5165165F Series
L
EO
16. t RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t AA , t CAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line
noise, which causes to degrade VIH min/VIL max level.
20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode
mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified
t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode
mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time
and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between t OHR and t OH , and between t OFR and t OFF.
22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after
self refresh mode according as note 23.
25 At t RASS > 100 µs, self refresh mode is activated, and not activated at t RASS < 10 µs. It is undefined within
the range of 10 µs ≤ t RASS ≤ 100 µs. For t RASS ≥ 10 µs, it is necessary to satisfy t RPS.
26. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
27. t ASC, t CAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS.
28. t CRP , t CHR, t RCH, t CPA and t CPW are determined by the later rising edge of UCAS or LCAS.
29. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS.
30. t CP is determined by the time that both UCAS and LCAS are high.
31. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
od
Pr
t
uc
Data Sheet E0099H10
17
HM5164165F Series, HM5165165F Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS
are allowed under the following conditions.
EO
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
L
LCAS
Pr
WE
Early write
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, EDO page mode can be performed.
UCAS
LCAS
od
RAS
t
uc
t UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
Data Sheet E0099H10
18
HM5164165F Series, HM5165165F Series
Timing Waveforms*31
Read Cycle
EO
tRC
tRAS
tRP
RAS
tCSH
tT
tASR
tRAD
tRAH
tRAL
tCAL
tASC
tCAH
Pr
Address
tRSH
tCAS
L
UCAS
LCAS
tCRP
tRCD
Column
Row
tRRH
tRCHR
tRCS
od
WE
tRCH
tDZC
tCDD
tWED
tRDD
High-Z
tDZO
tOEA
OE
tCAC
tAA
tRAC
tCLZ
t
uc
;
Din
tOED
tOEZ
tOHO
tOFF
tOH
tOFR
tOHR
tWEZ
Dout
Dout
Data Sheet E0099H10
19
HM5164165F Series, HM5165165F Series
Early Write Cycle
tRC
tRAS
tRP
EO
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
L
UCAS
LCAS
tASR
tASC
tCAH
Pr
Address
tRAH
Row
Column
tWCS
tDS
tDH
Din
High-Z*
Dout
t
uc
Din
od
WE
tWCH
* t WCS
Data Sheet E0099H10
20
t WCS (min)
HM5164165F Series, HM5165165F Series
Delayed Write Cycle*18
tRC
tRAS
tRP
EO
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
L
UCAS
LCAS
tRAH
tASR
Address
tASC
Row
tCAH
Column
Pr
tRCS
WE
High-Z
tDS
tDH
Din
tOED
tDZO
tOEH
tOEP
OE
tOEZ
tCLZ
t
uc
;
Din
tRWL
tWP
od
tDZC
tCWL
High-Z
Dout
Invalid Dout
Data Sheet E0099H10
21
HM5164165F Series, HM5165165F Series
Read-Modify-Write Cycle*18
tRWC
tRAS
tRP
EO
RAS
tT
tRCD
L
UCAS
LCAS
tASR
Address
tCAS
tCRP
tRAD
tASC
tRAH
Row
tCAH
Column
Pr
tCWL
tCWD
tRCS
tRWL
tWP
tAWD
tRWD
WE
od
tDZC
tDH
tDS
High-Z
Din
;
Din
tOED
tOEH
tOEA
tOEP
OE
tCAC
tAA
tOEZ
tRAC
tOHO
Dout
Dout
tCLZ
Data Sheet E0099H10
22
t
uc
tDZO
High-Z
HM5164165F Series, HM5165165F Series
RAS-Only Refresh Cycle
tRC
tRAS
EO
tRP
RAS
tT
tRPC
tCRP
tCRP
UCAS
LCAS
L
Address
tASR
tRAH
Row
tOFR
High-Z
od
t
uc
;
Dout
Pr
tOFF
Data Sheet E0099H10
23
HM5164165F Series, HM5165165F Series
CAS-Before-RAS Refresh Cycle
tRC
tRP
tRC
tRP
EO
tRAS
tRAS
tRP
RAS
tT
tRPC
tCP
tRPC
tCSR
tCHR
tCP
tCRP
tCSR
tCHR
UCAS
L
LCAS
tWRP
tWRH
tWRP
tWRH
WE
Pr
Address
tOFR
od
tOFF
High-Z
Data Sheet E0099H10
24
t
uc
;
Dout
HM5164165F Series, HM5165165F Series
Hidden Refresh Cycle
tRC
tRAS
tRP
tRC
tRAS
tRC
tRP
tRAS
tRP
EO
RAS
tT
tRSH
tCHR
tCRP
tRCD
UCAS
LCAS
tRAL
L
tRAD
tASR
Address
tRAH
tASC
Row
tCAH
Column
Pr
tRRH
tRCS
WE
tWED
od
tDZC
tRCH
tCDD
tRDD
High-Z
Din
tDZO
OE
tCAC
tAA
tRAC
t
uc
tOEA
tOED
tOFF
;
tCLZ
tOEZ
tWEZ
tOHO
tOH
Dout
Dout
tOFR
tOHR
Data Sheet E0099H10
25
HM5164165F Series, HM5165165F Series
EDO Page Mode Read Cycle
t RP
t HPC
t RASP
EO
RAS
tT
t CSH
t CP
t HPC
t CAS
UCAS
LCAS
t HPC
t CPRH
t CP
t
t CRP
RSH
t CAS
tCAS
tCAS
t RCHC
t RCHR
t RCS
t CP
t RRH
t RCH
t RCH t RCS
WE
Address
tRAH tASC
tCAH
L
tASR
Row
Column 1
t WPE
t ASC t CAH
t ASC t CAH
Column 2
Column 3
t CAL
t CAL
t RAL
t CAH
tASC
t WED
Column 4
t CAL
t CAL
tRDD
tCDD
tDZC
Pr
High-Z
Din
tCOL
tOEP
tCOP
tOED
tOEP
;
tDZO
OE
tAA
tCAC
tCAC
tAA
tWEZ
tRAC
Dout
tCPA
tAA
tCAC
tOEZ
tOHO
tOEZ
tOEA
tDOH
Dout 1
Dout 2
tOFR
tOHR
tOEZ
tCPA
od
tCPA
tOEA
Dout 2
tOHO
Dout 3
tAA
tCAC
tOHO
tOFF
tOH
tOEA
Dout 4
t
uc
Data Sheet E0099H10
26
HM5164165F Series, HM5165165F Series
EDO Page Mode Read Cycle (2CAS control)
t RP
t RASP
EO
RAS
tT
t CSH
t HPC
t CP
t CAS
LCAS
tHPC
t CP
t HPC
t CP
t CRP
tRSH
t CAS
tCAS
UCAS
t CAS
t RCHC
t RRH
t RCH
WE
L
t RCS
tASR
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
Pr
Address
tRAH tASC
t CAL
tDZC
t CAL
t RAL
t CAH
tASC
t WED
Column 4
t CAL
tRDD
t CAL
tCDD
High-Z
Din
tCOL
tCOP
od
tDZO
tOEP
OE
tOEA
tOFR
tOHR
tOEZ
tCPA
tCPA
tAA
tCAC
tOEZ
tOEZ
tOHO
tAA
;
tCAC
tAA
tOED
tOEP
tDOH
L Dout
tOHO
tOFF
tOH
tOHO
Dout 1
Dout 2
Dout 2
tCPA
tAA
tCAC
U Dout
tCAC
t
uc
tRAC
tOEA
Dout 1
Dout 4
tOEA
Dout 3
Dout 4
Data Sheet E0099H10
27
HM5164165F Series, HM5165165F Series
EDO Page Mode Early Write Cycle
tRP
tRASP
EO
RAS
tT
tCSH
tHPC
tCAS
tRCD
tCP
tRSH
tCAS
tCP
tCAS
tCRP
UCAS
LCAS
L
tASR
Address
Row
tRAH
tASC
Column 1
Column 2
tWCH
tDH
Din 1
tWCS
tWCH
tASC
tCAH
Column N
tWCS
tWCH
tDS
tDH
Din 2
High-Z*
tDS
tDH
Din N
t
uc
Dout
tCAH
od
tDS
Din
tASC
Pr
tWCS
WE
tCAH
* t WCS
Data Sheet E0099H10
28
t WCS (min)
HM5164165F Series, HM5165165F Series
EDO Page Mode Delayed Write Cycle*18
tRASP
EO
tRP
RAS
tT
tCP
tRCD
tCRP
tCP
tCSH
tHPC
tCAS
tCAS
tRSH
tCAS
UCAS
LCAS
L
tRAD
tASR
tASC
tCAH
tASC
tCAH
Column 1
Column 2
tRAH
Address
Row
tASC
tCAH
tWP
tDZC tDS
tRCS
Din
1
tDZO tOED
tDH
Din
2
tDZO
tOED
tOEP
tOEH
tDZO
tDH
Din
N
tOED
tOEP
tOEH
t
uc
;
tOEP
tOEH
tWP
tDZC tDS
od
tWP
tDZC tDS
tDH
Din
tCWL
tRWL
tRCS
tRCS
WE
tCWL
Pr
tCWL
Column N
OE
tCLZ
tCLZ
tOEZ
tCLZ
tOEZ
Dout
Invalid Dout
Invalid Dout
tOEZ
High-Z
Invalid Dout
Data Sheet E0099H10
29
HM5164165F Series, HM5165165F Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP
EO
t RP
RAS
tT
t HPRWC
t CP
t RCD
t RSH
t CP
t CAS
t CAS
t CRP
t CAS
UCAS
LCAS
L
t RAD
t ASR
Address
t ASC
t RAH
Row
t ASC
t CAH
t CAH
Column 1
Column 2
t CWL
Column N
t CPW
t CWL
Pr
t RWD
t AWD
t RCS
t WP
od
t OED
t DZC t DS
t DH
Din
2
t OED
t DZO
t OEP
t OEH
t DH
Din
N
t OED
t DZO
t OEP
t OEH
OE
t OHO
t OEA
t CAC
t OHO
t OEA
t CAC
t AA
t OEZ
t CLZ
t OHO
t OEA
t CAC
t AA
t CPA
t RAC
t
uc
;
t OEP
t OEH
t RWL
t CWD
t WP
Din
1
t CWL
t AWD
t RCS
t DZC t DS
t DH
t DZO
t CWD
t WP
t DZC t DS
Din
t CPW
t AWD
t RCS
t CWD
WE
t ASC
t CAH
t AA
t CPA
t OEZ
t CLZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Data Sheet E0099H10
30
Dout N
HM5164165F Series, HM5165165F Series
EDO Page Mode Mix Cycle (1) *20
t RP
t RASP
EO
RAS
tT
UCAS
LCAS
t CAS
t CRP
t CP
t CP
t CP
t CAS
tCAS
t CSH
tCAS
tCWL
tRSH
t RCD
t WCS
tCPW
tAWD
WE
L
t ASC
tRAH
tASR
Address
Row
tASC t CAH
Column 2
Column 3
tASC
t RAL
t CAH
Column 4
t CAL
tRDD
tCDD
t CAL
t DH
Din 1
tWP
t DH
t DS
High-Z
Din 3
tOED
;
Din
Column 1
t ASC t CAH
Pr
t DS
tCAH
t RRH
t RCH
t RCS
t RCS
t WCH
OE
tCPA
tAA
tOEA
tAA
tCAC
Dout
tWED
t DOH
Dout 2
tOFR
tWEZ
tCPA
od
tCPA
tOEP
t OEZ
tCAC t OHO
Dout 3
tAA
tOEZ
tCAC
tOHO
tOEA
tOFF
tOH
Dout 4
t
uc
Data Sheet E0099H10
31
HM5164165F Series, HM5165165F Series
EDO Page Mode Mix Cycle (2)* 20
t RP
t RASP
RAS
EO
CAS
tT
UCAS
LCAS
t CSH
t CAS
t RCD
t CAS
tCAS
t RCHR
t RCS
t RCH
tWCS t WCH
tCWL
t ASC
tRAH
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
tRSH
t RCS
t RRH
t RCH
tWP
tCPW
L
Address
tCAS
t RCS
WE
tASR
t CRP
t CP
t CP
t CP
t RAL
t CAH
tASC
Column 4
t CAL
t CAL
t DS
t DH
Pr
t DS
High-Z
Din
Din 2
Din 3
t OEP
t OEP
tOED
tOED
tCOP
tWED
tCOL
OE
t OEA
tOEA
tCAC
tOEZ
tCPA
tAA
tCAC
tRAC
t OHO
Dout 1
tOFR
tWEZ
tCPA
od
tAA
Dout
tRDD
tCDD
t DH
tOEZ
t OHO
Dout 3
tAA
tCAC
tOEZ
tOEA
tOFF
tOH
tOHO
Dout 4
t
uc
Data Sheet E0099H10
32
HM5164165F Series, HM5165165F Series
Self Refresh Cycle (L-version)* 23, 24, 25
tRASS
tRP
tRPS
EO
RAS
tT
;
;
tRPC
tCP
tCRP
tCHS
tCSR
UCAS
LCAS
L
tWRP
tWRH
WE
;
Pr
tOFR
tOFF
Dout
High-Z
od
t
uc
Data Sheet E0099H10
33
HM5164165F Series, HM5165165F Series
Package Dimensions
HM5164165FJ/FLJ Series
HM5165165FJ/FLJ Series (CP-50DA)
20.95
21.38 Max
3.50 ± 0.26
Pr
1.09 Max
0.80
*0.32 ± 0.08
0.30 ± 0.04
2.55 ± 0.12
25
0.47
0.90 ± 0.26
1
11.18 ± 0.13
26
10.16 ± 0.13
50
L
EO
Unit: mm
9.40 ± 0.25
0.10
CP-50DA
Conforms
—
1.2 g
od
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
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Data Sheet E0099H10
34
HM5164165F Series, HM5165165F Series
HM5164165FTT/FLTT Series
HM5165165FTT/FLTT Series (TTP-50DB)
Unit: mm
EO
20.95
21.35 Max
26
10.16
50
1
25
L
0.80
0.10
*0.30 +– 0.05
0.28 ± 0.05
0.13 M
0.80
11.76 ± 0.20
1.15 Max
0.10
*Dimension including the plating thickness
Base material dimension
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
0.68
0.13 ± 0.05
*0.145 ± 0.05
0.125 ± 0.04
Pr
1.20 Max
0° – 5°
TTP-50DB
—
—
0.51 g
od
t
uc
Data Sheet E0099H10
35
HM5164165F Series, HM5165165F Series
Cautions
L
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third
party’s patent, copyright, trademark, or other intellectual property rights for information contained in this
document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights,
including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when
used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other
consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
od
Pr
t
uc
Data Sheet E0099H10
36
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