NXP CBTL05023 Multiplexer/demultiplexer switch for thunderbolt application Datasheet

CBTL05023
Multiplexer/demultiplexer switch for Thunderbolt applications
Rev. 2 — 15 August 2012
Product brief
1. General description
The CBTL05023 is a multiplexer/demultiplexer switch chip for DisplayPort v1.2 signals
and the control signals of a 10 Gbit/s channel. The 10 Gbit/s channel does not pass
through this switch. This chip provides BIASOUT output control signal, and the
DC-biasing pull-down resistors to facilitate an external 10 Gbit/s channel.
The AUX MUX is a 2 : 1 switch with CA_DETect pin selecting between AUX and DDC
(Direct Display Control) signals.
The DP MUX is a 2 : 1 switch that selects between DPML (DisplayPort Main Link) and
LSTX/LSRX signals.
This chip also includes three control signal buffers: HPDOUT, CA_DETOUT and
BIASOUT.
CBTL05023 is powered by a 3.3 V supply and it is available in 3 mm × 3 mm HVQFN24
package with 0.4 mm pitch.
2. Features and benefits
2.1 AUX MUX 2 : 1 switch
 This 2 : 1 switch is controlled by CA_DET signal multiplexing of the 1 Mbit/s
differential AUX and DDC (Direct Display Control) signals
 When CA_DET is HIGH, DDC path is selected
 Differential AUX channel:
 Low insertion loss: −0.5 dB at 5 MHz
 Low return loss: −19 dB at 5 MHz
 Low ON-state resistance: 7.5 Ω
 Bandwidth: 5 GHz
 Low off-state isolation: −75 dB at 5 MHz
 Low crosstalk: −40 dB at 5 MHz
 Common-mode input voltage VIC: 0 V to 3.3 V
 Differential input voltage VID: 1.4 V (maximum)
 DDC channel has DDC_CLK and DDC_DAT I2C signals
 100 kHz 3.3 V voltage swing
 Both AUXIO+ and AUXIO− outputs have 900 Ω (±20 %) pull-down resistor that is
enabled by the status of the BIASOUT output pin
 These pull-down resistors provide DC bias for the 10 Gbit/s channel
CBTL05023
NXP Semiconductors
Multiplexer/de-multiplexer switch for Thunderbolt applications
2.2 DP MUX 2 : 1 switch
The DP MUX is a 2:1 switch that is controlled by DP_PD pin multiplexing of a differential
DPML signal and LSTX/LSRX signals
 The DPML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s
 The low speed DC coupled signals LSTX and LSRX are 3.3 V single-ended signals
that operated at 1 Mbit/s
 5.4 Gbit/s DPML channel:
 Low insertion loss for DP-DPMLO path: −2.0 dB at 2.5 GHz
 Low insertion loss for LS-DPMLO path: −2.0 dB at 2.5 GHz
 Low return loss for DP-DPMLO path: −15 dB at 2.5 GHz
 Low return loss for LS-DPMLO path: −14 dB at 2.5 GHz
 Low ON-state resistance for DP-DPMLO path: 9 Ω
 Low ON-state resistance for LS-DPMLO path: 13 Ω
 High bandwidth: 7 GHz
 Low off-state isolation: −20 dB at 2.5 GHz
 Low crosstalk: −25 dB at 2.5 GHz
 Common-mode input voltage VIC: 0 V to 3.3 V
 Differential input voltage VID: 1.4 V (maximum)
2.3 General
 The input of the HPDOUT (Hug Plug Detect output) buffer is 5 V tolerant
 HPDOUT, CA_DETOUT and BIASOUT buffers
 CA_DET input leakage current < 0.1 μA to prevent driving the 1 MΩ pull-down to a
HIGH level
 BIASOUT buffer is able to provide enough current to drive the bias circuit for the
PIN diode path
 BIASOUT buffer can drive up to six sets of bias circuits for the 10 Gbit/s paths
 When AUXIO_EN is LOW or (BIASIN = 0 and DP_PD = 1), this chip is in Sleep mode
 AUXIO+ and AUXIO− of AUX MUX are disabled
 CA_DETOUT and HPDOUT buffers are on
 When the chip is in Sleep mode, CBTL05023 will consume < 3.5 mW
 Patent-pending high-bandwidth analog pass-gate technology
 Very low intra-pair differential skew (5 ps typical)
 All channels have back current protection
 All channels support rail-to-rail input voltage
 CMOS input buffer with hysteresis
 Single 3.3 V ± 10 % power supply
 HVQFN24 3 mm × 3 mm package, 0.4 mm pitch, with exposed center pad for thermal
relief and electrical ground
 ESD: 2500 V HBM, 1250 V CDM
 Operating temperature range: 0 °C to 85 °C
CBTL05023
Product brief
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
2 of 4
CBTL05023
NXP Semiconductors
Multiplexer/de-multiplexer switch for Thunderbolt applications
3. Ordering information
Table 1.
Ordering information
Type number
CBTL05023BS
[1]
Package
Name
Description
Version
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 × 3 × 0.85 mm[1]
SOT905-1
Maximum package height is 1 mm.
4. Pinning information
CA_DET
18
19 DPMLO+
20 DPMLO−
21 GND
22 AUXIO+
23 AUXIO−
terminal 1
index area
24
BIASOUT
4.1 Pinning
17 HPD
BIASIN 1
AUXIO_EN 2
16 CA_DETOUT
CBTL05023BS
VDD 3
15 VDD
Transparent top view
12
HPDOUT
DP+ 11
DP− 10
DP_PD
GND 9
13 LSRX
AUX+ 8
DDC_CLK 5
AUX− 7
14 LSTX
6
DDC_DAT 4
002aag230
Center pad is connected to printed-circuit board ground plane for electrical grounding and
thermal relief.
Fig 1.
CBTL05023
Product brief
Pin configuration for HVQFN24
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
3 of 4
CBTL05023
NXP Semiconductors
Multiplexer/de-multiplexer switch for Thunderbolt applications
5. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 x 3 x 0.85 mm
B
D
SOT905-1
A
terminal 1
index area
A
E
A1
c
detail X
C
e1
e
b1
b
7
6
v
w
11
M
y
y1 C
C A B
C
M
12
L
13
5
e
b1 e2
Eh
17
1
LC
terminal 1
index area
24
23
19
18
Dh
X
L1
LC
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
b1
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
L1
LC
v
w
y
y1
mm
1
0.05
0.00
0.25
0.15
0.45
0.35
0.2
3.1
2.9
2.05
1.75
3.1
2.9
2.05
1.75
0.4
1.8
1.8
0.35
0.15
0.1
0.0
0.3
0.2
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
Fig 2.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT905-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
06-03-13
06-03-31
Package outline SOT905-1 (HVQFN24)
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 August 2012
Document identifier: CBTL05023
CBTL05023
Product brief
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
4 of 4
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