ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER General Description Features The ICS83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS83948I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. • • Twelve LVCMOS/LVTTL outputs • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • • • • • • Maximum output frequency: 250MHz ICS The ICS83948I is characterized at full 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS83948I ideal for those clock distribution applications demanding well defined performance and repeatability. Block Diagram Output skew: 350ps (maximum) Part-to-part skew: 1.5ns (maximum) 3.3V core, 3.3V output -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages LVCMOS_CLK Pullup CLK Pullup nCLK Pulldown CLK_SEL Q3 VDDO Q2 GND Q Q1 D VDDO GND Pin Assignment Q0 CLK_EN Pullup Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input 32 31 30 29 28 27 26 25 1 CLK_SEL 1 24 GND LVCMOS_CLK 2 23 Q4 Q1 CLK 3 22 VDDO Q2 nCLK 4 21 Q5 CLK_EN 5 20 GND OE 6 19 Q6 Q4 VDD 7 18 VDDO Q5 GND 8 17 Q7 Q0 0 Pullup GND Q8 VDDO Q9 Q10 GND Q7 10 11 12 13 14 15 16 VDDO Q6 9 Q11 Q3 ICS83948I Q8 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q9 Q10 Q11 OE Pullup IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 1 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1 CLK_SEL Input Pullup Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. 2 LVCMOS_CLK Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK Input Pullup Non-inverting differential clock input. 4 nCLK Input Pulldown 5 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. 6 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 7 VDD Power Positive supply pin. 8, 12, 16, 20, 24, 28, 32 GND Power Power supply ground. 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 10, 14, 18, 22, 26, 30 VDDO Power Output supply pins. Inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k 51 k RPULLDOWN Input Pulldown Resistor Minimum Typical Maximum Units CPD Power Dissipation Capacitance (per output) 25 pF ROUT Output Impedance 7 Function Tables Table 3A. Clock Select Function Table Control Input Clock CLK_SEL CLK/nCLK LVCMOS_CLK 0 Selected De-selected 1 De-selected Selected IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 2 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 3B. Clock Input Function Table Inputs Outputs CLK_SEL LVCMOS_CLK CLK nCLK Q[0:11] Input to Output Mode Polarity 0 – 0 1 LOW Differential to Single-Ended Non-Inverting 0 – 1 0 HIGH Differential to Single-Ended Non-Inverting 0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting 0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting 0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting 0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting 1 0 – – LOW Single-Ended to Single-Ended Non-Inverting 1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Power Supply Current 55 mA IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Test Conditions 3 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 4B. DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V Input Low Voltage -0.3 0.8 V VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V IIN Input Current ±100 µA VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOL = 20mA 2.5 V 0.4 V Maximum Units 250 MHz NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Parameter Symbol fMAX Output Frequency tPD Propagation Delay Test Conditions Minimum Typical CLK/nCLK; NOTE 1A ƒ 150MHz 2.25 3.75 ns LVCMOS_CLK; NOTE 1B ƒ 150MHz 2 4 ns 350 ps tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part Skew; NOTE 3, 6 tR / tF Output Rise/Fall Time tPW Output Pulse Width CLK/nCLK LVCMOS_CLK Measured on Rising Edge @ VDDO/2 Measured on Rising Edge @ VDDO/2 1.5 ns 2 ns 0.8V to 2V 0.2 1.0 ns ƒ < 150MHz tCycle/2 - 800 tCycle/2 + 800 ps tPZL, tPZH Output Enable Time; NOTE 4 11 ns tPLZ, tPHZ Output Disable Time; NOTE 4 11 ns tS Clock Enable Setup Time; NOTE 5 tH Clock Enable Hold Time; NOTE 5 CLK_EN to CLK/nCLK 1 ns CLK_EN to LVCMOS_CLK 0 ns CLK/nCLK to CLK_EN 1 ns LVCMOS_CLK to CLK_EN 1 ns NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 1B: Measured from VDD/2 or crosspoint of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Setup and Hold times are relative to the rising edge of the input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 4 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 1.65V±0.15V VDD SCOPE VDD, VDDO nCLK V Qx Cross Points PP V CMR CLK GND GND -1.65V±0.15V 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Differential Input Level Part 1 V V DDO DDO Qx Qx 2 2 Part 2 V V DDO DDO Qy Qy 2 tsk(pp) Part-to-Part Skew 2 tsk(o) Output Skew 2V 2V VDDO VDDO VDDO 2 2 2 Q0:Q11 0.8V 0.8V Q0:Q11 t PW tR t PERIOD tF odc = Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR t PW t PERIOD Output Pulse Width 5 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued VDD 2 LVCMOS_C nCLK CLK VDDO 2 Q0:Q11 t PD ➤ ➤ Propagation Delay IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 6 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVCMOS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVCMOS output can be left floating. There should be no trace attached. CLK Input For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 7 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver Differential Input LVPECL R2 50Ω R1 50Ω R2 50Ω R2 50Ω Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V R4 125Ω 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK Differential Input LVPECL R1 84Ω R2 84Ω Receiver Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V nCLK Zo = 50Ω LVDS 2.5V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 8 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Reliability Information Table 6. JA vs. Air Flow Table for a 32 Lead LQFP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W Transistor Count The transistor count for ICS83948I is: 1040 Pin compatible with the MPC948/948L IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 9 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 7. Package Dimensions for 32 Lead LQFP JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 10 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number ICS83948AYILF ICS83948AYILFT Marking ICS83948AYIL ICS83948AYI Package “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 11 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev Table Page T5 4 B B B B T5 4 T5 4 T5 4 Description of Change Date AC Characteristics table - tLZ, tHZ row changed symbol to read tPLZ, tPHZ and changed Parameter to read Output Enable Time. Added rows: tS ""Clock Enable Setup Time"" and tH ""Clock Enable Hold Time"". 5/20/02 AC Characteristics table, tS and tH rows - replaced SYNC_OE with CLK_EN. Added an extra note to Propagation Delay row. 6/26/02 AC Characteristics table, fMAX row corrected typo error of 150MHz to 250MHz. 8/8/02 AC Characteristics table - tPW row, added f< 150MHz for tPW Test Conditions. 11/11/02 Features Section - added Lead-Free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Added Recommendations for Unused Output Pins. Ordering Information Table - added Lead-Free part number, marking and note. 12/15/05 T8 1 2 6 9 C T8 8 11 Added Differential Clock Input Interface Section. Ordering Information Table - corrected Temperature column. Updated datasheet format. C T8 11 Removed leaded orderable parts from Ordering Information table T2 C IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 12 3/6/08 11/14/12 ICS83948AYI REV. C NOVEMBER 14, 2012 ICS83948I LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. 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