Cypress CY7C135-55JI 4k x 8 dual-port static ram and 4k x 8 dual-port sram with semaphore Datasheet

CY7C135
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port
SRAM with Semaphores
Features
Functional Description
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 4K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Semaphores included on the 7C1342 to permit software
handshaking between ports
• Available in 52-pin PLCC
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8
dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any
location in memory. Application areas include interprocessor/multiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). The
CY7C135 is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore,
the user must be aware that simultaneous access to a location
is possible. Semaphores are offered on the CY7C1342 to assist in arbitrating between ports. The semaphore logic is comprised of eight shared latches. Only one side can control the
latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a
chip enable (CE) pin or SEM pin (CY7C1342 only).
The CY7C135 and CY7C1342 are available in 52-pin PLCC.
Logic Block Diagram
R/WL
R/WR
CEL
OEL
CER
OER
I/O7L
I/O
CONTROL
I/O0L
I/O7R
I/O
CONTROL
I/O0R
A11L
A11R
ADDRESS
DECODER
A0L
ADDRESS
DECODER
MEMORY
ARRAY
SEMAPHORE
ARBITRATION
(7C1342 only)
CEL
A0R
CER
OEL
OER
R/WL
R/WR
(7C1342 only)
(7C1342 only) SEM
R
Cypress Semiconductor Corporation
Document #: 38-06038 Rev. *B
1342–1
SEM
L
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 22, 2004
CY7C135
CY7C1342
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Maximum Standby
Commercial
Current for ISB1(mA)
7C135–15
7C1342–15
15
220
7C135–20
7C1342–20
20
190
7C135–25
7C1342–25
25
180
7C135–35
7C1342–35
35
160
7C135–55
7C1342–55
55
160
60
50
40
30
30
Pin Configurations
CER
R/WR
N/C
A11R
A10R
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C135
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
NC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O 4L
I/O 5L
I/O 6L
I/O 7L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
A11L
N/C
R/W
L
CEL
VCC
A0L
OEL
A10L
PLCC
Top View
1342–3
CER
R/WR
SEMR
A11R
A10R
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C1342
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
NC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O 4L
I/O 5L
I/O 6L
I/O 7L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
SEM L
R/W
L
CEL
VCC
A0L
OEL
A10L
A11L
PLCC
Top View
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
1342–4
Pin Definitions
Left Port
Right Port
Description
A0L–11L
CEL
OEL
R/WL
SEML
(CY7C1342 only)
A0R–11R
CER
OER
R/WR
SEMR
(CY7C1342 only)
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The
three least significant bits of the address lines will determine which semaphore to write
or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested
by writing a 0 into the respective location.
Document #: 38-06038 Rev. *B
Page 2 of 12
CY7C135
CY7C1342
Maximum Ratings[1]
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch-Up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied..............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ............................................ –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................ –0.5V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
DC Input Voltage[2]......................................... –3.0V to +7.0V
Electrical Characteristics Over the Operating Range[4]
7C135–15
7C1342–1
5
Parameter
Description
Test Conditions
Min.
Max
.
7C135–25
7C1342–25
Min
.
Min.
Max
.
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND ≤ VI ≤ VCC
–10
+10
–10
+10
–10
+10
µA
IOZ
Output Leakage Current
Outputs Disabled,
GND ≤ VO ≤ VCC
–10
+10
–10
+10
–10
+10
µA
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
180
mA
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
f = fMAX[5]
Com’l
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH,
f = fMAX[5]
Com’l
ISB3
ISB4
0.4
2.2
0.4
2.2
0.8
220
190
Com’l
60
50
V
40
mA
50
130
120
110
mA
120
15
15
Ind.
Ind.
V
190
Ind.
Standby Current
(One Port CMOS Level)
0.4
0.8
Ind.
Com’l
V
2.2
Ind.
Standby Current
Both Ports CE and CER ≥
(Both Ports CMOS Levels) VCC – 0.2V,
VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[5]
One Port CEL or
CER ≥ VCC – 0.2V,
VIN ≥VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f =
fMAX[5]
2.4
Uni
t
Output HIGH Voltage
ISB2
2.4
Max
.
VOH
ISB1
2.4
7C135–20
7C1342–2
0
15
mA
30
125
115
100
mA
115
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Pulse width < 20 ns.
3. TA is the “instant on” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document #: 38-06038 Rev. *B
Page 3 of 12
CY7C135
CY7C1342
Electrical Characteristics Over the Operating Range[4](continued)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
7C135–35
7C1342–35
7C135–55
7C1342–55
Min.
Min.
Max.
2.4
2.2
Input LOW Voltage
IIX
Input Load Current
GND ≤ VI ≤ VCC
–10
+10
IOZ
Output Leakage Current
Outputs Disabled, GND ≤ VO ≤ VCC
–10
+10
ICC
Operating Current
VCC = Max., IOUT = 0 mA
Com’l
VCC = Max., IOUT = 0 mA
Ind.
ISB2
0.8
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH, f = fMAX[5]
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH, f = fMAX[5]
Standby Current
Both Ports CE and CER ≥ VCC – 0.2V,
(Both Ports CMOS Levels) VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[5]
ISB3
ISB4
Standby Current
(One Port CMOS Level)
One Port CEL or CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = fMAX[5]
V
0.4
V
2.2
VIL
ISB1
Unit
2.4
0.4
VIH
Max.
V
0.8
V
–10
+10
µA
–10
+10
µA
160
160
mA
180
180
Com’l
30
30
Ind.
40
40
Com’l
100
100
Ind.
110
110
Com’l
15
15
Ind.
30
30
Com’l
90
90
Ind.
100
100
mA
mA
mA
mA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
AC Test Loads and Waveforms
5V
R1= 893Ω
OUTPUT
C= 30pF
RTH = 250Ω
RTH = 250Ω
OUTPUT
OUTPUT
C = 5 pF
C= 30pF
R1= 347Ω
VX
VTH = 1.4V
(b) Thévenin Equivalent (Load 1)
(a) Normal Load (Load 1)
1342–5
(c) Three-State Delay (Load 3)
1342–6
1342–7
ALL INPUT PULSES
3.0V
GND
10%
90%
≤ 3 ns
90%
10%
≤ 3 ns
1342–8
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06038 Rev. *B
Page 4 of 12
CY7C135
CY7C1342
Switching Characteristics Over the Operating Range[7, 8]
Parameter
Description
7C135–15
7C1342–15
7C135–20
7C1342–20
7C135–25
7C1342–25
7C135–35
7C1342–35
7C135–55
7C1342–55
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
15
tOHA
Output Hold From
Address Change
tACE
CE LOW to Data Valid
15
20
25
35
55
ns
tDOE
OE LOW to Data Valid
10
13
15
20
25
ns
tLZOE[9,10,11]
tHZOE[9,10,11]
tLZCE[9,10,11]
tHZCE[9,10,11]
tPU[11]
tPD[11]
OE Low to Low Z
3
3
CE LOW to Power Up
3
0
CE HIGH to Power Down
3
0
15
3
0
20
3
0
25
ns
25
20
ns
ns
25
0
35
ns
ns
3
20
15
ns
55
3
3
15
13
55
35
3
3
13
10
35
25
3
3
10
CE HIGH to High Z
25
20
3
3
OE HIGH to High Z
CE LOW to Low Z
20
15
ns
ns
55
ns
WRITE CYCLE
tWC
Write Cycle Time
15
20
25
35
55
ns
tSCE
CE LOW to Write End
12
15
20
30
50
ns
tAW
Address Set-Up to Write End
12
15
20
30
50
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
Write Pulse Width
12
15
20
25
50
ns
tSD
Data Set-Up to Write End
10
13
15
15
25
ns
tHD
Data Hold from Write End
0
tHZWE[10,11]
R/W LOW to High Z
tLZWE[10,11]
tWDD[12]
tDDD[12]
R/W HIGH to Low Z
0
10
3
0
13
3
0
15
3
0
20
3
ns
25
3
ns
ns
Write Pulse to Data Delay
30
40
50
60
70
ns
Write Data Valid to Read
Data Valid
25
30
30
35
40
ns
SEMAPHORE TIMING[13]
tSOP
SEM Flag Update Pulse
(OE or SEM)
10
10
10
15
15
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
5
5
ns
Notes:
7. See the last page of this specification for Group A subgroup testing information.
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3.
11. This parameter is guaranteed but not tested.
12. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Semaphore timing applies only to CY7C1342.
Document #: 38-06038 Rev. *B
Page 5 of 12
CY7C135
CY7C1342
Switching Waveforms
Read Cycle No. 1[14,15]
Either Port Address Access
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1342–9
Read Cycle No.
2[14,16]
Either Port CE/OE Access
SEM
[13]
or CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
1342–10
Read Timing with Port-to-Port[17]
twc
ADDRESSR
MATCH
t
R/WR
PWE
t
DATAINR
ADDRESSL
t
SD
HD
VALID
MATCH
tDDD
DATAOUTL
VALID
tWDD
1342–11
Notes:
14. R/W is HIGH for read cycle.
15. Device is continuously selected, CE = VIL and OE = VIL.
16. Address valid prior to or coincident with CE transition LOW.
17. CEL = CER =LOW; R/WL = HIGH
Document #: 38-06038 Rev. *B
Page 6 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[18,19,20]
tWC
ADDRESS
tSCE
[13]
SEM
OR CE
tAW
tHA
tPWE
R/W
tSA
tSD
DATAIN
tHD
DATA VALID
OE
t
tHZOE
LZOE
HIGH IMPEDANCE
DATAOUT
1342–12
Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[19, 21]
tWC
ADDRESS
tSCE
tHA
[13]
SEM
OR CE
tSA
tAW
tPWE
R/W
tSD
DATA VALID
DATAIN
tHZWE
DATAOUT
tHD
tLZWE
HIGH IMPEDANCE
1342–13
Notes:
18. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
19. R/W must be HIGH during all address transactions.
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified
tPWE.
21. Data I/O pins enter high-impedance when OE is held LOW during write.
Document #: 38-06038 Rev. *B
Page 7 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side (CY7C1342 only)[22]
tOHA
tAA
A0–A 2
VALID ADDRESS
VALID ADDRESS
tAW
SEM
tACE
tHA
tSCE
tSOP
tSD
I/O0
DATAINVALID
tSA
DATAOUT VALID
tHD
tPWE
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
1342–14
Timing Diagram of Semaphore Contention (CY7C1342 only)[23,24,25]
A0L–A 2L
MATCH
R/WL
SEML
tSPS
A0R–A 2R
MATCH
R/W R
SEM R
1342–15
Notes:
22. CE = HIGH for the duration of the above timing (both write and read cycle).
23. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
24. Semaphores are reset (available to both ports) at cycle start.
25. If tSPS is violated, it is guaranteed that only one side will gain access to the semaphore.
Document #: 38-06038 Rev. *B
Page 8 of 12
CY7C135
CY7C1342
Architecture
The CY7C135 consists of an array of 4K words of 8 bits each
of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). Two semaphore control pins exist for the
CY7C1342 (SEML/R).
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. Since there is no
on-chip arbitration, the user must be sure that a specific location will not be accessed simultaneously by both ports or erroneous data could result. A write operation is controlled by either the OE pin (see Write Cycle No. 1 timing diagram) or the
R/W pin (see Write Cycle No. 2 timing diagram). Data can be
written tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for write operations are
summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read the same location, a port-to-port
flowthrough delay is met before the data is valid on the output.
Data will be valid on the port wishing to read the location tDDD
after the data is presented on the writing port.
zero (the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the semaphore. Table 2 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a
write from the other port. If both ports request a semaphore
control by writing a 0 to a semaphore within tSPS of each other,
it is guaranteed that only one side will gain access to the semaphore.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
Table 1. Non-Contending Read/Write
Inputs
CE
Outputs
I/O0 – I/O7
OE
SEM
H
X
X
H
High Z
Power-Down
H
H
L
L
Data Out
Read
Semaphore
X
X
H
X
High Z
I/O Lines Disabled
H
L
X
L
Data In
Write to Semaphore
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE are asserted. If the user of the CY7C1342 wishes to access a semaphore, the SEM pin must be asserted instead of
the CE pin. Required inputs for read operations are summarized in Table 1.
Semaphore Operation
The CY7C1342 provides eight semaphore latches which are
separate from the dual port memory locations. Semaphores
are used to reserve resources which are shared between the
two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting
the latch by reading it. After writing to the semaphore, SEM or
OE must be deasserted for tSOP before attempting to read the
semaphore. The semaphore value will be available tSWRD +
tDOE after the rising edge of the semaphore write. If the left port
was successful (reads a zero), it assumes control over the
shared resource, otherwise (reads a one) it assumes the right
port has control and continues to poll the semaphore. When
the right side has relinquished control of the semaphore (by
writing a one), the left side will succeed in gaining control of
the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches. CE
must remain HIGH during SEM LOW. A0–2 represents the
semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a 0 is
written to the left port of an unused semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing a
Document #: 38-06038 Rev. *B
Operation
R/W
L
X
X
L
Illegal Condition
Table 2. Semaphore Operation Example
Function
I/O0-7 I/O0-7
Left Right
Status
No Action
1
1
Semaphore free
Left port writes
semaphore
0
1
Left port obtains
semaphore
Right port writes 0 to
semaphore
0
1
Right side is denied
access
Left port writes 1 to
semaphore
1
0
Right port is granted
access to Semaphore
Left port writes 0 to
semaphore
1
0
No change. Left port
is denied access
Right port writes 1 to
semaphore
0
1
Left port obtains
semaphore
Left port writes 1 to
semaphore
1
1
No port accessing
semaphore address
Right port writes 0 to
semaphore
1
0
Right port obtains
semaphore
Right port writes 1 to
semaphore
1
1
No port accessing
semaphore
Left port writes 0 to
semaphore
0
1
Left port obtains
semaphore
Left port writes 1 to
semaphore
1
1
No port accessing
semaphore
Page 9 of 12
CY7C135
CY7C1342
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.2
SB
ISB
1.2
NORMALIZED I,CC
I
1.0
0.8
0.6
0.4
ICC
1.0
ISB3
0.8
0.6
V CC = 5.0V
V IN = 5.0V
0.4
0.2
0.2
0.0
4.0
ICC
4.5
5.0
5.5
0.6
–55
6.0
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.10
NORMALIZED t AA
NORMALIZED t AA
TA = 25°C
1.05
1.00
1.1
1.0
VCC = 5.0V
0.9
0.95
4.0
4.5
5.0
5.5
0.8
–55
6.0
25
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
DELTA tAA (ns)
NORMALIZED t PC
0.50
15.0
10.0
0
0.0
0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-06038 Rev. *B
5.0
80
VCC = 5.0V
TA = 25°C
60
40
20
0
0
1.0
2.0
3.0
4.0 5.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
100
90
80
70
V CC = 5.0V
TA = 25°C
60
50
0.0
1.0
2.0
3.0
4.0
5.0
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs.CYCLE TIME
VCC = 5.0V
TA = 25°C
VIN = 0.5V
1.0
0.75
V CC = 4.5V
TA = 25°C
5.0
0.25
100
1.25
20.0
0.75
120
125
AMBIENT TEMPERATURE (°C)
1.0
140
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
NORMALIZED I,CC
I
SB
1.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED I CC
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
50
CYCLE FREQUENCY (MHz)
Page 10 of 12
CY7C135
CY7C1342
Ordering Information
4K x8 Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Operating
Range
Package Type
15
CY7C135–15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7C135–20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7C135–25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C135–25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C135–35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C135–35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C135–55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C135–55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
35
55
4K x8 Dual-Port SRAM with Semaphores
Speed
(ns)
Ordering Code
Package
Type
Operating
Range
Package Type
15
CY7C1342–15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7C1342–20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7C1342–25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C1342–25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C1342–35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C1342–35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C1342–55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C1342–55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
35
55
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
51-85004-*A
Document #: 38-06038 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C135
CY7C1342
Document History Page
Document Title: CY7C135/CY7C1342 4K x 8 Dual Port Static RAM and 4K x 8 Dual Port Static RAM w/Semaphores
Document Number: 38-06038
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110181
10/21/01
SZV
Change from Spec number: 38-00541 to 38-06038
*A
122288
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
236763
SEE ECN
YDT
Removed cross information from features section
Document #: 38-06038 Rev. *B
Page 12 of 12
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