ACTIVE-SEMI ACT8325 Dual pwm step-down dc/dcs in tdfn33 Datasheet

ACT8325
Active-Semi
Rev 2, 25-May-11
Dual PWM Step-Down DC/DCs in TDFN33
FEATURES
GENERAL DESCRIPTION
• Multiple Patents Pending
• Two Integrated Step-Down DC/DC Converters
The patent-pending ACT8325 integrates two stepdown DC/DCs into a single, thin, space-saving
package to provide a cost-effective, highly-efficient
ActivePMUTM power management solution. This
device is ideal for a wide range of portable handheld equipment that can benefit from the advantages of ActivePMU technology but do not require a
high level of integration.
− ACT8325NDAAA
REG1: 350mA min
REG2: 550mA min
− ACT8325NDEH
REG1: 550mA min
REG2: 800mA min
REG1 and REG2 are fixed-frequency, current-mode
PWM step-down DC/DC converters that are optimized for high efficiency and are capable of supplying up to 550mA and 800mA, respectively. Both
outputs are available in a wide range of factorypreset output voltage options, and an adjustable
output voltage mode is also available.
• 180° Out-of-Phase Operation
− Reduces Input Capacitor Requirements
•
•
•
•
Fixed or Adjustable Output Voltage Options
Independent Enable/Disable Control
Minimal External Components
The ACT8325 is available in a tiny 3mm x 3mm
10-pin Thin-DFN package that is just 0.75mm thin.
3x3mm, Thin-DFN (TDFN33-10) Package
− Only 0.75mm Height
− RoHS-Compliant
APPLICATIONS
• Portable Devices and PDAs
• MP3/MP4 Players
• Wireless Handhelds
• GPS Receivers
SYSTEM BLOCK DIAGRAM
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
FUNCTIONAL BLOCK DIAGRAM
Active-Semi
VP1
To Battery
ACT8325
ON1
REG1
UVLO
ON2
SW1
OUT1
FB1
GP12
VP2
GA
REG2
To Battery
SW2
OUT2
FB2
GP12
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ACT8325
Active-Semi
Rev 2, 25-May-11
ORDERING INFORMATIONcd
PART
NUMBER
VOUT1
VOUT2
ACT8325NDAAA-T
Adjustable
Adjustable
ACT8325NDEH-T
1.8V
3.3V
PACKAGE
PINS
TEMPERATURE
RANGE
TDFN33-10
10
-40°C to +85°C
OUTPUT VOLTAGE CODES
A
C
P
J
D
E
F
I
Q
G
H
Adjustable
1.2V
1.3V
1.4V
1.5V
1.8V
2.5V
2.8V
2.85V
3.0V
3.3V
c: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders.
Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order
quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations.
d: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
TOP VIEW
VP1
1
10
FB1
SW1
2
9
ON2
GP12
3
8
ON1
SW2
4
7
GA
VP2
5
6
FB2
Active-Semi
ACT8325
Thin - DFN (TDFN 33-10)
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ACT8325
Active-Semi
Rev 2, 25-May-11
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
VP1
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
2
SW1
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
3
GP12
Power Ground for REG1, REG2. Connect GA and GP12 together at single point as close to the
IC as possible.
4
SW2
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
5
VP2
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
6
FB2
Feedback Node for REG2. For fixed output voltage options, connect this pin directly to the output. For the adjustable output voltage options the voltage at this pin is regulated to 0.625V, connect this pin to the center of the output feedback resistor divider for voltage setting.
7
GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA and GP12 together at
a single point as close to the IC as possible.
8
ON1
Enable Control Input for REG1. Drive ON1 to VP1 or to a logic high for normal operation, drive to
GA or to a logic low to disable REG1.
9
ON2
Enable Control Input for REG2. Drive ON2 to VP1or to a logic high for normal operation, drive to
GA or to a logic low to disable REG2.
10
FB1
Feedback Node for REG1. For fixed output voltage options, connect this pin directly to the output. For the adjustable output voltage options the voltage at this pin is regulated to 0.625V, connect this pin to the center of the output feedback resistor divider for voltage setting.
EP
EP
Exposed Pad. Must be soldered to ground on PCB.
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ACT8325
Active-Semi
Rev 2, 25-May-11
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
VP1, SW1, VP2, SW2 to GP12, FB1, FB2, ON1, ON2 to GA
-0.3 to + 6
V
SW1 to VP1, SW2 to VP2
-6 to + 0.3
V
-0.3 to + 0.3
V
33
°C/W
-40 to 85
°C
Junction Temperature
125
°C
Storage Temperature
-55 to 150
°C
300
°C
GP12 to GA
Junction to Ambient Thermal Resistance (θJA)
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
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ActivePMUTM is a trademark of Active-Semi.
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
STEP-DOWN DC/DC CONVERTER
ELECTRICAL CHARACTERISTICS (REG1)
(VVP1 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
VP1 Operating Voltage Range
MIN
3.1
VP1 UVLO Threshold
Input Voltage Rising
VP1 UVLO Hysteresis
Input Voltage Falling
2.9
ON1 = GA, VVP1 = 4.2V
Adjustable Output Option Regulation
Voltage
Output Voltage Regulation Accuracy
5.5
V
3.1
V
mV
130
200
µA
0.1
1
µA
V
VNOM1 < 1.3V, IOUT1 = 10mA
-2.4%
VNOM1
+1.8%
VNOM1 ≥ 1.3V, IOUT1 = 10mA
-1.2%
VNOM1c
+1.8%
VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V
Load Regulation
IOUT1 = 10mA to 350mA
Oscillator Frequency
UNIT
0.625
Line Regulation
Switch Peak Current Limit
3
MAX
80
Standby Supply Current
Shutdown Supply Current
TYP
V
0.15
%/V
0.0017
%/mA
ACT8325NDAAA
0.45
0.6
ACT8325NDEH
0.65
0.85
VOUT1 ≥ 20% of VNOM1
1.35
1.6
A
1.85
MHz
VOUT1 = 0V
530
ACT8325NDAAA, ISW1 = -100mA
0.52
0.88
ACT8325NDEH, ISW1 = -100mA
0.4
0.68
NMOS On-Resistance
ISW1 = 100mA
0.27
0.46
Ω
SW1 Leakage Current
VVP1 = 5.5V, VSW1 = 5.5V or 0V
1
µA
PMOS On-Resistance
kHz
Ω
Power Good Threshold
94
%VNOM1
Minimum On-Time
70
ns
Logic High Input Voltage
ON1
1.4
V
Logic Low Input Voltage
ON1
Thermal Shutdown Temperature
Temperature Rising
160
°C
Thermal Shutdown Hysteresis
Temperature Falling
20
°C
0.4
V
c: VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section.
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ActivePMUTM is a trademark of Active-Semi.
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
STEP-DOWN DC/DC CONVERTER
ELECTRICAL CHARACTERISTICS (REG2)
(VVP2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
VP2 Operating Voltage Range
MIN
3.1
VP2 UVLO Threshold
Input Voltage Rising
VP2 UVLO Hysteresis
Input Voltage Falling
2.9
ON2 = GA, VVP2 = 4.2V
Adjustable Output Option Regulation
Voltage
Output Voltage Regulation Accuracy
5.5
V
3.1
V
mV
130
200
µA
0.1
1
µA
V
VNOM2 < 1.3V, IOUT2 = 10mA
-2.4%
VNOM2c
+1.8%
VNOM2 ≥ 1.3V, IOUT2 = 10mA
-1.2%
VNOM2
+1.8%
VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V
Load Regulation
IOUT2 = 10mA to 550mA
Oscillator Frequency
UNIT
0.625
Line Regulation
Switch Peak Current Limit
3
MAX
80
Standby Supply Current
Shutdown Supply Current
TYP
V
0.15
%/V
0.0017
%/mA
ACT8325NDAAA
0.65
0.85
ACT8325NDEH
0.95
1.25
VOUT2 ≥ 20% of VNOM2
1.35
1.6
A
1.85
MHz
VOUT2 = 0V
530
PMOS On-Resistance
ISW2 = -100mA
0.40
0.68
Ω
NMOS On-Resistance
ISW2 = 100mA
0.27
0.46
Ω
SW2 Leakage Current
VVP2 = 5.5V, VSW2 = 5.5V or 0V
1
µA
kHz
Power Good Threshold
94
%VNOM2
Minimum On-Time
70
ns
Logic High Input Voltage
ON2
1.4
V
Logic Low Input Voltage
ON2
Thermal Shutdown Temperature
Temperature Rising
160
°C
Thermal Shutdown Hysteresis
Temperature Falling
20
°C
0.4
V
c: VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section.
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ActivePMUTM is a trademark of Active-Semi.
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
STEP-DOWN DC/DC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8325NDAAA, VVP1 = VVP2 = 3.6V, L = 3.3µH, CVP1 = CVP2 = 2.2μF, COUT1 = COUT2 = 10μF, TA = 25°C, unless otherwise specified.)
REG1 Efficiency vs. Load Current
Efficiency (%)
85
80
100
VIN = 4.2V
75
VIN = 3.6V
VOUT2 = 3.3V
90
Efficiency (%)
VIN = 3.6V
ACT8325-002
VOUT1 = 1.2V
90
REG2 Efficiency vs. Load Current
ACT8325-001
95
70
65
VIN = 4.2V
80
70
60
60
55
50
50
1
10
1
1000
100
10
Output Current (mA)
OUT2 Regulation Voltage
0.22
OUT2 Voltage (%)
OUT1 Voltage (%)
0.44
0.33
0.11
0.00
-0.11
-0.22
-0.33
0.18
0.09
0.00
-0.09
-0.18
-0.27
-0.36
-0.56
-0.45
-0.55
-40
-20
0
20
40
60
IOUT2 = 35mA
0.36
0.27
-0.44
-0.67
-40
85
-20
Temperature (°C)
REG1 MOSFET Resistance
20
40
60
85
REG2 MOSFET Resistance
PMOS
RDSON (mΩ)
400
PMOS
360
NMOS
200
ACT8325-006
440
ACT8325-005
500
RDSON (mΩ)
0
Temperature (°C)
600
300
ACT8325-004
0.55
0.45
ACT8325-003
IOUT1 = 35mA
0.56
1000
Output Current (mA)
OUT1 Regulation Voltage
0.67
100
280
NMOS
200
120
100
40
0
0
2.5
3.0
3.5
4.0
4.5
5.0
2.5
5.5
ActivePMUTM is a trademark of Active-Semi.
3.5
4.0
4.5
5.0
5.5
VP2 Voltage (V)
VP1 Voltage (V)
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
STEP-DOWN DC/DC CONVERTER
FUNCTIONAL DESCRIPTION
General Description
Compensation
REG1 and REG2 are fixed-frequency, currentmode, synchronous PWM step-down converters
that achieve peak efficiencies of up to 97%. REG1
is capable of supplying up to 550mA of output current, while REG2 supports up to 800mA. These
regulators operate with a fixed frequency of
1.6MHz, minimizing noise in sensitive applications
and allowing the use of small external components.
REG1 and REG2 are available with a variety of
standard and custom output voltages, as described
in the Ordering Information section of this datasheet.
REG1 and REG2 utilize current-mode control and a
proprietary internal compensation scheme to simultaneously simplify external component selection
and optimize transient performance over their full
operating range. No compensation design is required; simply follow a few simple guidelines described below when choosing external components.
Thermal Shutdown
The ACT8325 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8325 die temperature exceeds
160°C, and prevents the regulators from being enabled until the IC temperature drops by 20°C (typ).
100% Duty Cycle Operation
Both REG1 and REG2 are capable of operating at
up to 100% duty cycle. During 100% duty-cycle
operation, the high-side power MOSFET is held on
continuously, providing a direct connection from the
input to the output (through the inductor), ensuring
the lowest possible dropout voltage in batterypowered applications.
Input Capacitor Selection
The input capacitor reduces peak currents and
noise induced upon the voltage source. A 2.2µF
ceramic capacitor for each of REG1 and REG2 is
recommended for most applications.
Synchronous Rectification
Output Capacitor Selection
REG1 and REG2 both feature integrated n-channel
synchronous rectifiers, maximizing efficiency and
minimizing the total solution size and cost by eliminating the need for external rectifiers.
For most applications, 10µF ceramic output capacitors are recommended for both REG1 and REG2.
Although the these regulators were designed to
take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR
tantalum capacitors can provide acceptable results
as well.
Enabling and Disabling REG1 and REG2
Each of the ACT8325's regulators features independent pin-controlled enable control. Drive ON1 to
a logic-high to enable REG1, drive ON1 to a logiclow to disable REG1. Similarly, drive ON2 to a
logic-high to enable REG2, drive ON2 to a logic-low
to disable REG2. When disabled, each regulator's
supply current drops to less than 1µA.
Output Voltage Programming
Figure 4:
Output Voltage Programming
OUTx
Soft-Start
REG1 and REG2 each include matched soft-start
circuitry. When enabled, the output voltages track
the internal 80µs soft-start ramp and both power up
in a monotonic manner that is independent of loading on either output. This circuitry ensures that both
outputs power up in a controlled manner, greatly
simplifying power sequencing design considerations.
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ActivePMUTM is a trademark of Active-Semi.
CFF
ACT8325
RFB1
FBx
RFB2
Figure 4 shows the feedback network necessary to
set the output voltage when using the adjustable
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
STEP-DOWN DC/DC CONVERTER
output voltage option. output voltage option. Select
components as follows: Set RFB2 = 51kΩ, then
calculate RFB1 using the following equation:
⎛V
⎞
RFB1 = RFB2 ⎜⎜ OUTX − 1 ⎟⎟
⎝ VFBX
⎠
(1)
where VFBX is 0.625V. Finally choose CFF using the
following equation:
C FF =
2.2 × 10 −6
R FB1
(2)
Where RFB1 = 47kΩ, use 47pF.
Inductor Selection
REG1 and REG2 utilize current-mode control and a
proprietary internal compensation scheme to simultaneously simplify external component selection
and optimize transient performance over their full
operating range. These devices were optimized for
operation with 3.3µH inductors, although inductors
in the 2.2µH to 4.7µH range can be used. Choose
an inductor with a low DC-resistance, and avoid
inductor saturation by choosing inductors with DC
ratings that exceed the maximum output current of
the application by at least 30%.
PCB Layout Considerations
High switching frequencies and large peak current
make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and
voltage gradients in the ground plane, both of which
can result in instability or regulation errors. Stepdown DC/DCs exhibit discontinuous input current,
so the input capacitors should be placed as close
as possible to the IC, and avoiding the use of vias if
possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator’s
power loop should be connected at a single point in
a star-ground configuration, and this point should
be connected to the backside ground plane with
multiple vias. For fixed output voltage options, connect the output node directly to the FBx pin. For
adjustable output voltage options, connect the feedback resistors and feed-forward capacitor to the
FBx pin through the shortest possible route. In both
cases, the feedback path should be routed to maintain sufficient distance from switching nodes to prevent noise injection.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
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Copyright © 2011 Active-Semi, Inc.
ACT8325
Active-Semi
Rev 2, 25-May-11
PACKAGE INFORMATION
PACKAGE OUTLINE
TDFN33-10 PACKAGE OUTLINE AND DIMENSIONS
SYMBOL
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.0000
0.002
A3
0.153
0.253
0.006
0.010
D
2.900
3.100
0.114
0.122
E
2.900
3.100
0.114
0.122
D2
2.350
2.450
0.093
0.096
E2
1.650
1.750
0.065
0.069
b
0.200
0.320
0.008
0.012
e
L
0.500 TYP
0.300
0.500
0.020 TYP
0.012
0.020
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
[email protected] or visit http://www.active-semi.com.
®
is a registered trademark of Active-Semi.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
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Copyright © 2011 Active-Semi, Inc.
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