MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION ●Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) ●Power dissipation In high-speed mode ..........................................................34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) ●Operating temperature range .................................... –20 to 85°C The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter. FEATURES ● Basic machine-language instructions ...................................... 71 ● Minimum instruction execution time .................................. 0.5 µs (at 8 MHz oscillation frequency) ● Memory size ROM ................................................................... 8K to 32K bytes RAM ................................................................. 512 to 1024 bytes ● Programmable input/output ports ............................................ 34 ● Interrupts ................................................. 15 sources, 14 vectors ● Timers ............................................................................. 8-bit ✕ 4 ● Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized) ● Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized) ● PWM ............................................................................... 8-bit ✕ 1 ● A-D converter ............................................... 10-bit ✕ 5 channels ● Watchdog timer ............................................................ 16-bit ✕ 1 ● Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 M38503MXH-XXXFP/SP VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK P25/TxD P24/RxD P23 P22 CNVSS VPP P21/XCIN P20/XCOUT RESET XIN XOUT VSS 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) : Flash memory version Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP) Fig. 1 M38503MXH-XXXFP/SP pin configuration 2 Fig. 2 Functional block diagram 20 AVSS VREF 2 3 A-D converter (10) Watchdog timer P WM (8) Reset Sub-clock Sub-clock input output XCIN XCOUT Main-clock output XOUT Clock generating circuit 19 Main-clock input XIN I/O port P4 4 5 6 7 8 P4(5) RAM FUNCTIONAL BLOCK DIAGRAM INT0– INT3 ROM I/O port P3 38 39 40 41 42 P3(5) 21 VSS PC H SI/O1(8) C P U 1 VCC PS PC L S Y X A 18 RESET Reset input P2(8) CNTR0 I/O port P2 9 10 11 12 13 1416 17 15 CNVSS XCIN XCOUT P1(8) I/O port P1 22 23 24 25 26 27 28 29 CNTR1 Prescaler Y(8) Prescaler X(8) Prescaler 12(8) I/O port P0 30 31 32 33 34 35 36 37 P0(8) Timer Y( 8 ) Timer X( 8 ) Timer 2( 8 ) Timer 1( 8 ) SI/O2(8) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description Pin Name VCC, V SS Power source CNVSS CNV SS input RESET Reset input XIN Clock input XOUT Clock output P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 I/O port P0 P10–P17 I/O port P1 P20/XCOUT P21/XCIN P22 P23 I/O port P2 P24/RxD P25/TxD Functions •Reset input pin for active “L.” •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the X IN pin and leave the XOUT pin open. •8-bit CMOS I/O port. • Serial I/O2 function pin •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •P10 to P17 (8 bits) are enabled to output large current for LED drive. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. • Sub-clock generating circuit I/O pins (connect a resonator) •P20, P21 , P24 to P27: CMOS3-state output structure. •P22, P23 : N-channel open-drain structure. • Serial I/O1 function pin P26/SCLK P27/CNTR0/ SRDY1 P30/AN0– P34/AN4 • Serial I/O1 function pin/ Timer X function pin •8-bit CMOS I/O port with the same function as port P0. I/O port P3 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM Function except a port function •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. I/O port P4 • A-D converter input pin •CMOS compatible input level. •CMOS 3-state output structure. •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. • Timer Y function pin • Interrupt input pins •CMOS 3-state output structure. • Interrupt input pin • SCMP2 output pin • Interrupt input pin • PWM output pin 3 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product name M3850 3 M 4 H– XXX SP Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. – : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. H–: Partial specification changed version ROM/PROM/Flash memory size 9 : 36864 bytes 1 : 4096 bytes A : 40960 bytes 2 : 8192 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Fig. 3 Part numbering 4 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Packages Mitsubishi plans to expand the 3850 group (spec. H) as follows. 42P4B ......................................... 42-pin shrink plastic-molded DIP 42P2R-A/E ........................................... 42-pin plastic-molded SOP 42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version) Memory Type Support for mask ROM, One Time PROM, and flash memory versions. Memory Size Flash memory size ......................................................... 32 K bytes One Time PROM size ..................................................... 24 K bytes Mask ROM size ................................................... 8 K to 32 K bytes RAM size ............................................................... 512 to 1 K bytes Memory Expansion Plan ROM size (bytes) As of Nov. 2000 ROM exteranal Under development M38507M8/F8 32K 28K Mass production M38504M6/E6 24K 20K Mass production M38503M4H 16K 12K Mass production M38503M2H 8K 384 512 640 768 896 1024 1152 RAM size (bytes) 1280 1408 1536 2048 Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig. 4 Memory expansion plan 5 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Currently planning products are listed below. As of Nov. 2000 Table 2 Support products Product name M38503M2H-XXXSP M38503M2H-XXXFP M38503M4H-XXXSP M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M388504E6SP M388504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 8192 (8062) 512 16384 (16254) 512 Package 42P4B 42P2R-A/E 424P4B 42P2R-A/E 424P4B 24576 (24446) 640 42S1B-A 42P2R-A/E Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products 3850 group (standard) 3850 group (spec. H) M38503M2-XXXFP/SP M38503M2H-XXXFP/SP M38503M4-XXXFP/SP M38503M4H-XXXFP/SP M38503E4-XXXFP/SP M38504M6-XXXFP/SP M38503E4FP/SP M38504E6-XXXFP/SP M38503E4SS M38504E6FP/SP M38504E6SS M38507M8-XXXFP/SP M38507F8FP/SP M37516RSS Table 4 Differences between 3850 group (standard) and 3850 group (spec. H) Serial I/O 3850 group (standard) 1: Serial I/O (UART or Clock-synchronized) A-D converter Large current port Unserviceable in low-speed mode 5: P13–P17 3850 group (spec. H) 2: Serial I/O1 (UART or Clock-synchronized) Serial I/O2 (Clock-synchronized) Serviceable in low-speed mode 8: P1 0–P17 Notes on differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-X OUT , XCIN -X COUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. 6 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016 ”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PC L. It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 5 740 Family CPU register structure 7 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) – 1 M (S) (PCL) (S) (S)– 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) – 1 (PCL) Push return address on stack (S) – 1 (PS) Push contents of processor status register on stack (S) – 1 Interrupt Service Routine Execute RTS (S) (PCH) I Flag is set from “0” to “1” Fetch the jump vector Execute RTI Note: Condition for acceptance of an interrupt (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 6 Register push and pop at interrupt generation and subroutine call Table 5 Push and pop instructions of accumulator or processor status register Accumulator Processor status register 8 Push instruction to stack Pop instruction from stack PHA PHP PLA PLP MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag D flag SEI CLI SED CLD B flag _ _ T flag V flag SET CLT _ CLV N flag _ _ 9 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16 . b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 7 Structure of CPU mode register 10 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Special Page RAM Access to this area with only 2 bytes is possible in the special page addressing mode. RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 000016 SFR area Zero page 004016 RAM 010016 XXXX16 Not used 0FF016 0FFF16 SFR area (Note) Not used YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Note: Flash memory version only Fig. 8 Memory map diagram 11 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) Timer count source selection register (TCSS) 000816 Port P4 (P4) 002816 000916 Port P4 direction register (P4D) 002916 000A16 002A16 000B16 002B16 Reserved ✽ 000C16 002C16 Reserved ✽ 000D16 002D16 Reserved ✽ 000E16 002E16 Reserved ✽ 000F16 002F16 Reserved ✽ 001016 003016 Reserved ✽ 003116 Reserved ✽ 001116 001216 Reserved ✽ 003216 001316 Reserved ✽ 003316 001416 Reserved ✽ 003416 A-D control register (ADCON) 001516 Serial I/O2 control register 1 (SIO2CON1) 003516 A-D conversion low-order register (ADL) 001616 Serial I/O2 control register 2 (SIO2CON2) 003616 A-D conversion high-order register (ADH) 001716 Serial I/O2 register (SIO2) 003716 Reserved ✽ 001816 Transmit/Receive buffer register (TB/RB) 003816 MISRG 001916 Serial I/O1 status register (SIOSTS) 003916 Watchdog timer control register (WDTCON) 001A16 Serial I/O1 control register (SIOCON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1 (IREQ1) 001D16 PWM control register (PWMCON) 003D16 Interrupt request register 2 (IREQ2) 001E16 PWM prescaler (PREPWM) 003E16 Interrupt control register 1 (ICON1) 001F16 PWM register (PWM) 003F16 Interrupt control register 2 (ICON2) ✽ Reserved : Do not write any data to this addresses, because these areas are reserved. Fig. 9 Memory map of special function register (SFR) 12 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 7 I/O port function Pin P00/S IN2 P01/S OUT2 P02/S CLK2 P03/S RDY2 P04–P07 P10–P17 P20/X COUT P21/X CIN P22 P23 P24 /RxD P25/TxD P26/S CLK P27 /CNTR0/S RDY1 P30/AN 0– P34/AN 4 P40 /CNTR1 P41/INT0 P42/INT1 P43/INT2 /SCMP2 Name I/O Structure Non-Port Function Serial I/O2 function I/O Port P0 Related SFRs Serial I/O2 control register CMOS compatible input level CMOS 3-state output Sub-clock generating circuit CPU mode register CMOS compatible input level N-channel open-drain output Port P2 Input/output, individual bits Port P3 CMOS compatible input level CMOS 3-state output Ref.No. (1) (2) (3) (4) (5) Port P1 Port P4 P44/INT3/PWM Input/Output (6) (7) (8) Serial I/O1 function I/O Serial I/O1 control register (9) (10) (11) Serial I/O1 function I/O Timer X function I/O Serial I/O1 control register Timer XY mode register (12) A-D conversion input A-D control register (13) Timer Y function I/O Timer XY mode register (14) External interrupt input Interrupt edge selection register (15) External interrupt input Interrupt edge selection register Serial I/O2 control register (16) Interrupt edge selection register PWM control register (17) SCMP2 output External interrupt input PWM output 13 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Port P01 (1) Port P00 P01/SOUT2 P-channel output disable bit Direction register Data bus Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output (3) Port P02 (4) Port P03 P02/SCLK2 P-channel output disable bit SRDY2 output enable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (6) Port P20 (5) Ports P04-P07,P1 Port XC switch bit Direction register Data bus Port latch Direction register Data bus Port latch Oscillator Port P21 (7) Port P21 Port XC switch bit Port XC switch bit (8) Ports P22,P23 Direction register Data bus Direction register Port latch Data bus Sub-clock generating circuit input Fig. 10 Port block diagram (1) 14 Port latch MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (10) Port P25 (9) Port P24 Serial I/O1 enable bit Receive enable bit P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Direction register Port latch Data bus Port latch Data bus Serial I/O1 input Serial I/O1 output (11) Port P26 (12) Port P27 Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Port latch Data bus Pulse output mode Serial ready output Serial I/O1 clock output Timer output External clock input (13) Ports P30-P34 CNTR0 interrupt input (14) Port P40 Direction register Direction register Port latch Data bus Port latch Data bus Pulse output mode Timer output A-D converter input Analog input pin selection bit CNTR1 interrupt input (16) Port P43 Serial I/O2 I/O comparison signal control bit (15) Ports P41,P42 Direction register Data bus Port latch Interrupt input Direction register Data bus Port latch Serial I/O2 I/O comparison signal output Interrupt input Fig. 11 Port block diagram (2) 15 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (17) Port P44 PWM output enable bit Direction register Data bus Port latch PWM output Interrupt input Fig. 12 Port block diagram (3) 16 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS ■Notes Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR 0 and CNTR1 ) 3. Clear the interrupt request bit to “0” 4. Accept the interrupt. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. 17 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 8 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) Priority 1 Vector Addresses (Note 1) High Low FFFD16 FFFC16 Interrupt Request Generating Conditions Remarks At reset Non-maskable At detection of either rising or falling edge of INT0 input External interrupt (active edge selectable) INT0 2 FFFB16 FFFA16 Reserved 3 FFF916 FFF816 Reserved External interrupt (active edge selectable) INT1 4 FFF716 FFF616 At detection of either rising or falling edge of INT1 input INT2 5 FFF516 FFF416 At detection of either rising or falling edge of INT2 input External interrupt (active edge selectable) INT3/ Serial I/O2 6 FFF316 FFF216 At detection of either rising or falling edge of INT 3 input/ At completion of serial I/O2 data reception/transmission External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit Reserved Timer X Timer Y Timer 1 Timer 2 7 8 9 FFF116 FFEF 16 FFED 16 10 11 FFEB 16 FFE916 FFF016 FFEE16 FFEC16 FFEA 16 FFE816 At timer X underflow At timer Y underflow At timer 1 underflow Serial I/O1 reception 12 FFE716 FFE616 At completion of serial I/O1 data reception Valid when serial I/O1 is selected Serial I/O1 transmission 13 FFE516 FFE416 At completion of serial I/O1 transfer shift or when transmission buffer is empty Valid when serial I/O1 is selected CNTR0 14 FFE316 FFE216 At detection of either rising or falling edge of CNTR0 input External interrupt (active edge selectable) CNTR1 15 FFE116 FFE016 At detection of either rising or falling edge of CNTR1 input External interrupt (active edge selectable) A-D converter BRK instruction 16 FFDF16 FFDE16 At completion of A-D conversion 17 FFDD16 FFDC16 At BRK instruction execution Reserved Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 18 STP release timer underflow At timer 2 underflow Non-maskable software interrupt MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns “0” when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 b7 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write “1” to this bit.) INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit Reserved(Do not write “1” to this bit.) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers 19 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS Timer 1 and Timer 2 The 3850 group (spec. H) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. b0 b7 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig. 15 Structure of timer XY mode register b7 b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read) Fig. 16 Structure of timer count source selection register 20 (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “00 16”, the signal output from the CNTR 0 (or CNTR1) pin is inverted. If the CNTR 0 (or CNTR 1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR 0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR 0 (or CNTR1) pin is counted. When the CNTR 0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR 0 (or CNTR1 ) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR 1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. ■Note When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler X latch (8) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode) Timer X count source selection bit measurement mode Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge selection bit “0 ” P27/CNTR0 Event counter mode “1 ” Timer X (8) To timer X interrupt request bit Timer X count stop bit To CNTR0 interrupt request bit CNTR0 active edge selection “1” bit “0” Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Port P27 latch Port P27 direction register Timer X latch (8) Pulse output mode Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler Y latch (8) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit Pulse width measurement mode Timer mode Pulse output mode Prescaler Y (8) CNTR1 active edge selection bit “0 ” P40/CNTR1 Event counter mode “1 ” Port P40 direction register Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge selection “1” bit Q Toggle flip-flop T Q Port P40latch Timer Y latch (8) “0” R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit Timer 12 count source selection bit To timer 1 interrupt request bit Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 21 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Clock Synchronous Serial I/O Mode SERIAL I/O ●SERIAL I/O1 Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 001816 Receive buffer register Receive buffer full flag (RBF) Receive shift register P24/RXD Address 001A16 Receive interrupt request (RI) Shift clock Clock control circuit P26/SCLK XIN Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 BRG count source selection bit 1/4 P27/SRDY1 F/F Clock control circuit Falling-edge detector Shift clock P25/TXD Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Transmit buffer register Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Address 001816 Data bus Fig. 18 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 19 Operation of clock synchronous serial I/O1 function 22 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 001816 P24/RXD Serial I/O1 control register Address 001A16 Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 8 bits PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O1 synchronous clock selection bit P26/SCLK XIN BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 Transmit shift register P25/TXD Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer register Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 20 Block diagram of UART serial I/O1 23 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TBE=1 ST D0 D1 SP TSC=1 ST D0 Receive buffer read signal SP D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 21 Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. 24 [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25 /TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIOSTS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits b0 Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins) Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 22 Structure of serial I/O1 control registers 25 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ●SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P01 /S OUT2 , P0 2/S CLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to “1” automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H” is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16 ). [Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 23. 26 b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits b2 b1 b0 0 0 0 0 1 1 0 0 1 1 1 1 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode ) b7 b0 Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance Fig. 23 Structure of Serial I/O2 control registers 1, 2 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal synchronous clock selection bits 1/8 XCIN “10” “00” “01” XIN 1/16 1/32 Divider Main clock division ratio selection bits (Note) Data bus 1/64 1/128 1/256 P03 latch Serial I/O2 synchronous clock selection bit “0” P03/SRDY2 SCLK2 SRDY2 Synchronous circuit “1” SRDY2 output enable bit “1” “0” External clock P02 latch Optional transfer bits (3) “0” P02/SCLK2 Serial I/O2 interrupt request Serial I/O counter 2 (3) “1” Serial I/O2 port selection bit P01 latch “0” P01/SOUT2 “1” Serial I/O2 port selection bit Serial I/O2 register (8) P00/SIN2 P43 latch “0” D P43/SCMP2/INT2 Q “1” Serial I/O2 I/O comparison signal control bit Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig. 24 Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal to serial I/O2 register (Note 2) Serial I/O2 output SOUT2 D0 D1 . D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion. Fig. 25 Timing chart of Serial I/O2 27 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SCMP2 SCLK2 SOUT2 SIN2 Judgement of I/O data comparison Fig. 26 SCMP2 output operation 28 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) PWM Operation The 3850 group (spec. H) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X IN or that clock input divided by 2. When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P4 4. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz,count source selection bit = “0”) Output pulse “H” term = PWM period ✕ m / 255 = 0.125 ✕ (n+1) ✕ m µs (when f(X IN) = 8 MHz,count source selection bit = “0”) 31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz,count source selection bit = “0”) Fig. 27 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit (XCIN “0” XIN at low-speed mode) 1/2 Port P44 “1” Port P44 latch PWM enable bit Fig. 28 Block diagram of PWM function 29 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read) Fig. 29 Structure of PWM control register A B B = C T T2 C PWM output T PWM register write signal PWM prescaler write signal T T2 (Changes “H” term from “A” to “B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 30 PWM output timing when PWM register or PWM prescaler is changed ■Note The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: 30 n+1 2 • f(XIN) sec (Count source selection bit = 0, where n is the value set in the prescaler) n+1 f(XIN) sec (Count source selection bit = 1, where n is the value set in the prescaler) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 16, 003616 b7 b0 AD control register (ADCON : address 003416) The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. Analog input pin selection bits b2 b1 b0 0 0 0 0 1 [AD Control Register (ADCON)] 003416 The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. 0 0 1 1 0 0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4 Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) Comparison Voltage Generator Fig. 31 Structure of AD control register The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Channel Selector 10-bit reading (Read address 003616 before 003516) The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator. b7 (Address 003616) Comparator and Control Circuit b0 b9 b8 b7 The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(X IN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(X IN) and f(X CIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit. (Address 003516) b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : The high-order 6 bits of address 003616 become “0” at reading. 8-bit reading (Read only address 003516) b7 b0 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b2 Fig. 32 Structure of A-D conversion registers Data bus AD control register (Address 003416) b7 b0 3 A-D control circuit Channel selector P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 Comparator A-D interrupt request A-D conversion high-order register (Address 003616) A-D conversion low-order register (Address 003516) 10 Resistor ladder VREF AVSS Fig. 33 Block diagram of A-D converter 31 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER ●Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916 ) permits selecting a watchdog timer H count source. When this bit is set to “0”, the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(X CIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(X IN) (or f(XCIN)). The detection time in this case is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after reset. The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control register (address 003916) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003916 ) may be started before an underflow. When the watchdog timer control register (address 003916 ) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. ●Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916 ) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “1”, it cannot be rewritten to “0” by program. This bit is cleared to “0” after reset. ●Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to “FF16 .” “FF16” is set when watchdog timer control register is written to. XCIN Data bus “0” “10” Main clock division ratio selection bits (Note) XIN “FF16” is set when watchdog timer control register is written to. Watchdog timer L (8) 1/16 “1” “00” “01” Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit RESET Internal reset Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 34 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 003916) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 35 Structure of Watchdog timer control register 32 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more of XIN. Then the RESET pin is returned to an “H” level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for V CC of 2.7 V. Poweron RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage; Vcc = 2.7 V RESET VCC Power source voltage detection circuit Fig. 36 Reset circuit example XIN φ RESET RESETOUT Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals. Fig. 37 Reset sequence 33 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents (1) Port P0 (P0) 000016 0016 (34) MISRG 003816 (2) Port P0 direction register (P0D) 000116 0016 (35) Watchdog timer control register (WDTCON) 003916 0 0 1 1 1 1 1 1 (3) Port P1 (P1) 000216 0016 (36) Interrupt edge selection register (INTEDGE) 003A16 (4) Port P1 direction register (P1D) 000316 0016 (37) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (5) Port P2 (P2) 000416 0016 (38) Interrupt request register 1 (IREQ1) 003C16 0016 (6) Port P2 direction register (P2D) 000516 0016 (39) Interrupt request register 2 (IREQ2) 003D16 0016 (7) Port P3 (P3) 000616 0016 (40) Interrupt control register 1 (ICON1) 003E16 0016 (8) Port P3 direction register (P3D) 000716 0016 (41) Interrupt control register 2 (ICON2) 003F16 0016 (9) Port P4 (P4) 000816 0016 (42) Processor status register (PS) (10) Port P4 direction register (P4D) 000916 0016 (43) Program counter (PCH) FFFD16 contents (11) Serial I/O2 control register 1 (SIO2CON1) 001516 0016 (PCL) FFFC16 contents (12) Serial I/O2 control register 2 (SIO2CON2) 001616 0 0 0 0 0 1 1 1 (13) Serial I/O2 register (SIO2) 001716 X X X X X X X X (14) Transmit/Receive buffer register (TB/RB) 001816 X X X X X X X X (15) Serial I/O1 status register (SIOSTS) 001916 1 0 0 0 0 0 0 0 (16) Serial I/O1 control register (SIOCON) 001A16 (17) UART control register (UARTCON) 001B16 1 1 1 0 0 0 0 0 (18) Baud rate generator (BRG) 001C16 X X X X X X X X (19) PWM control register (PWMCON) 001D16 (20) PWM prescaler (PREPWM) 001E16 X X X X X X X X (21) PWM register (PWM) 001F16 X X X X X X X X (22) Prescaler 12 (PRE12) 002016 FF16 (23) Timer 1 (T1) 002116 0116 (24) Timer 2 (T2) 002216 0016 (25) Timer XY mode register (TM) 002316 0016 (26) Prescaler X (PREX) 002416 FF16 (27) Timer X (TX) 002516 FF16 (28) Prescaler Y (PREY) 002616 FF16 (29) Timer Y (TY) 002716 FF16 (30) Timer count source selection register (TCSS) 002816 0016 (31) A-D control register (ADCON) 003416 0 0 0 1 0 0 0 0 (32) A-D conversion low-order register (ADL) 003516 X X X X X X X X (33) A-D conversion high-order register (ADH) 003616 0 0 0 0 0 0 X X 0016 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 38 Internal status at reset 34 Address Register contents 0016 0016 X X X X X 1X X MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT (2) Wait mode The 3850 group (spec. H) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer ’s recommended values. No external resistor is needed between XIN and X OUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock X IN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction. ■Note (2) High-speed mode The internal clock φ is half the frequency of XIN. When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. ■Note If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN ). XCIN XCOUT Rf CCIN XIN XOUT Rd CCOUT CIN COUT (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock X IN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock X CIN-X COUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Fig. 39 Ceramic resonator circuit XCIN Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and X IN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF 16” and timer 1 is set to “01 16.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either X IN or X CIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. XCOUT Rf XIN XOUT Open Rd External oscillation circuit CCIN CCOUT Vcc Vss Fig. 40 External clock input circuit 35 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [MISRG (MISRG)] 003816 b7 b0 MISRG (MISRG : address 003816) MISRG consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to “1” while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to “1”, XIN oscillation automatically starts and the mode is automatically switched to the middle-speed mode. Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return “0” when read) Note: W h e n th e mo d e i s a u t o m a ti c a lly s wi tc h e d fr o m t h e lo w- s p e e d m o d e t o the middle-speed mode, the value of CPU mode register (address 003B16) changes. Fig. 41 Structure of MISRG XCOUT XCIN “0” “1” Port XC switch bit XOUT XIN Main clock division ratio selection bits (Note 1) Low-speed mode 1/2 1/4 Prescaler 12 1/2 High-speed or middle-speed mode FF16 Timer 1 0116 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode Timing φ (internal clock) High-speed or low-speed mode Main clock stop bit Q S R S Q STP instruction WIT instruction Q S R R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: When bit 0 of MISRG = “0” Fig. 42 System clock generating circuit block diagram (Single-chip mode) 36 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset C “0 M4 CM ” ← “1 6 → ”← “1 ” → “0 ” ” “0 4 → M ” C ”← “0 “1 M6 → C ”← “1 Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1” ←→ “0” C “0 M7 CM ” ← “1 6 → “1 ”← ” → “0 ” CM4 “1” ←→ “0” CM4 “1” ←→ “0” CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) High-speed mode (f(φ) = 4 MHz) C M6 “1” ←→ “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1” ←→ “0” Middle-speed mode (f(φ) = 1 MHz) CM5 “1” ←→ “0” Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”. (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 43 State transitions of system clock 37 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Summary Table 9 shows the summary of the M38507F8 (flash memory version). Table 9 Summary of M38507F8 (flash memory version) Item Specification Power source voltage Vcc = 2.7–5.5 V (Note 1) Vcc = 2.7–3.6 V (Note 2) Program/Erase VPP voltage 4.5–5.5 V, f(XIN) = 8 MHz Flash memory mode 3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode) User ROM area 1 block (32 Kbytes) Boot ROM area 1 block (4 Kbytes) (Note 3) Erase block division Program method Byte program Erase method Batch erasing Program/Erase control method Program/Erase control by software command Number of commands 6 commands Number of program/Erase times 100 times ROM code protection Available in parallel I/O mode, and standard serial I/O mode Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation. 2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. 38 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Flash Memory Mode The M38507F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when V CC is 5 V, and 2 power sources when VCC is 3.3 V. For this flash memory , three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/ O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory of the M38507F8 is divided into User ROM area and Boot ROM area as shown in Figure 44. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Parallel I/O mode 800016 Block 1 : 32 kbyte FFFF16 F00016 4 kbyte FFFF16 User ROM area Boot ROM area BSEL = 0 BSEL = 1 CPU rewrite mode, standard serial I/O mode 800016 Block 1 : 32 kbyte Product name Flash memory start address M38507F8 800016 FFFF16 F00016 4 kbyte FFFF16 User ROM area User area / Boot area selection bit = 0 Boot ROM area User area / Boot area selection bit = 1 Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 44 Block diagram of flash memory version 39 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 44 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User area/Boot area selection bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In boot mode, this bit is set “1” automatically. Operation of this bit must be in RAM area. Figure 46 shows a flowchart for setting/releasing the CPU rewrite mode. Microcomputer Mode and Boot Mode Precautions on CPU Rewrite Mode The control program for CPU rewrite mode must be written into the user ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 44 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P41 /INT0 pin high, the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC 16, FFFD16 fixation). This mode is called the “boot” mode. Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock frequency 4MHz or less using the main clock division ratio selection bits (bit 6, 7 at 003B16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . (3) Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Watchdog timer Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. In case of the M38507F8, it has only one block. In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) Reset Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it can be executed. The CPU rewrite mode is accessed by applying 5V ± 10% to the CNVSS pin and writing “1” for the CPU rewrite mode select bit (bit 1 in address 0FFE16). Software commands are accepted once the mode is accessed. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 45 shows the flash memory control register. _____ Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”. Bit 1 is the CPU rewrite mode select bit. When this bit is set to “1” and 5V ± 10% are applied to the CNVSS pin, the M38507F8 accesses the CPU rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing a “0”. 40 Reset is always valid. In case of CNVSS = H when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset FM CR 0FFE16 XXX00001 Bit name Bit symbol Function FMCR0 RY/BY status flag 0: Busy (being written or erased) 1: Ready FMCR1 CPU rewrite mode select bit (Note 1) FMCR2 CPU rewrite mode entry flag 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) FMCR3 Flash memory reset bit (Note 2) 0: Normal operation 1: Reset FMCR4 User area / Boot area selection bit 0: User ROM area 1: Boot ROM area R WW R Nothing is assigned. When write, set “0”. When read, values are indeterminate. Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to “0” subsequently after setting it to “1” (reset). Fig. 45 Flash memory control registers Program in ROM Start Single-chip mode, or boot mode Set CPU mode register (Note 1) Transfer CPU rewrite mode control program to internal RAM Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Program in RAM *1 Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Check the CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 2) *1 Write “0” to CPU rewrite mode select bit End Notes 1: Set bit 6, 7 (Main clock division ratio selection bits ) at CPU mode register (003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Fig. 46 CPU rewrite mode set/reset flowchart 41 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Software Commands Read Status Register Command (7016) Table 10 lists the software commands. After setting the CPU rewrite mode select bit to “1”, write a software command to specify an erase or program operation. The content of each software command is explained below. When the command code “70 16” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D 7) by a read in the second bus cycle. The status register is explained in the next section. Read Array Command (FF16) Clear Status Register Command (5016) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D7). The read array mode is retained intact until another command is written. And after power on and after recover from deep power down mode, this mode is selected also. This command is used to clear the bits SR1,SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. Table 10 List of software commands (CPU rewrite mode) First bus cycle Command Cycle number Mode Address Second bus cycle Data (D0 to D7) Mode Address Data (D0 to D7) Read X SRD (Note 1) Read array 1 Write Read status register 2 Write X 7016 Clear status register 1 Write X 5016 Program 2 Write X 4016 Write Erase all block 2 Write X 2016 Write X 2016 Block erase 2 Write X 2016 Write (Note 3) D016 X (Note 4) Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address (Enter the maximum address of each block.) 4: X denotes a given address in the user ROM area . 42 FF16 WA (Note 2) BA WD (Note 2) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Program Command (4016) Block Erase Command (2016/D016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read_____ ing the status register or the RY/BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0–D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF 16) is written. ____ The RY/BY status flag is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. By writing the command code “2016 ” in the first bus cycle and the confirmation command code “D016 ” in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed. Erase All Blocks Command (2016/2016) By writing the command code “20 16” in the first bus cycle and the confirmation command code “20 16” in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY status flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write 2016:Erase all blocks D016:Block erase 2016/D016 Block address Status register read SR7=1? or RY/BY=1? NO YES SR5=0? Start NO Erase error YES Write 4016 Erase completed Write Write address Write data Fig. 48 Erase flowchart Status register read SR7=1? or RY/BY=1? NO YES NO SR4=0? Program error YES Program completed Fig. 47 Program flowchart 43 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Status Register Sequencer status (SR7) The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF 16) is input After power-on, and after recover from deep power down mode, the sequencer status is set to “1”(ready). The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. Table 11 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (5016) (2) In the deep power down mode (3) In the power supply off state After a reset, the status register is set to “8016”. Each bit in this register is explained below. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to “1”. The erase status is reset to “0” when cleared. Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to “1”. The program status is reset to “0” when cleared. If “1” is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to “1”. Table 11 Definition of each bit in status register Each bit of SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) 44 Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 49 shows a full sta- tus check flowchart and the action to be taken when each error occurs. Read status register SR4=1 and SR5 =1 ? YES Command sequence error NO SR5=0? NO Block erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. YES SR4=0? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 49 Full status check flowchart and remedial procedure for errors 45 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect function The ROM code protect function is the function inhibit reading out or modifying the contents of the flash memory version by using the ROM code protect control address (FFDB16) during parallel I/O mode. Figure 50 shows the ROM code protect control address (FFDB16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to “0”, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or some other mode to rewrite the contents of the ROM code protect reset bits. ROM code protect control address b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ROMCP Address FFDB16 When reset F F1 6 Function Bit name Bit symbol Reserved bit Always set this bit to “1” ROM code protect level 2 set bit (Note 1, 2) b3 b2 ROMCP2 ROM code protect reset bit (Note 3) b5 b4 ROMCR ROMCP1 ROM code protect level 1 set bit (Note 1) b7 b6 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled Notes 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be changed in parallel input/output mode, they need to be rewritten in serial input/output mode or some other mode. Fig. 50 ROM code protect control address 46 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which are FFD4 16 to FFDA16 . Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 ID1 FFD516 ID2 FFD616 ID3 FFD716 ID4 FFD816 ID5 FFD916 ID6 FFDA16 ID7 FFDB16 ROM cord Protect control Interrupt vector area Fig. 51 ID code store addresses 47 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Parallel I/O Mode Bus Operation Modes The parallel I/O mode is entered by making connections shown in Figure 52 and then turning the Vcc power supply on. Read Address The user ROM is only one block as shown in Figure 44. The block address referred to in this data sheet is the maximum address value of each block. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 44 can be rewritten. The BSEL pin is used to choose between these two areas. The user ROM area is selected by pulling the BSEL input low; the boot ROM area is selected by driving the BSEL input high. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 44. The user ROM area is 32 Kbytes in size. In parallel I/O mode, it is located at addresses 800016 through FFFF16. The boot ROM area is 4 Kbytes in size. In parallel I/O mode, it is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. Functional Outline (Parallel I/O Mode) In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, Write, and Deep Power Down—are selected by the status _____ _____ _____ _____ of the CE, OE, WE, and RP input pins. The contents of erase, program, and other operations are selected by writing a software command. The data, status register, etc. in memory can only be read out by a read after software command input. Program and erase operations are controlled using software commands. The following explains about bus operation modes, software commands, and status register. _____ _____ The Read mode is entered by pulling the OE pin low when the CE _____ _____ pin is low and the WE and RP pins are high. There are two read modes: array, and status register, which are selected by software command input. In read mode, the data corresponding to each software command entered is output from the data I/O pins D 0–D7. The read array mode is automatically selected when the device is powered on or after it exits deep power down mode. Output Disable _____ The output disable mode is entered by pulling the CE pin low and the _____ _____ _____ WE, OE, and RP pins high. Also, the data I/O pins are placed in the high-impedance state. Standby _____ _____ The standby mode is entered by driving the CE pin high when the RP pin is high. Also, the data I/O pins are placed in the high-impedance _____ state. However, if the CE pin is set high during erase or program operation, the internal control circuit does not halt immediately and normal power consumption is required until the operation under way is completed. Write _____ _____ The write mode is entered by pulling the WE pin low when the CE pin _____ _____ is low and the OE and RP pins are high. In this mode, the device accepts the software commands or write data entered from the data I/O pins. A program, erase, or some other operation is initiated depending on the content of the software command entered here. The input data such as address and software command is latched at the _____ _____ rising edge of WE or CE whichever occurs earlier. Deep Power Down _____ The deep power down is entered by pulling the RP pin low. Also, the data I/O pins are placed in the high-impedance state. When the device is freed from deep power down mode, the read array mode is selected and the content of the status register is set to “8016 .” If the _____ RP pin is pulled low during erase or program operation, the operation under way is canceled and the data in the relevant block becomes invalid. Table 12 Relationship between control signals and bus operation modes Pin name Mode Read Array Status register Output disabled Stand by Write Deep power down Note : X can be VIL or VIH. 48 Program Erase Other _____ _____ ______ CE OE WE _____ RP D0 to D7 VIL VIL VIL VIH VIL VIL VIL X VIL VIL VIH X VIH VIH VIH X VIH VIH VIH X VIL VIL VIL X VIH VIH VIH VIH VIH VIH VIH VIL Data output Status register data output High impedance High impedance Command/data input Command input Command input High impedance MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode) Pin name Signal name I/O Function VCC,VSS Power supply input I Apply 5.0 ± 0.5 V to the Vcc pin and 0 V to the Vss pin. CNVSS CNVSS I Connect this pin to Vcc. RESET Reset input I Reset input pin. When reset is held low, more than 20 cycles of clock are required at the XIN pin. X IN Clock input I XOUT Clock output O Connect a ceramic or crystal resonator between the XIN and XOUT pins. When entering an externally drived clock, enter it from XIN and leave XOUT open. AVSS Analog power supply input I Connect AVss to Vss. VREF Reference voltage input I Input AD reference voltage or keep open. P00 to P07 Data I/O D0 to D7 I/O These are data D0–D7 input/output pins. P10 to P17 Address input A8 to A15 I These are address A8–A15 input pins. P20 to P27 Address input A0 to A7 I These are address A0–A7 input pins. P30 BSEL input I This is a BSEL input pin. P31 RP input I This is a RP input pin. P32 WE input I This is a WE input pin. P 33 CE input I This is a CE input pin. P34 OE input I This is a OE input pin. P40 RY/BY output O This is a RY/BY output pin. P41 Input P41 I Enter low signals to this pin. P42 to P44 Input P4 I Input “H” or “L” or keep open. 49 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VCC VSS RY/BY A7 A6 A5 A4 A3 A2 A1 A0 ✽ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mode setup method Signal Value CNVSS VCC P41/INT0 VSS RESET VSS Fig. 52 Pin connection diagram in parallel I/O mode 50 M38507F8SP/FP VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/SCL2/TxD P24/SDA2/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) ✽ Connect oscillator circuit BSEL RP WE CE OE D0 D1 D2 D3 D4 D5 D6 D7 A8 A9 A10 A11 A12 A13 A14 A15 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Software Commands Read Status Register Command (7016) Table 14 lists the software commands. By entering a software command from the data I/O pins (D0 –D7) in Write mode, specify the content of the operation, such as erase or program operation, to be performed. The following explains the content of each software command. When the command code “7016” is written in the first bus cycle, the content of the status register is output from the data I/O pins (D0 –D7) by a read in the second bus cycle. Since the content of the status _____ _____ _____ _____ register is updated at the falling edge of OE or CE, the OE or CE signal must be asserted each time the status is read. The status register is explained in the next section. Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is output from the data I/O pins (D 0–D7). The read array mode is retained intact until another command is written. The read array mode is also selected automatically when the device is powered on and after it exits deep power down mode. Clear Status Register Command (5016) This command is used to clear the bits SR4,SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. Table 14 Software command list (parallel I/O mode) Second bus cycle First bus cycle Command Cycle number Mode Read array Read status register Clear status register Program All block erase Block erase 1 2 1 2 2 2 Write Write Write Write Write Write Data Address (D0 to D7) X(Note 4) X X X X X FF16 7016 5016 4016 2016 2016 Mode Read Write Write Write Data Address (D0 to D7) X SRD(Note 1) WA(Note 2) WD(Note 2) X 2016 BA(Note 3) D016 Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address (Enter the maximum address of each block) 4: X denotes a given address in the user ROM area or boot ROM area. 51 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ____ Program Command (4016) The program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read_____ ing the status register or the RY/BY signal status. When the program starts, the read status register mode is accessed automatically and the content of the status register can be read out from the data bus (D0 –D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16 ) is written. ____ The RY/BY pin is “L” during write operation and “H” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Erase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY signal status . When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY pin is “L” during erase operation and “H” when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Block Erase Command (20 16/D0 16) By writing the command code “2016 ” in the first bus cycle and the confirmation command code “D0 16” in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY signal. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16 ) is written. ____ The RY/BY pin is “L” during block erase operation and “H” when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed. Start Start Write 4016 Write 2016 Write Write address Write data Write Status register read SR7=1? or RY/BY=1? Status register read NO SR7=1? or RY/BY=1? YES YES Program completed Fig. 53 Page program flowchart 52 NO YES NO SR4=0? 2016:Erase all blocks D016:Block erase 2016/D016 Block address Program error SR5=0? NO YES Erase completed Fig. 54 Block erase flowchart Erase error MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Status Register Program Status (SR4) The status register indicates status such as whether an erase operation or a program ended successfully or in error. It can be read under the following conditions. (1) In the read array mode when the read status register command (7016) is written and the block address is subsequently read. (2) In the period from when the program write or auto erase starts to when the read array command (FF16) The program status reports the operating status of the write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. If “1” is written for any of the SR5, SR4 bits, the program erase all blocks, block erase, commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to “1”. The status register is cleared in the following situations. (1) By writing the clear status register command (5016) (2) In the deep power down mode (3) In the power supply off state Table 15 gives the definition of each status register bit. When power is turned on or returning from the deep power down mode, the status register outputs “8016 ”. Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 55 shows a flowchart of the full status check and explains how to remedy errors which occur. ____ Ready/Busy (RY/BY) pin ____ Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. When power is turned on or returning from the deep power down mode, “1” is set for it. This bit is “0” (busy) during the write or erase operations and becomes “1” when these operations ends. The RY/BY pin is an output pin (N-chanel open drain output) which, like the sequencer status (SR7), indicates the operating status of the flash memory. It is “L” level during auto program or auto erase operations and becomes to the high impedance state (ready state) when ____ these operations end. The RY/BY pin requires an external pull-up. Erase Status (SR5) The erase status reports the operating status of the erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Table 15 Status register Each bit of SRD0 bits SR7 (D7) SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” “0” Ready Ended in error Ended in error - Busy Ended successfully Ended successfully - 53 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Read status register SR4=1 and SR5 =1 ? YES Command sequence error NO SR5=0? NO Block erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. YES SR4=0? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the program, all blocks erase, or block erase is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 55 Full status check flowchart and remedial procedure for errors 54 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P4 1(INT0) pin and “H” to the CNVSS pin (when VCC = 4.5 V to 5.5 V, connect to VCC ; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary command mode, set CNVss pin to “L” level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 56 shows the pin connections for the standard serial I/O mode. Serial data I/O uses SI/ O1 data serially in 8-bit units. To use standard serial I/O mode. The operation uses the four SI/O1 __________ pins S CLK, RxD, TxD and SRDY1 (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is input. __________ The TxD pin is for CMOS output. The SRDY1 (BUSY) pin outputs an “L” level when ready for reception and an “H” level when reception starts. In the standard serial I/O mode, only the user ROM area indicated in Figure 44 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Overview of standard serial I/O mode In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (SI/O1). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or pro__________ gram execution, the SRDY1 (BUSY) pin is “H” level. Accordingly, al__________ ways start the next transfer after the S RDY1 (BUSY) pin is “L” level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc. 55 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 16 Pin functions (Flash memory standard serial I/O mode) Pin Name I/O Description VCC,VSS Power input CNVSS CNVSS I Connect to VCC when VCC = 4.5 V to 5.5 V. Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V. RESET Reset input I Reset input pin. While reset is “L” level, a 20 cycle or longer clock must be input to XIN pin. XIN Clock input I XOUT Clock output O Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. AVSS Analog power supply input VREF Reference voltage input I Enter the reference voltage for AD from this pin. P00 to P07 Input port P0 I Input “H” or “L” level signal or open. P10 to P17 Input port P1 I Input “H” or “L” level signal or open. P20 to P23 Input port P2 I Input “H” or “L” level signal or open. P24 RxD input I Serial data input pin P25 TxD output O Serial data output pin P26 SCLK input I Serial clock input pin P27 BUSY output O BUSY signal output pin P30 to P34 Input port P3 I Input “H” or “L” level signal or open. P40, P42 to P44 Input port P4 I Input “H” or “L” level signal or open. P41 Input P41 I Input “H” level signal, when reset is released. 56 Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. Connect AVSS to VSS . MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VCC VSS P41 BUSY SCLK TxD D RxXD R ✽ 2 VPP RESET ✽1 1 2 42 41 3 4 40 39 38 37 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 M38507F8SP/FP VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/SCL2/TxD P24/SDA2/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) Mode setup method Signal Value CNVSS 4.5 to 5.5 V P41 VCC ✽ 3 RESET VSS → VCC Notes 1: Connect oscillator circuit 2: Connect to Vcc when Vcc = 4.5 V to 5.5 V. Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V. 3: It is necessary to apply Vcc only when reset is released. Fig. 56 Connection for serial I/O mode 57 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Software Commands Table 17 lists software commands. In the standard serial I/O mode, erase operations, programs and reading are controlled by transferring software commands via the RxD pin. Software commands are explained here below. Basically, the software commands of the standard serial I/O mode is as same as that of the parallel I/O mode, but it is excluded 1 command of block erase, and it is added 3 command of ID check, download function, version data output function. Table 17 Software commands (Standard serial I/O mode 1) Control command 1st byte transfer 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 Page read FF 16 Address (middle) Address (high) Data output Data output Data output Data output to 259th byte 2 Page program 41 16 Address (middle) Address (high) Data input Data input Data input Data input to 259th byte 3 Erase all blocks A7 16 D016 4 Read status register 70 16 SRD output 5 Clear status register 50 16 6 ID check F5 16 7 Download function 8 Version data output function FA 16 FB 16 When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable SRD1 output Not acceptable Address (middle) Size (high) Size (low) Address (high) Checksum Version data output Version data output Address (low) Version data output ID size ID1 To Data required number input of times Version Version data data output output To ID7 Version data output to 9th byte Acceptable Not acceptable Acceptable Notes 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address high (A16 to A23) must be “0016 ”. 58 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“00 16”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D 0–D7) for the page (256 bytes) specified with addresses A 8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock. SCLK FF16 RxD A8 to A15 A16 to A23 data0 TxD data255 SRDY1(BUSY) Fig. 57 Timing for page read Read Status Register Command Clear Status Register Command This command reads status information. When the “70 16” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. This command clears the bits (SR4–SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. __________ When the clear status register operation ends, the SRDY1 (BUSY) signal changes from the “H” to the “L” level. SCLK SCLK RxD RxD TxD 7016 SRD output SRDY1(BUSY) Fig. 58 Timing for reading the status register SRD1 output 5016 TxD SRDY1(BUSY) Fig. 59 Timing for clearing the status register 59 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A 15 and A 16 to A 23 (“0016 ”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D 0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. __________ When reception setup for the next 256 bytes ends, the S RDY1 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. SCLK 4116 RxD A8 to A15 A16 to A23 data0 data255 TxD SRDY1(BUSY) Fig. 60 Timing for the page program Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A716 ” command code with the 1st byte. (2) Transfer the verify command code “D016 ” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. __________ When block erasing ends, the SRDY1 (BUSY) signal changes from the “H” to the “L” level . The result of the erase operation can be known by reading the status register. SCLK RxD TxD SRDY1(BUSY) Fig. 61 Timing for erasing all blocks 60 A716 D016 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Download Command (4) The program to execute is sent with the 5th byte onward. This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA 16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. SCLK RxD FA16 Data size Data size (low) (high) Check sum Program data Program data TxD SRDY1(BUSY) Fig. 62 Timing for download Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB 16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. SCLK RxD FB16 TxD ‘V’ ‘E’ ‘R’ ‘X’ SRDY1(BUSY) Fig. 63 Timing for version information output 61 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ID Check the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516 ” command code with the 1st byte. (2) Transfer addresses A0 to A 7, A8 to A 15 and A16 to A23 (“0016”) of SCLK RxD F516 D416 FF16 0016 ID size ID1 ID7 TxD SRDY1(BUSY) Fig. 64 Timing for the ID check ID Code sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD4 16 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses. When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command Address FFD416 ID1 FFD516 ID2 FFD616 ID3 FFD716 ID4 FFD816 ID5 FFD916 ID6 FFDA16 ID7 FFDB16 ROM cord Protect control Interrupt vector area Fig. 65 ID code storage addresses 62 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Status Register (SRD) The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 18 gives the definition of each status register bit. After clearing the reset, the status register outputs “8016”. The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Sequencer status (SR7) Program Status (SR4) After power-on and recover from deep power down mode, the sequencer status is set to “1”(ready). The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Erase Status (SR5) Table 18 Status register (SRD) Definition SRD0 bits Status name SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved “1” “0” Ready Terminated in error Terminated in error - Busy Terminated normally Terminated normally - Status Register 1 (SRD1) Check Sum Consistency Bit (SR12) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (70 16). Also, status register 1 is cleared by writing the clear status register command (5016). Table 19 gives the definition of each status register bit. “00 16” is output when power is turned on and the flag status is maintained even after the reset. This flag indicates whether the check sum matches or not when a program is downloaded for execution using the download function. Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. Table 19 Status register 1 (SRD1) SRD1 bits Status name SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits SR9 (bit1) SR8 (bit0) Data reception time out Reserved Definition “1” Update completed Match 00 01 10 11 Time out - “0” Not Update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - 63 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 66 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4=1 and SR5 =1 ? YES Command sequence error NO SR5=0? NO Erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. YES SR4=0? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 to SR4 is set to “1”, none of the program, erase all blocks commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 66 Full status check flowchart and remedial procedure for errors Example Circuit Application for The Standard Serial I/O Mode Figure 67 shows a circuit application for the standard serial I/O mode. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. P 41 Clock input SCLK BUSY output SRDY1 (BUSY) Data input RXD Data output TXD VPP power source input CNVss M38507F8 Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. 2: In this example, the Vpp power supply is supplied from an external source (writer). To use the user’s power source, connect to 4.5 V to 5.5 V. Fig. 67 Example circuit application for the standard serial I/O mode 64 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Flash memory Electrical characteristics Table 20 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00 –P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40 –P44, VREF Input voltage P22, P2 3 Input voltage RESET, XIN Input voltage CNV SS Output voltage P00 –P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40 –P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS . Output transistors are cut off. Ta = 25 °C Ratings –0.3 to 6.5 Unit V –0.3 to VCC +0.3 V –0.3 to 5.8 –0.3 to V CC +0.3 –0.3 to VCC +0.3 V V V –0.3 to V CC +0.3 V –0.3 to 5.8 1000 (Note) 25±5 –40 to 125 V mW °C °C Note: The rating becomes 300 mW at the 42P2R-A/E package. Table 21 Flash memory mode Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Limits Symbol IPP1 IPP2 IPP3 VIL VIH VPP VCC Parameter VPP power source current (read) VPP power source current (program) VPP power source current (erase) “L” input voltage (Note) “H” input voltage (Note) VPP power source voltage VCC power source voltage Conditions Min. Microcomputer mode operation at VCC = 2.7 to 5.5V Microcomputer mode operation at VCC = 2.7 to 3.6V Unit 0 2.0 4.5 Max. 100 60 30 0.8 VCC 5.5 4.5 5.5 V 3.0 3.6 V VPP = VCC VPP = VCC VPP = VCC Typ. µA mA mA V V V Note: Input pins for parallel I/O mode. 65 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER AC Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Table 22 Read-only mode Symbol t RC ta (AD) ta (CE) ta (OE) t CLZ t DF(CE) t OLZ t DF(OE) t PHZ t OH t OEH t PS Parameter Read cycle time Address access time _____ CE access time _____ OE access time _____ Output enable time (after CE) _____ Output floating time (after CE) _____ Output enable time (after OE) _____ Output floating time (after OE) _____ Output floating time (after PR) _____ _____ Output valid time (after CE, OE, address) Write recovery time (before read) _____ RP recovery time Min. 200 Limits Typ. Max. 100 100 80 0 25 0 25 300 0 200 10 Unit ns ns ns ns ns ns ns ns ns ns ns µs Note : Timing measurement condition is showed in Figure 71. _____ Table 23 Read / Write mode (WE control) Symbol t WC t AS t AH t DS t DH t CS t CH t WP t WPH t DAP t DAE t WHRL t PS Parameter Write cycle time Address set up time Address hold time Data set up time Data hold time _____ CE set up time _____ CE hold time _____ WE pulse width “H” write pulse width Program time Erase all blocks time _____ RY/BY delay time _____ RP recovery time Limits Min. 200 100 25 100 25 0 0 100 50 Max. 25 1.5 200 10 Note : The read timing parameter in the command write operation mode is same as that of the read-only mode. Typical value is at VCC = 5.0 V, Ta = 25 °C condition. 66 Typ. Unit ns ns ns ns ns ns ns ns ns µs s ns µs MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Flash memory mode Electrical characteristics (Ta = 25 oC, VCC = 4.5 to 5.5V unless otherwise noted) _____ Table 24 Read / Write mode (CE control) Symbol tWC tAS tAH tDS tDH tWS tWH tCEP tCEPH tDAP tDAE tEHRL tPS Limits Parameter Min. 200 100 25 100 25 0 0 100 50 Write cycle time Address set up time Address hold time Data set up time Data hold time ______ WE set up time ______ WE hold time _____ CE pulse width _____ “H” CE pulse width Program time Erase all blocks time Typ. Unit Max. ns ns ns ns ns ns ns ns ns µs s ns µs 25 1.5 _____ 200 RY/BY delay time _____ RP recovery time 10 Note : The read timing parameter in the command write operation mode is same as that of the read-only mode. Typical value is at V CC = 5.0 V, Ta = 25 °C condition. Table 25 Erase and program operation Parameter Erase all blocks time Block erase time Program time (1byte) Min. Typ. 1.5 1.0 25 Max. Unit s s µs Table 26 VCC power up / power down timing Symbol tVCS Parameter RP = VIH set up time (after rised VCC = V CC min.) _____ Min. 10 Typ. Max. Unit µs Note : Miserase or miswrite may happen, in case of noise pulse due to the power supply on or off is input to the control pins. Therefore disableing the write mode is need for prevent from memory data break at the power supply on or off. 10µs (min.) waiting_____ time is need to initiate read or write operation after V CC rises to VCC min. at power supply on. The memory data is protected owing to keep the RP pin VIL level at power supply off. The _____ _____ RP pin must be kept VIL level for 10µs (min.) after V CC rises to VCC min. at the _____ power supply on. The RP pin must be kept VIL level until the VCC _____ falls to the GND level at power supply off. RP pin doesn't have latch mode, so RP pin must be kept V IH level during read, erase and program operation. 67 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Inhibit read / write Inhibit read / write VCC 5.0V GND tVCS RP VIH VIL CE VIH VIL WE tPS VIH VIL Fig. 68 V CC power up / power down timing 68 tPS Inhibit read / write MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Program VIH Valid Address Address VIL tWC Read status register Write read array command Valid Address tAS ta(CE) tAH VIH CE VIL OE tCS tCH tWP VIH VIL WE ta(OE) tOEH tWPH VIH VIL DATA tDS VIH 40H VIL DIN SRD tDH VoH RY/BY tWHRL VoL tPS VIH RP FFH tDAP VIL _____ Fig. 69 AC wave for program operation (WE control) Program VIH Address tWC tAS Write read array command Valid Address Valid Address VIL Read status register tAH ta(CE) VIH CE VIL OE ta(OE) VIH VIL tCEP tWH tWS tOEH VIH WE VIL tDS VIH DATA 40H DIN SRD FFH VIL tDH VoH RY/BY tEHRL VoL VIH RP tPS tDAP VIL _____ Fig. 70 AC wave for program operation (CE control) 69 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VIH Address CE Valid address VIL tRC VIH ta (AD) VIL OE VIH VIL WE tDF(CE) ta (CE) tOEH tDF(OE) VIH ta (OE) VIL tOH tOLZ DATA VOH RP tCLZ HIGH-Z VOL HIGH-Z Valid output tPS tPHZ VIH VIL Fig. 71 AC wave for read operation and test condition 1.3V AC electrical characteristics test condition 1N914 Input voltage : VIL = 0V, VIH = 5.0V Input signal rising time, falling time : 10ns 3.3k Timing measurement Reference voltage : 1.5V measurement pin CL =100pF Load circuit : 1TTL gate+ CL(100pF ) or Fig. 72 AC electrical characteristics test condition 70 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Read status register Erase VIH Address Valid Address Valid Address VIL tAS tWC tAH ta(CE) VIH CE VIL tCS tCH ta(OE) VIH OE VIL tOEH tDAE tWPH VIH WE VIL tWP 20H VIL tDH tDS VIH DATA Write read array command SRD D0H FFH tWHRL VOH RY/BY VOL tPS RP VIH VIL _____ Fig. 73 AC wave for erase operation (WE control) Read status register Erase VIH Address Valid Address Valid Address VIL tWC CE Write read array command tAH tAS ta(CE) VIH VIL tCEPH tCEP VIH OE ta(OE) tOEH VIL tWS WE tDAE tWH VIH VIL VIH DATA 20H VIL RY/BY tDH tDS SRD D0H FFH tEHRL VOH VOL tPS RP VIH VIL _____ Fig. 74 AC wave for erase operation (CE control) 71 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register A-D Converter The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X IN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Interrupts Instruction Execution Time The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1.” Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H.” 72 NOTES ON USAGE Differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT , XCIN -XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (V CC pin) and GND pin (VSS pin) and between power source pin (V CC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recommended. EPROM Version/One Time PROM Version/ Flash Memory Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (V PP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form ✽1 2. Mark Specification Form ✽2 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. The built-in PROM of the blank One Time PROM version and buitin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS The following are necessary when ordering a PROM programming service: 1. ROM Programming Confirmation Form ✽1 2. Mark Specification Form ✽2 (only special mark with customer’s trade mark logo) 3. Data to be programmed to PROM, in EPROM form (three identical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage. ✽1 Mask ROM Confirmation Forms http://www.infomicom.mesc.co.jp/38000/38ordere.htm ✽2 Mark Specification Forms http://www.infomicom.mesc.co.jp/mela/markform.htm Table 27 Programming adapter Package Name of Programming Adapter 42P4B, 42S1B PCA4738S-42A 42P2R-A/E PCA4738F-42A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 75 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 75 Programming and testing of One Time PROM version 73 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 28 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17 , P20, P21, P24–P27, P30–P34 , P40–P44, VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17 , P20, P21, P24–P27, P30–P34 , P40–P44, XOUT Output voltage P22, P2 3 Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS . Output transistors are cut off. Ratings –0.3 to 6.5 Unit V –0.3 to VCC +0.3 V –0.3 to 5.8 –0.3 to V CC +0.3 –0.3 to VCC +0.3 V V V –0.3 to V CC +0.3 V –0.3 to 5.8 1000 (Note) –20 to 85 –40 to 125 V mW °C °C Ta = 25 °C Note : The rating becomes 300mW at the 42P2R-A/E package. Table 29 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter 8 MHz (high-speed mode) 8 MHz (middle-speed mode), 4 MHz (high-speed mode) VCC Power source voltage VSS VREF AVSS VIA VIH VIH VIL VIL VIL Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage “H” input voltage “H” input voltage AN 0–AN 4 P00–P07, P1 0–P17, P20–P27 , P30–P34, P40 –P44 RESET, XIN , CNVSS “L” input voltage “L” input voltage “L” input voltage P00–P07, P1 0–P17, P20–P27 , P30–P34, P40 –P44 RESET, CNV SS XIN ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) “H” total peak output current “H” total peak output current “L” total peak output current (Note) “L” total peak output current (Note) “L” total peak output current “H” total average output current “H” total average output current “L” total average output current (Note) “L” total average output current (Note) “L” total average output current P00–P07, P10–P17 , P30–P34 P20, P21, P24 –P27, P40–P44 P00–P07, P30–P34 P10–P17 P20–P27,P4 0–P44 (Note) P00–P07, P10–P17 , P30–P34 P20, P21, P24 –P27, P40–P44 P00–P07, P30–P34 P10–P17 P20–P27,P4 0–P44 (Note) Min. 4.0 2.7 Limits Typ. 5.0 5.0 Max. 5.5 5.5 0 2.0 (Note) (Note) (Note) (Note) V VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC V V V V V V V V V –80 –80 80 120 80 –40 –40 40 60 40 mA mA mA mA mA mA mA mA mA mA VCC 0 AVSS 0.8V CC 0.8V CC 0 0 0 Unit Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 74 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 30 Recommended operating conditions (2) (V CC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) Parameter “H” peak output current P00–P07, P10 –P17, P20, P21 , P24–P27, P30 –P34, P40–P44 (Note 1) “L” peak output current (Note 1) P00–P07, P20 –P27, P30–P34, P4 0–P44 “L” peak output current (Note 1) P10–P17 “H” average output current P00–P07, P10 –P17, P20, P21 , P24–P27, P30 –P34, P40–P44 (Note 2) “L” average output current (Note 2) P00–P07, P20 –P27, P30–P34, P4 0–P44 “L” average output current (Note 2) P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. Unit –10 mA 10 20 mA mA –5 mA 5 15 8 4 mA mA MHz MHz Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%. 75 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 31 Electrical characteristics (1) (V CC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– I IH I IH I IH I IL I IL I IL VRAM Parameter “H” output voltage P00–P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40–P44 (Note) “L” output voltage P00–P07 , P20–P27, P30–P34, P40–P44 “L” output voltage P10–P17 Hysteresis CNTR0, CNTR 1, INT 0–INT3 Hysteresis RxD, SCLK ____________ Hysteresis RESET “H” input current P00–P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40–P44 ____________ “H” input current RESET, CNV SS “H” input current XIN “L” input current P00–P07 , P10–P17, P20–P27 P30–P34 , P40–P44 ____________ “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage Test conditions I OH = –10 mA VCC = 4.0–5.5 V I OH = –1.0 mA VCC = 2.7–5.5 V I OL = 10 mA VCC = 4.0–5.5 V I OL = 1.0 mA VCC = 2.7–5.5 V I OL = 20 mA VCC = 4.0–5.5 V I OL = 10 mA VCC = 2.7–5.5 V Min. Typ. V VCC–1.0 V 2.0 V 1.0 V 2.0 V 1.0 V 0.4 V 0.5 V 0.5 VI = VCC 5.0 VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped Unit VCC–2.0 5.0 4 –5.0 –5.0 –4 2.0 Note: P2 5 is measured when the P2 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 76 Max. 5.5 V µA µA µA µA µA µA V MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 32 Electrical characteristics (2) (V CC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ICC Parameter Power source current Limits Test conditions Min. High-speed mode f(XIN) = 8 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN ) = 32.768 kHz Output transistors “off” Except Low-speed mode M38507F8FP/SP f(XIN) = stopped f(XCIN ) = 32.768 kHz M38507F8FP/SP Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Low-speed mode (VCC = 3 V) Except f(XIN) = stopped M38507F8FP/SP f(XCIN ) = 32.768 kHz M38507F8FP/SP Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN) = 8 MHz f(XCIN ) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN ) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Typ. Max. 6.8 13 1.6 60 Unit mA mA 200 µA µA T.B.D. 20 40 µA 20 55 µA µA T.B.D. 5.0 10.0 µA 4.0 7.0 mA 1.5 mA 800 µA 0.1 1.0 µA 10 µA 77 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 33 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Symbol Parameter – – t CONV Resolution Absolute accuracy (excluding quantization error) Conversion time RLADDER I VREF Ladder resistor Reference power source input current I I(AD) A-D port input current 78 Test conditions VREF “on” VREF “off” Limits Min. High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50 Typ. 40 35 150 0.5 Max. 10 ±4 61 200 5.0 5.0 Unit bit LSB 2tc(XIN) µs kΩ µA µA MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 34 Timing requirements (1) (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(Rx D-SCLK1 ) th (SCLK1 -RxD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(S IN2-SCLK2 ) th (SCLK2 -SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR 1 input cycle time CNTR0, CNTR 1 input “H” pulse width CNTR0, CNTR 1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Min. 20 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN ) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 35 Timing requirements (2) (V CC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(Rx D-SCLK1 ) th (SCLK1 -RxD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(S IN2-SCLK2 ) th (SCLK2 -SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR 1 input cycle time CNTR0, CNTR 1 input “H” pulse width CNTR0, CNTR 1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART). 79 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 36 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t WH (SCLK1 ) t WL (SCLK1) t d (SCLK1 -TXD) t v (SCLK1 -TXD) t r (SCLK1 ) t f (SCLK1 ) t WH (SCLK2 ) t WL (SCLK2) t d (SCLK2 -SOUT2) t v (SCLK2 -SOUT2) t f (SCLK2 ) t r (CMOS) t f (CMOS) Parameter Test conditions Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig.76 Limits Min. Typ. tC (SCLK1 )/2–30 tC (SCLK1 )/2–30 Max. 140 –30 30 30 t C(S CLK2)/2–160 t C(S CLK2)/2–160 200 0 10 10 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/S OUT2 and P0 2/S CLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 0015 16) is “0”. 3: The XOUT pin is excluded. Table 37 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t WH (SCLK1 ) t WL (SCLK1) t d (SCLK1-T XD) t v (SCLK1 -TXD) t r (SCLK1 ) t f (SCLK1 ) t WH (SCLK2 ) t WL (SCLK2) t d (SCLK2 -SOUT2) t v (SCLK2 -SOUT2) t f (SCLK2 ) t r (CMOS) t f (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Fig.76 Limits Min. Typ. tC (SCLK1 )/2–50 tC (SCLK1 )/2–50 Max. 350 –30 50 50 t C(S CLK2)/2–240 t C(S CLK2)/2–240 400 0 20 20 50 50 50 Notes 1: When the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/S OUT2 and P0 2/S CLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 0015 16) is “0”. 3: The XOUT pin is excluded. 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100 pF CMOS output Fig. 76 Circuit for measuring output switching characteristics 81 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC(CNTR) tWH(CNTR) CNTR0 CNTR1 tWL(CNTR) 0.8VCC 0.2VCC tWL(INT) tWH(INT) 0.8VCC INT0 to INT3 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN SCLK1 SCLK2 tf 0.2VCC tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.8VCC 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) RXD SIN2 0.8VCC 0.2VCC td(SCLK1-TXD), td(SCLK2-SOUT2) TXD SOUT2 Fig. 77 Timing diagram 82 th(SCLK1-RxD), th(SCLK2-SIN2) tv(SCLK1-TXD), tv(SCLK2-SOUT2) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 42P4B Plastic 42pin 600mil SDIP EIAJ Package Code SDIP42-P-600-1.78 Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy 22 1 21 E 42 e1 c JEDEC Code – Symbol L A1 A A2 D e b1 b2 b SEATING PLANE A A1 A2 b b1 b2 c D E e e1 L 42P2R-A/E Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° Plastic 42pin 450mil SSOP EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code – Weight(g) 0.63 e b2 22 E Recommended Mount Pad F Symbol 1 21 A D G A2 e y A1 b L L1 HE e1 I2 42 Lead Material Alloy 42 A A1 A2 b c D E e HE L L1 z Z1 y c z Z1 Detail G Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – 83 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 42S1B-A Metal seal 42pin 600mil DIP EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code – Weight(g) 1 21 e1 22 E 42 c D A1 L A A2 Symbol Z e b b1 SEATING PLANE 84 A A1 A2 b b1 c D E e e1 L Z Dimension in Millimeters Min Nom Max – – 5.0 – – 1.0 3.44 – – 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 – – 41.1 – 15.8 – – – 1.778 – – 15.24 3.05 – – – – 3.05 HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • • © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 2000. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 3850 GROUP (SPEC. H) DATA SHEET Revision Description Rev. date 1.0 First Edition 000309 1.1 Font errors are revised. 000322 2.0 Page 1; “●Interrupts” of “FEATURES” is revised. 001222 Page 1; Figure 1 is partly revised. Page 6; Table 3 is partly revised. Page 17; Explanations of “INTERRUPTS” are partly revised. Page 23; Figure 20 is partly revised. Page 27; Figure 24 is partly revised. Page 33; Explanations of “RESET CIRCUIT” are partly revised. Page 36; Note 1 into Figure 42 is partly revised. Pages 38 to 71; Explanations of “FLASH MEMORY VERSION” are added. Page 41; Figure 45 is partly revised. Page 72; “EPROM Version/One Time PROM Version/Flash Memory Version” of “NOTES ON USAGE” is added. Page 73; “DATA REQUIRED FOR MASK ORDERS” is added. Page 73; “DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS” is added. Page 73; “ROM PROGRAMMING METHOD” is added. Page 77; Table 32 is partly revised. Page 79; Limit of tw(RESET) into Table 34 is revised. Page 79; Limit of tw(RESET) into Table 35 is revised. (1/1)