Microsemi NX2117CUTR Synchronous pwm controller with current limit, power good & over voltage Datasheet

NX2116/2116A/2116B/2117/2117A
SYNCHRONOUS PWM CONTROLLER WITH
CURRENT LIMIT, POWER GOOD & OVER VOLTAGE
PRELIMINARY DATA SHEET
Pb Free Product
FEATURES
DESCRIPTION
The NX2116/2117 family of products are synchronous n Bus voltage operation from 2V to 25V
Buck controller IC designed for step down DC to DC n Power Good indicator available in NX2116
converter applications. They are optimized to convert n Fixed 300kHz, 600kHz and 1MHz for NX2116 and
300kHz, 600kHz for NX2117 family.
bus voltages from 2V to 25V to as low as 0.8V output
n
Internal Digital Soft Start Function
voltage. The NX2116 and 2117 offer an Enable pin that
n
Less
than 50 nS adaptive deadband
can be used to program the converter's start up voltage
n
Enable
pin to program BUS UVLO for NX2116/2117
using an external divider from bus voltage. These prodn
Programmable
current limit triggers latch out by
ucts operate at fixed internal frequency of 300kHz, exsensing
Rdson
of
cept that NX2116A operates at 600kHz and 2116B at
Synchronous MOSFET
1MHz frequency. These products employ loss-less curn
No negative spike at Vout during startup and
rent limiting protection by sensing the Rdson of synshutdown
chronous MOSFET followed by latch out feature. Feed-
APPLICATIONS
back under voltage triggers Hiccup.
Other features are; 5V gate drive, Power good indica- n
tor, Adaptive deadband control, Internal digital soft start; n
Vcc undervoltage lock out and shutdown capability via n
the enable pin or comp pin.
n
TYPICAL APPLICATION
L2 1uH
Vin1
+12V
Graphic Card on board converters
Memory Vddq Supply
On board DC to DC such as 2V to 3.3V, 2.5V or
1.8V
ADSL Modem
C5
1uF
C3
39uF
Vin2
D1
MBR0530T1
R3
10
+5V
C4
1uF
R5
68k
4
ON
R6
12.4k
R7
10k
C1
33pF
8
C2
1.5nF
7
R4
17.4k
11
R2
16k
EN
Comp
Fb
Gnd
Hdrv
NX2116A
R8 10k 2N3904
1
C7
0.1uF
BST
Vcc
6
OFF
Cin
270uF,18mohm
M1
2
L1 1uH
SW
OCP
10
Ldrv
3
Pgood
5
9
R11 3.7k
M2
Vout
+1.8V,9A
Co
2x (220uF,12mohm)
+5V
R10 1k
R1 20k
R9
2.61k
C8
1nF
Figure 1 - Typical application of 2116
ORDERING INFORMATION
Device
NX2116CMTR
NX2116ACMTR
NX2116BCMTR
NX2117CUTR
NX2117ACUTR
Rev. 3.0
03/14/06
Temperature
0 to 70oC
0 to 70o C
0 to 70o C
0 to 70o C
0 to 70o C
Package
MLPD-10L
MLPD-10L
MLPD-10L
MSOP-10L
MSOP-10L
Frequency
300kHz
600kHz
1MHz
300kHz
600kHz
Pb-Free
Yes
Yes
Yes
Yes
Yes
1
NX2116/2116A/2116B/2117/2117A
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V
BST to GND Voltage ........................................ -0.3V to 35V
SW to GND ...................................................... -2V to 35V
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
NX2116/2116A/2116B
10-LEAD PLASTIC MLPD
NX2117/2117A
10-LEAD PLASTIC MSOP
θ JA ≈ 52o C /W
θJA ≈ 200o C/W
BST 1
BST 1
10 SW
10 SW
9 OCP
HDrv 2
9 OCP
8 COMP
GND 3
8 COMP
VCC 4
7 FB
LDrv 4
7 FB
PGOOD 5
6 EN
VCC 5
6 EN
HDrv 2
LDrv 3
Gnd
(PAD)
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to TA
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Reference Voltage
Ref Voltage
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
VCC Supply Current (Static)
VCC Supply Current
(Dynamic)
VCC
ICC (Static) Outputs not switching
CLOAD=3300pF
ICC
(Dynamic) FS=300kHz
Supply Voltage(VBST)
VBST Supply Current (Static)
IBST (Static) Outputs not switching
TBD
mA
VBST Supply Current
(Dynamic)
IBST
CLOAD=3300pF
(Dynamic) FS=300kHz
TBD
mA
Rev. 3.0
03/14/06
SYM
Test Condition
Min
VREF
TYP
MAX
0.8
0.2
4.5
5
3
TBD
Units
V
%
5.5
V
mA
mA
2
NX2116/2116A/2116B/2117/2117A
PARAMETER
Under Voltage Lockout
VCC-Threshold
VCC-Hysteresis
Oscillator
Frequency
Ramp-Amplitude Voltage
Max Duty Cycle
Min Duty Cycle
Error Amplifiers
Transconductance
Input Bias Current
EN & SS
Soft Start time
Enable HI Threshold
Enable Hysterises
High Side Driver
(CL=3300pF)
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time
Fall Time
Deadband Time
SYM
Test Condition
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
FS
2116, 2117
2116A,2117A
2116B
VRAMP
Min
TYP
MAX
Units
3.8
4
0.2
4.2
V
V
300
600
1000
1.5
95
0
Ib
Tss
NX2116,NX2117
NX2116A, NX2117A
NX2116B
kHz
kHz
kHz
V
%
%
2000
10
umho
nA
6.8
mS
1.25
150
V
mV
Rsource(Hdrv)
I=200mA
0.9
ohm
Rsink(Hdrv)
I=200mA
0.65
ohm
THdrv(Rise)
VBST-VSW=4.5V
THdrv(Fall)
VBST-VSW=4.5V
Tdead(L to Ldrv going Low to Hdrv going
High, 10%-10%
H)
50
50
30
ns
ns
ns
Rsource(Ldrv)
I=200mA
0.9
ohm
Rsink(Ldrv)
I=200mA
0.5
ohm
50
50
30
ns
ns
ns
40
uA
90
%
5
%
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time
Fall Time
Deadband Time
OCP Adjust
OCP current
Power Good(Pgood)
Threshold Voltage as % of
Vref
Hysteresis
Rev. 3.0
03/14/06
TLdrv(Rise)
10% to 90%
TLdrv(Fall)
90% to 10%
Tdead(H to SW going Low to Ldrv going
L)
High, 10% to 10%
FB ramping up
3
NX2116/2116A/2116B/2117/2117A
PIN DESCRIPTIONS
PIN SYMBOL
VCC
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to
and connected to this pin and ground pin. The maximum rating of this pin is 5V.
BST
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is
placed as close as possible to and connected to these pins and respected SW pins.
GND
Ground pin.
FB
OCP
SW
Rev. 3.0
03/14/06
PIN DESCRIPTION
This pin is the error amplifier inverting input. It is connected via resistor divider to the
output of the switching regulator to set the output DC voltage. When FB pin voltage is
lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching
cycles.
This pin is connected to the drain of the external low side MOSFET via resistor and is the
input of the over current protection(OCP) comparator. An internal current source 40uA is
flown to the external resistor which sets the OCP voltage across the Rdson of the low side
MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is
reached the Hdrv and Ldrv pins are latched out.
This pin is connected to source of high side FET and provides return path for the high side
driver. It is also used to hold the low side driver low until this pin is brought low by the
action of high side turning off. LDRV can only go high if SW is below 1V threshold .
HDRV
High side gate driver output.
LDRV
Low side gate driver output.
PGOOD
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI
state.
EN
A resistor divider is connected from the respective switcher BUS voltages to these pins
that holds off the controller's soft start until this threshold is reached. An external low cost
Transistor can be connected to this pin for external enable control.
COMP
This pin is the output of error amplifier and is used to compensate the voltage control
feedback loop. This pin can also be used to perform a shutdown if pulled lower than 0.3V.
4
NX2116/2116A/2116B/2117/2117A
BLOCK DIAGRAM
VCC
FB
Hiccup Logic
0.6V
Bias
Generator
1.25V
OC
0.8V
UVLO
BST
POR
START
HDRV
EN
1.25/1.15
SW
OC
Control
Logic
START 0.8V
PWM
OSC
Digital
start Up
VCC
ramp
S
R
LDRV
Q
OC
FB
0.6V
CLAMP
COMP
START
40uA
1.3V
CLAMP
OCP
Latch Out
OCP
comparator
GND
FB
0.9Vref
/0.85Vref
PGOOD
Figure 2 - Simplified block diagram of the NX2116
Rev. 3.0
03/14/06
5
NX2116/2116A/2116B/2117/2117A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN
- Input voltage
VOUT
- Output voltage
IOUT
- Output current
=
DVRIPPLE - Output voltage ripple
FS
∆IRIPPLE =
VIN -VOUT VOUT 1
×
×
LOUT
VIN FS
...(2)
12V-1.8V 1.8v
1
×
×
= 2.55A
1uH
12V 600kHz
Output Capacitor Selection
- Working frequency
Output capacitor is basically decided by the
DIRIPPLE - Inductor current ripple
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
Design Example
VIN = 12V
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
VOUT=1.8V
condition is determined by equation(3).
The following is typical application for NX2116A,
the schematic is figure 1.
FS=600kHz
∆VRIPPLE = ESR × ∆IRIPPLE +
IOUT=9A
DVRIPPLE <=20mV
Where ESR is the output capacitors' equivalent
DVDROOP<=100mV @ 9A step
series resistance,COUT is the value of output capacitors.
Typically when large value capacitors are selected
Output Inductor Selection
such as Aluminum Electrolytic,POSCAP and OSCON
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
output current. This is a design freedom which can be
decided by design engineer according to various appli-
ESR desire =
cation requirements. The inductor value can be calcu-
IRIPPLE =k × IOUTPUT
...(4)
tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP
...(1)
where k is between 0.2 to 0.4.
Select k=0.3, then
12V-1.8V 1.8V
1
×
×
LOUT =
0.3 × 9A 12V 600kHz
LOUT =0.94uH
Choose inductor from COILCRAFT DO3316P102HC with L=1uH is a good choice.
Current Ripple is recalculated as
∆VRIPPLE 20mV
=
= 7.8m Ω
∆IRIPPLE
2.55A
If low ESR is required, for most applications, mul-
lated by using the following equations:
V -V
V
1
L OUT = IN OUT × OUT ×
∆IRIPPLE
VIN
FS
∆IRIPPLE
8 × FS × COUT ...(3)
2R5TPE220MC with 12mΩ are chosen.
N =
E S R E × ∆ IR I P P L E
∆ VR IPPLE
...(5)
Number of Capacitor is calculated as
N=
12mΩ× 2.56A
20mV
N =1.5
The number of capacitor has to be round up to a
integer. Choose N =2.
If ceramic capacitors are chosen as output ca
Rev. 3.0
03/14/06
6
NX2116/2116A/2116B/2117/2117A
pacitors, both terms in equation (3) need to be evalu-
of output capacitor. For low frequency capacitor such
ated to determine the overall ripple. Usually when this
as electrolytic capacitor, the product of ESR and ca-
type of capacitors are selected, the amount of capaci-
pacitance is high and L ≤ L crit is true. In that case, the
tance per single unit is not sufficient to meet the tran-
transient spec is dependent on the ESR of capacitor.
sient specification, which results in parallel configuration of multiple capacitors .
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆VRIPPLE
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
N=
2.56A
= 2mΩ× 2.55A +
8 × 600kHz × 100uF
= 10.4mV
ESR E × ∆Istep
∆Vtran
is specified as:
∆VDROOP <∆VTRAN @ step load DISTEP
transient is composed of two sections. One Section is
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR E × CE
 V
 OUT
Lcrit =
high enough, the overshoot can be estimated as the following equation.
...(6)
where τ is the a function of capacitor, etc.
L crit =
The selected inductor is 1uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitors is
τ=
=
...(7)
where
ESR × COUT × VOUT ESR E × C E × VOUT
=
∆Istep
∆Istep
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
L × ∆ I step
VOUT
− ESR E × C E
1µH × 9A
− 12m Ω × 220µ F = 2.36us
1.8V
N=
...(8)
ESR E × C E × VOUT
=
∆Istep
12mΩ × 220µF × 1.8V
= 0.56µH
9A
DISTEP
transient load, if assuming the bandwidth of system is
L ≥ L crit
...(10)
If the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is
input, output voltage. For example, for the overshoot,
if
L ≥ L crit
used, the critical inductance is given as
a function of the inductor, output capacitance as well as
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR × COUT
 V
 OUT
if
For example, assume voltage droop during tran-
dependent on the ESR of capacitor, the other section is
VOUT
× τ2
2 × L × COUT
...(9)
sient is 100mV for 9A load step.
During the transient, the voltage droop during the
∆Vovershoot = ESR × ∆Istep +
VOUT
× τ2
2 × L × C E × ∆Vtran
where
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
when load from high load to light load with a
+
ESR E × ∆Istep
∆Vtran
+
VOUT
× τ2
2 × L × CE × ∆Vtran
12mΩ × 9A
+
100mV
1.8V
× (2.36us)2
2 ×1µH × 220µF ×100mV
= 1.3
=
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
The number of capacitors has to satisfied both ripple
voltage droop or overshoot is only dependent on the ESR
and transient requirement. Overall, we can choose N=2.
Rev. 3.0
03/14/06
7
NX2116/2116A/2116B/2117/2117A
It should be considered that the proposed equation is based on ideal case, in reality, the droop or over-
FZ1 =
1
2 × π × R 4 × C2
...(11)
FZ2 =
1
2 × π × (R 2 + R3 ) × C3
...(12)
FP1 =
1
2 × π × R3 × C3
...(13)
shoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
1
FP2 =
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin.Ideally,the
Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency,
phase margin greater than 50o and the gain crossing
0dB with -20dB/decade. Power stage output capacitors
usually decide the compensator type. If electrolytic
capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, be-
...(14)
C × C2
2 × π × R4 × 1
C1 + C2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 4.
The transfer function of type III compensator for
transconductance amplifier is given by:
Ve
1 − gm × Z f
=
VOUT
1 + gm × Zin + Z in / R1
For the voltage amplifier, the transfer function of
compensator is
Ve
−Z f
=
VOUT
Zin
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R 4>>2/gm. And it would be desirable if R 1||R2||R3>>1/gm can be met at the same time.
cause the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensator should be chosen.
A. Type III compensator design
Zin
R3
R2
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
C3
sate the system with type III compensator. The following figures and equations show how to realize the type III
C2
R4
Fb
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen-
Zf
C1
Vout
gm
Ve
R1
Vref
compensator by transconductance amplifier.
Figure 3 - Type III compensator using
transconductance amplifier
Rev. 3.0
03/14/06
8
NX2116/2116A/2116B/2117/2117A
Case 1:
FLC<FO<FESR
Choose R1=16kΩ.
3. Set zero FZ2 = FLC and Fp1 =FESR .
Gain(db)
4. Calculate R4 and C3 with the crossover
frequency at 1/10~ 1/5 of the switching frequency. Set
power stage
FO=50kHz.
FLC
40dB/decade
C3 =
1
1 1
×( - )
2 ×π× R2 Fz2 Fp1
1
1
1
×(
)
2 × π × 20kΩ 7.6kHz 60.3kHz
=916pF
=
loop gain
FESR
20dB/decade
R4 =
VOSC 2 × π × FO × L
×
× Cout
Vin
C3
1.5V 2 × π × 50kHz × 1uH
×
× 440uF
12V
1nF
=17.2k Ω
=
compensator
Choose C3=1nF, R 4=17.4kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
FZ1 FZ2
FO FP1
FP2
double pole by equation (11).
C2 =
Figure 4 - Bode plot of Type III compensator
1
2 × π × FZ1 × R 4
1
2 × π × 0.75 × 7.6kHz × 17.4kΩ
= 1.6nF
=
Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<FESR, and FO<=1/10~1/5Fs.
1.Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
=
1
2 × π × L OUT × C OUT
1
2 × π × 1uH × 440uF
= 7.6kHz
Choose C2=1.5nF.
6. Calculate C 1 by equation (14) with pole F p2 at
half the switching frequency.
C1 =
1
2 × π × R 4 × FP2
1
2 × π × 17.4kΩ × 300kHz
= 30pF
=
Choose C1=33pF
FESR =
1
2 × π × ESR × C OUT
1
=
2 × π × 6m Ω × 440uF
= 60.3kHz
2. Set R2 equal to 20kΩ.
R1=
Rev. 3.0
03/14/06
R 2 × VREF
20k Ω × 0.8V
=
= 16k Ω
VOUT -VREF
1.8V-0.8V
7. Calculate R 3 by equation (13).
R3 =
1
2 × π × FP1 × C3
1
2 × π × 60.3kHz × 1nF
= 2.64k Ω
=
Choose R3=2.61kΩ.
9
NX2116/2116A/2116B/2117/2117A
Case 2:
FLC<FESR<FO
2. Set R2 equal to 10kΩ.
Gain(db)
R1 =
R 2 × VREF
10kΩ × 0.8V
=
= 8kΩ
VOUT -VREF
1.8V-0.8V
Choose R1=8kΩ.
power stage
3. Set zero FZ2 = FLC and Fp1 =FESR .
FLC
40dB/decade
4. Calculate C3 .
C3 =
FESR
1
1 1
)
×(
2 × π × R2
Fz2 Fp1
1
1
1
)
×(
2 × π × 10kΩ 2.9kHz 8.2kHz
=3.5nF
=
loop gain
20dB/decade
Choose C3=3.3nF.
5. Calculate R3 .
compensator
R3 =
1
2 × π × FP1 × C3
1
2 × π × 8.2kHz × 3.3nF
= 5.9k Ω
=
FZ1 FZ2 FP1 FO
FP2
Choose R3 =5.9kΩ.
6. Calculate R4 with FO=60kHz.
Figure 5 - Bode plot of Type III compensator
(FLC<FESR<FO)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown
as the following steps. Here two SANYO MV-WG1500
with 13 mΩ is chosen as output capacitor.
1. Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
=
R4 =
VOSC 2 × π × FO × L R2 × R3
×
×
Vin
ESR
R 2 + R3
1.5V 2 × π × 60kHz × 1uH 10kΩ × 5.9kΩ
×
×
12V
6.5mΩ
10kΩ + 5.9kΩ
=26.9kΩ
=
Choose R4=26.7kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
C2 =
1
2 × π × 0.75 × 2.9kHz × 26.7k Ω
= 2nF
=
1
2 × π × L OUT × C OUT
1
2 × π × 1uH × 3000uF
= 2.9kHz
Choose C2=2.2nF.
6. Calculate C 1 by equation (14) with pole F p2 at
half the switching frequency.
C1 =
FESR =
1
2 × π × ESR × COUT
1
2 × π × 6.5mΩ × 3000uF
= 8.2kHz
=
Rev. 3.0
03/14/06
1
2 × π × FZ1 × R 4
1
2 × π × R 4 × FP2
1
2 × π × 26.7kΩ × 300kHz
= 20pF
=
Choose C1=22pF.
10
NX2116/2116A/2116B/2117/2117A
B. Type II compensator design
If the electrolytic capacitors are chosen as power
Vout
stage output capacitors, usually the Type II compensator can be used to compensate the system.
R2
Fb
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 7. R3 and C1
introduce a zero to cancel the double pole effect. C2
Ve
gm
R1
R3
Vref
C2
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero lo-
C1
cation and constant gain.
Gain=gm ×
R1
× R3
R1+R2
... (15)
Figure 7 - Type II compensator with
1
Fz =
2 × π × R3 × C1
Fp ≈
transconductance amplifier
... (16)
1
2 × π × R3 × C2
... (17)
For this type of compensator, FO has to satisfy
FLC<FESR<<FO<=1/10~1/5Fs.
The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 1.8V,
output inductor is 1uH, output capacitors are two 1500uF
Gain(db)
power stage
with 13mΩ electrolytic capacitors.
40dB/decade
1.Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
loop gain
Gain
1
=
20dB/decade
compensator
1
2 × π × L OUT × C OUT
2 × π × 1uH × 3000uF
= 2.9kHz
FESR =
1
2 × π × ESR × C OUT
1
2 × π × 6.5m Ω × 3000uF
= 8.2kHz
=
FZ FLC FESR
FO FP
2.Set R2 equal to 1kΩ.
Figure 6 - Bode plot of Type II compensator
R1 =
R 2 × VREF
1kΩ × 0.8V
=
= 800Ω
VOUT -VREF 1.8V-0.8V
Choose R1=806Ω.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=60kHz.
4.Calculate R3 value by the following equation.
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NX2116/2116A/2116B/2117/2117A
Vout
4.Calculate R3 value by the following equation.
R2
V
2 × π × FO × L 1 VOUT
R 3 = OSC ×
×
×
Vin
RESR
gm VREF
1.5V 2 × π × 60kHz × 1uH
1
×
×
12V
6.5m Ω
2.0mA/V
1.8V
×
0.8V
=8.15kΩ
Fb
R1
=
Vref
Voltage divider
Figure 8 - Voltage divider
Choose R3 =8.2kΩ.
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
1
C1 =
2 × π × R 3 × Fz
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk ca-
1
=
2 × π × 8.2k Ω × 0.75 × 2.9kHz
=8.9nF
pacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are de-
Choose C1=8.2nF.
cided by voltage rating and RMS current rating. The RMS
6. Calculate C 2 by setting compensator pole Fp
current in the input capacitors can be calculated as:
at half the swithing frequency.
IRMS = IOUT × D × 1- D
1
C2=
π × R 3 × Fs
D=
1
π × 8 .2k Ω × 3 0 0 k H z
=129pF
=
VOUT
VIN
...(19)
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation (19),
the result of input RMS current is 3.2A.
For higher efficiency, low ESR capacitors are rec-
Choose C1=120pF.
ommended. One Sanyo OS-CON 16SP180M 16V 180uF
Output Voltage Calculation
20mΩ with 3.4A RMS rating is chosen as input bulk
capacitors.
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at
Power MOSFETs Selection
0.8V. The divider consists of two ratioed resistors so
The power stage requires two N-Channel power
that the output voltage applied at the Fb pin is 0.8V when
MOSFETs. The selection of MOSFETs is based on
the output voltage is at the desired value. The following
maximum drain source voltage, gate source voltage,
equation and picture show the relationship between
maximum current rating, MOSFET on resistance and
VOUT , VREF and voltage divider..
power dissipation. The main consideration is the power
R 1=
R 2 × VR E F
V O U T -V R E F
...(18)
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3709Z are
used. They have the following parameters: VDS=30V,RDSON
=6.5mΩ,QGATE =17nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
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NX2116/2116A/2116B/2117/2117A
sired voltage decided by the feedback resistor divider.
PHCON =IOUT 2 × D × RDS(ON) × K
PTOTAL =PHCON + PLCON
...(20)
Vbus
+
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
POR
OFF
R1
ON
dependency. As a result, RDS(ON) should be selected for
R2
10k
EN
1.25V/
1.15V
Digital
start
up
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3709Z datasheet. Conduction loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover con-
Figure 9 - Enable and Shut down the NX2116
with Enable pin.
duction at the switching transition. The total switching
loss can be approximated.
resistor divider at Enable pin. For example, if the input
1
PSW = × VIN × IOUT × TSW × FS
...(21)
2
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Switching loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS
The start up of NX2116 can be programmed through
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is the low
side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
Soft Start and Enable
NX2116 has digital soft start for switching control-
bus voltage is12V and we want NX2116 starts when Vbus
is above 9V. We can select using the following equation.
R1 =
(9V − 1.25V) × R2
1.25V
The NX2116 can be turned off by pulling down the
Enable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin is below 1.25V, the digital soft start is reset to zero. In addition, all the high side
and low side driver is off and no negative spike will be
generated during the turn off.
Over Current Protection
Over current protection is achieved by sensing current through the low side MOSFET. An internal current
source of 40uA flows through an external resistor connected from OCP pin to SW node sets the over current
protection threshold. When synchronous FET is on, the
voltage at node SW is given as
VSW =-IL × RDSON
ler and has one enable pin for this start up. When the
The voltage at pin OCP is given as
Power Ready (POR) signal is high and the voltage at
IOCP × ROCP +VSW
enable pin is above 1.25V the internal digital counter
When the voltage is below zero, the over current
starts to operate and the voltage at positive input of Error
occurss as shown in figure 10.
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the deRev. 3.0
03/14/06
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NX2116/2116A/2116B/2117/2117A
vbus
I OCP
40uA
OCP
SW
R OCP
OCP
comparator
Figure 10 - Over current protection
The over current limit can be set by the following
equation
ISET =
IOCP × ROCP
K × RDSON
If MOSFET RDSON=6.5mΩ, the worst case thermal
consideration K=1.5 and the current limit is set at 15A,
then
ROCP =
ISET × K × RDSON 15A × 1.5 × 6.5m Ω
=
= 3.656kΩ
IOCP
40uA
Choose ROCP=3.7kΩ
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the
connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to
reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more sensitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.
Rev. 3.0
03/14/06
14
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