Intersil EL5256IY <1mv voltage offset, 600mhz amplifier Datasheet

EL5156, EL5157, EL5256, EL5257
®
Data Sheet
June 15, 2006
FN7386.3
<1mV Voltage Offset, 600MHz Amplifiers
Features
The EL5156, EL5157, EL5256, and EL5257 are 600MHz
bandwidth -3dB voltage mode feedback amplifiers with DC
accuracy of <0.01%, 1mV offsets and 40kV/V open loop
gains. These amplifiers are ideally suited for applications
ranging from precision measurement instrumentation to high
speed video and monitor applications demanding the very
highest linearity at very high frequency. Capable of operating
with as little as 6.0mA of current from a single supply ranging
from 5V to 12V and dual supplies ranging from ±2.5V to
±5.0V, these amplifiers are also well suited for handheld,
portable and battery-powered equipment. With their
capability to output as much as 140mA, any member of this
family is comfortable with demanding load conditions.
• 600MHz -3dB bandwidth, 240MHz 0.1dB bandwidth
Single amplifiers are available in SOT-23 packages and
duals in a 10 Ld MSOP package for applications where
board space is critical. Additionally, singles and duals are
available in the industry-standard 8 Ld SO package. All parts
operate over the industrial temperature range of -40°C to
+85°C.
• 700V/µs slew rate
• <1mV input offset
• Very high open loop gains 92dB
• Low supply current = 6mA
• 140mA output current
• Single supplies from 5V to 12V
• Dual supplies from ±2.5V to ±5V
• Fast disable on the EL5156 and EL5256
• Low cost
• Pb-free plus anneal available (RoHS compliant)
Applications
• Imaging
• Instrumentation
• Video
• Communications devices
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5156, EL5157, EL5256, EL5257
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
EL5156IS
5156IS
-
8 Ld SO
MDP0027
EL5156IS-T7
5156IS
7”
8 Ld SO
MDP0027
EL5156IS-T13
5156IS
13”
8 Ld SO
MDP0027
EL5156ISZ (Note)
5156ISZ
-
8 Ld SO (Pb-free)
MDP0027
EL5156ISZ-T7 (Note)
5156ISZ
7”
8 Ld SO (Pb-free)
MDP0027
EL5156ISZ-T13 (Note)
5156ISZ
13”
8 Ld SO (Pb-free)
MDP0027
EL5157IW-T7
BHAA
7” (3K pcs)
5 Ld SOT-23
MDP0038
EL5157IW-T7A
BHAA
7” (250 pcs)
5 Ld SOT-23
MDP0038
EL5157IWZ-T7 (Note)
BAAM
7” (3K pcs)
5 Ld SOT-23 (Pb-free)
MDP0038
EL5157IWZ-T7A (Note)
BAAM
7” (250 pcs)
5 Ld SOT-23 (Pb-free)
MDP0038
EL5256IY
BAHAA
-
10 Ld MSOP
MDP0043
EL5256IY-T7
BAHAA
7”
10 Ld MSOP
MDP0043
EL5256IY-T13
BAHAA
13”
10 Ld MSOP
MDP0043
EL5257IS
5257IS
-
8 Ld SO
MDP0027
EL5257IS-T7
5257IS
7”
8 Ld SO
MDP0027
EL5257IS-T13
5257IS
13”
8 Ld SO
MDP0027
EL5257IY
BAJAA
-
8 Ld MSOP
MDP0043
EL5257IY-T7
BAJAA
7”
8 Ld MSOP
MDP0043
EL5257IY-T13
BAJAA
13”
8 Ld MSOP
MDP0043
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
EL5157
(5 LD SOT-23)
TOP VIEW
EL5156
(8 LD SO)
TOP VIEW
NC 1
IN- 2
IN+ 3
+
VS- 4
8 CE
OUT 1
7 VS+
VS- 2
6 OUT
IN+ 3
INA+ 1
4 IN-
EL5257
(8 LD SO)
TOP VIEW
10 INA-
+
VS- 3
CEB 4
+ -
5 NC
EL5256
(10 LD MSOP)
TOP VIEW
CEA 2
5 VS+
+
-
OUTA 1
9 OUTA
INA- 2
8 VS+
INA+ 3
7 OUTB
VS- 4
8 VS+
7 OUTB
+
6 INB+
5 INB+
6 INB-
INB+ 5
2
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VS and VS- . . . . . . . . . . . . . . . . . . . . 13.2V
Maximum Slewrate from VS+ and VS- . . . . . . . . . . . . . . . . . . . 1V/µs
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5V to VS +0.5V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, CE = +5V, RF = RG = 562Ω, RL = 150Ω, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +1, RL = 500Ω, CL = 4.7pF
600
MHz
AV = +2, RL = 150Ω
180
MHz
GBWP
Gain Bandwidth Product
RL = 150Ω
210
MHz
BW1
0.1dB Bandwidth
AV = +2
70
MHz
SR
Slew Rate
VO = -3.2V to +3.2V, AV = +2, RL = 150Ω
640
V/µs
VO = -3.2V to +3.2V, AV = +1, RL = 500Ω
700
V/µs
15
ns
500
tS
0.1% Settling Time
AV = +1
dG
Differential Gain Error
AV = +2, RL = 150Ω
0.005
%
dP
Differential Phase Error
AV = +2, RL = 150Ω
0.04
°
VN
Input Referred Voltage Noise
12
nV/√Hz
IN
Input Referred Current Noise
5.5
pA/√Hz
DC PERFORMANCE
VOS
Offset Voltage
TCVOS
Input Offset Voltage Temperature
Coefficient
Measured from TMIN to TMAX
AVOL
Open Loop Gain
VO is from -2.5V to 2.5V
-1
10
0.5
1
mV
-3
µV/°C
40
kV/V
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
Guaranteed by CMRR test
CMRR
Common Mode Rejection Ratio
VCM = 2.5V to -2.5V
80
108
IB
Input Bias Current
EL5156 & EL5157
-1
-0.4
+1
µA
EL5256 & EL5257
-600
-200
+600
nA
-250
100
+250
nA
10
25
MΩ
1
pF
IOS
Input Offset Current
RIN
Input Resistance
CIN
Input Capacitance
-2.5
+2.5
V
dB
OUTPUT CHARACTERISTICS
VOUT
IOUT
Output Voltage Swing
Peak Output Current
RL = 150Ω to GND
±3.4
±3.6
V
RL = 500Ω to GND
±3.6
±3.8
V
RL = 10Ω to GND
±80
±140
mA
200
ns
ENABLE (EL5156 and EL5256 ONLY)
tEN
Enable Time
3
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, CE = +5V, RF = RG = 562Ω, RL = 150Ω, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
tDIS
Disable Time
IIHCE
CE Pin Input High Current
CE = VS+
IILCE
CE Pin Input Low Current
CE = VS-
VIHCE
CE Input High Voltage for Power-down
VILCE
CE Input Low Voltage for Power-up
MIN
TYP
MAX
UNIT
300
5
ns
0
-1
µA
13
25
µA
VS+ -1
V
VS+ -3
V
SUPPLY
ISON
Supply Current - Enabled (per amplifier)
ISOFF
PSRR
No load, VIN = 0V, CE = +5V
5.1
6.0
6.9
mA
Supply Current - Disabled (per amplifier) No load, VIN = 0V, CE = 5V
5
13
25
µA
Power Supply Rejection Ratio
75
90
DC, VS = ±3.0V to ±6.0V
dB
Typical Performance Curves
4
135
RL=150Ω
CL=4.7pF
2
45
AV=+2
-2
AV=+10
AV=+5
-4
-6
100K
1M
AV=+5
AV=+2
AV=+1
0
PHASE (°)
NORMALIZED GAIN (dB)
RL=150Ω
CL=4.7pF
-45
AV=+10
-135
-225
10M
100M
-315
100K
1G
1M
FREQUENCY (Hz)
1G
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE PHASE FOR VARIOUS GAINS
4
5
VS=±5V
AV=+2
2 RF=RG=562Ω
AV=+1
RL=500Ω
RL=500Ω
0
RL=150Ω
-2
RL=750Ω
RL=50Ω
-4
1M
CL=27pF
3
GAIN (dB)
NORMALIZED GAIN (dB)
100M
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL FREQUENCY RESPONSE - GAIN
-6
100K
10M
10M
100M
CL=4.7pF
1
-1
CL=1pF
-3
1G
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RL
4
CL=10pF
-5
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
5
16
AV=+2
RL=500Ω
3 RF=RG=500Ω
AV=+2
RL=150Ω
12 RF=RG=562Ω
CL=22pF
CL=10pF
GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves (Continued)
1
CL=8.2pF
-1
CL=33pF
CL=10pF
8
4
CL=0pF
-3
0
CL=0pF
1M
10M
100M
-4
100K
1G
1M
FREQUENCY (Hz)
10M
100M
1G
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
5
5
AV=+5
RL=500Ω
3
CL=82pF
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
CL=180pF
CL=4.7pF
-5
100K
CL=100pF
CL=68pF
-1
CL=22pF
-3
-5
100K
1M
10M
100M
AV=+1
RL=500Ω
3 CL=4.7pF
±2.0V
±4.0V
-1
±5.0V
-3
-5
100K
1G
±3.0V
1
1M
FREQUENCY (Hz)
100M
1G
FIGURE 8. FREQUENCY RESPONSE vs POWER SUPPLY
5
4
AV=+1
RL=500Ω
3 CL=4.7pF
NORMALIZED GAIN (dB)
AV=+1
1
-1
AV=+2
-3
-5
100K
10M
FREQUENCY (Hz)
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
NORMALIZED GAIN (dB)
CL=100pF
AV=+5
1M
10M
100M
FREQUENCY (Hz)
FIGURE 9. EL5256 SMALL SIGNAL FREQUENCY
RESPONSE FOR VARIOUS GAINS
5
1G
VS=±5V
RF=620Ω
2 RL=150Ω
AV=-1
0
AV=-2
-2
-4
-6
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 10. SMALL SIGNAL INVERTING FREQUENCY
RESPONSE FOR VARIOUS GAINS
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Typical Performance Curves (Continued)
4
5
AV=+1
CL=4.7pF
RL=500Ω
2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
AV=+1
CL=0.2pF
RL=300Ω
0
RL=150Ω
-2
-4
-6
100K
1M
10M
100M
3
RL=500Ω
RL=200Ω
1
-1
RL=50Ω
-3
RL=100Ω
-5
100K
1G
1M
FREQUENCY (Hz)
FIGURE 11. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RL
CIN=12pF
CIN=8.2pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1G
4
AV=+2
RL=500Ω
3 CL=4.7pF
RF=500Ω
CIN=4.7pF
1
CIN=0.2pF
-1
CIN=0pF
-3
-5
100K
1M
10M
AV=+5
CL=4.7pF
2 RL=500Ω
RF=102Ω
-2
CIN=0pF
CIN=4.7pF
-4
1M
AV=+2
CL=4.7pF
4 RL=500Ω
NORMALIZED GAIN (dB)
6
VS=±5V
AV=+2
2 RL=150Ω
CL=4.7pF
RF=RG=1kΩ
0
RF=RG=562Ω
RF=RG=500Ω
RF=RG=250Ω
-4
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 15. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RF AND RG
6
100M
FIGURE 14. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CIN
4
-2
10M
FREQUENCY (Hz)
FIGURE 13. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CIN
RF=RG=350Ω
CIN=47pF
CIN=22pF
-6
100K
100M
CIN=68pF
0
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100M
FIGURE 12. EL5256 SMALL SIGNAL FREQUENCY
RESPONSE FOR VARIOUS RL
5
-6
100K
10M
FREQUENCY (Hz)
RF=RG=3kΩ
RF=RG=2kΩ
RF=RG=1kΩ
2
0
RF=RG=500Ω
-2
-4
100K
RF=RG=200Ω
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 16. EL5256 SMALL SIGNAL FREQUENCY
RESPONSE FOR VARIOUS RF AND RG
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Typical Performance Curves (Continued)
3
5
AV=+2
RL=200Ω
CL=4.7pF
+15dBm
1
-20dBm
+10dBm
-1
+17dBm
+20dBm
-3
-5
100K
1M
10M
100M
AV=+1
RL=500Ω
3 CL=4.7pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
CH1
1
CH2
-1
-3
-5
100K
1G
1M
FREQUENCY (Hz)
FIGURE 17. LARGE SIGNAL FREQUENCY RESPONSE FOR
VARIOUS INPUT AMPLITUDES
100M
1G
FIGURE 18. CHANNEL TO CHANNEL FREQUENCY
RESPONSE
0
700
AV=+5
RL=500Ω
-20 CL=4.7pF
AV=+1, RL=500Ω, CL=5pF
600
500
AV=+1, RL=150Ω
BW (MHz)
CROSS TALK (10dB)
10M
FREQUENCY (Hz)
-40
-60
400
300
AV=+2, RL=150Ω
200
-80
100
-100
100K
1M
10M
100M
0
4.5
1G
5.5
6.5
7.5
FIGURE 19. EL5256 CROSS TALK vs FREQUENCY CHANNEL
A TO B & B TO A
9.5
10.5 11.5 12.5
FIGURE 20. BANDWIDTH vs SUPPLY VOLTAGE
4
1K
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
AV=+5
CL=4.7pF
NORMALIZED GAIN (dB)
8.5
VS (V)
FREQUENCY (Hz)
2
RL=1kΩ
0
RL=500Ω
-2
RL=100Ω
RL=50Ω
-4
-6
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 21. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RL
7
100
VN
10
IN
1
100K
1M
10M
10M
100M
100M
1G
FREQUENCY (Hz)
FIGURE 22. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Typical Performance Curves (Continued)
1K
-20
AV=+2
RL=0Ω
RG=RF=400Ω
100
IMPEDANCE (Ω)
CMRR (dB)
-40
-60
-80
10
1
-100
-120
100
1K
10K
100K
1M
10M
0.01
1K
100M
10K
100K
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 24. OUTPUT IMPEDANCE
FIGURE 23. CMRR
-10
6.1
VS=±5V
AV=+2
-30 RL=150Ω
6
5.9
5.8
-50
IS (mA)
DISABLED ISOLATION (dB)
1M
-70
IS-
5.7
IS+
5.6
5.5
-90
5.4
-110
100K
1M
10M
100M
5.3
4.5
1G
5.5
6.5
7.5
FREQUENCY (Hz)
FIGURE 25. INPUT TO OUTPUT ISOLATION vs FREQUENCY DISABLE
8.5
9.5
10.5
11.5
VS (V)
FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE
0.8
AV=+2
RL=500Ω
SUPPLY=±5V ±12.3mA
DISABLE
322ns
AV=+1
CL=5pF
RL=500Ω
0.6
PEAKING (dB)
ENABLE
192ns
0.7
0.5
0.4
0.3
0.2
0.1
TIME (400ns/DIV)
0
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
VS (V)
FIGURE 27. ENABLE/DISABLE RESPONSE
8
FIGURE 28. PEAKING vs SUPPLY VOLTAGE
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Typical Performance Curves (Continued)
AV=+2
RL=500Ω
SUPPLY=±5V ±12.3mA
OUTPUT=200mVP-P
VOUT (40mV/DIV)
VOUT (40mV/DIV)
AV=+2
RL=500Ω
SUPPLY=±5V ±12.3mA
OUTPUT=200mVP-P
0
RISE
20%-80%
∆T=2.025ns
0
FALL
80%-20%
∆T=1.7ns
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 29. SMALL SIGNAL RISE TIME
FIGURE 30. SMALL SIGNAL FALL TIME
AV=+2
RL=500Ω
SUPPLY=±5V ±12.3mA
OUTPUT=2.0VP-P
VOUT (400mV/DIV)
VOUT (400mV/DIV)
AV=+2
RL=500Ω
SUPPLY=±5V ±12.3mA
OUTPUT=2.0VP-P
0
RISE
20%-80%
∆T=1.657ns
0
FALL
80%-20%
∆T=1.7ns
TIME (2ns/DIV)
TIME (2ns/DIV)
FIGURE 31. LARGE SIGNAL RISE TIME
1.8
FIGURE 32. LARGE SIGNAL FALL TIME
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.6
1.4
1.2 1.136W
SO8
θJA=110°C/W
1 870mW
0.8
MSOP10
θJA=115°C/W
0.6 543mW
0.4
SOT23-5
θJA=230°C/W
0.2
0
1
781mW
0.8
SO8
θJA=160°C/W
0.6
488mW
0.4 486mW
SOT23-5
θJA=256°C/W
MSOP10
θJA=115°C/W
0.2
0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
9
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
EL5156 Product Description
The EL5156, EL5157, EL5256, and EL5257 are wide
bandwidth, single or dual supply, low power and low offset
voltage feedback operational amplifiers. Both amplifiers are
internally compensated for closed loop gain of +1 or greater.
Connected in voltage follower mode and driving a 500Ω
load, the -3dB bandwidth is about 610MHz. Driving a 150Ω
load and a gain of 2, the bandwidth is about 180MHz while
maintaining a 600V/µs slew rate. The EL5156 and EL5256
are available with a power-down pin to reduce power to
17µA typically while the amplifier is disabled.
Input, Output and Supply Voltage Range
The EL5156 and EL5157 families have been designed to
operate with supply voltage from 5V to 12V. That means for
single supply application, the supply voltage is from 5V to
12V. For split supplies application, the supply voltage is from
±2.5V to ±5V. The amplifiers have an input common mode
voltage range from 1.5V above the negative supply (VS- pin)
to 1.5V below the positive supply (VS+ pin). If the input
signal is outside the above specified range, it will cause the
output signal to be distorted.
The outputs of the EL5156 and EL5157 families can swing
from -4V to 4V for VS = ±5V. As the load resistance becomes
lower, the output swing is lower. If the load resistor is 500Ω,
the output swing is about -4V at a 4V supply. If the load
resistor is 150Ω, the output swing is from -3.5V to 3.5V.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the amplifier's phase
margin is reduced. This causes ringing in the time domain
and peaking in the frequency domain. Therefore, RF can't be
very big for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
For gain of +1, RF = 0 is optimum. For the gains other than
+1, optimum response is obtained with RF between 500Ω to
750Ω.
The EL5156 and EL5157 families have a gain bandwidth
product of 210MHz. For gains ≥5, its bandwidth can be
predicted by the following equation:
Gain × BW = 210MHz
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. The dG and dP for these families are about 0.006%
and 0.04%, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance.
Driving Capacitive Loads and Cables
The EL5156 and EL5157 families can drive 27pF loads in
parallel with 500Ω with less than 5dB of peaking at gain of
+1. If less peaking is desired in applications, a small series
resistor (usually between 5Ω to 50Ω) can be placed in series
with the output to eliminate most peaking. However, this will
reduce the gain slightly. If the gain setting is greater than 1,
the gain resistor RG can then be chosen to make up for any
gain loss which may be created by the additional series
resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5156 and EL5256 can be disabled and their output
placed in a high impedance state. The turn-off time is about
330ns and the turn-on time is about 130ns. When disabled,
the amplifier's supply current is reduced to 17µA typically,
thereby effectively eliminating the power consumption. The
amplifier's power-down can be controlled by standard TTL or
CMOS signal levels at the ENABLE pin. The applied logic
signal is relative to VS- pin. Letting the ENABLE pin float or
applying a signal that is less than 0.8V above VS- will enable
the amplifier. The amplifier will be disabled when the signal
at ENABLE pin is above VS+ -1.5V.
Output Drive Capability
The EL5156 and EL5157 families do not have internal short
circuit protection circuitry. They have a typical short circuit
current of 95mA and 70mA. If the output is shorted
indefinitely, the power dissipation could easily overheat the
die or the current could eventually compromise metal
integrity. Maximum reliability is maintained if the output
current never exceeds ±40mA. This limit is set by the design
of the internal metal interconnect. Note that in transient
applications, the part is robust.
Power Dissipation
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
10
With the high output drive capability of the EL5152 and
EL5153 families, it is possible to exceed the 125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for an application to
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------Θ JA
Where:
TJMAX = Maximum junction temperature
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
n
V OUTi
∑ ( VS – VOUTi ) × ---------------R Li
PD MAX = V S × I SMAX +
i=1
For sinking:
n
∑ ( VOUTi – VS ) × ILOADi
PD MAX = V S × I SMAX +
i=1
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
N = number of amplifiers (max = 2)
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail. See Figure 37 for a complete tuned power supply
bypass methodology.
11
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Application Circuits
Sullen Key High Pass Filter
Sullen Key Low Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the EL5152. A derivation of the transfer function is provided
for convenience (See Figure 35).
V2
5V
K = 1+
L1
1
V1
R2C2s + 1
Vo
V1 − Vi
Vo − Vi
K
1 + − V1 +
=0
1
R1
R2
C1s
K
H(s) =
R1C1R2C2s 2 + ((1 − K )R1C1 + R1C2 + R21C2)s + 1
1
H( jw ) =
2
1 − w R1C1R2C2 + jw ((1 − K )R1C1 + R1C2 + R2C2)
R5
C3
1kΩ
C5
1nF
1nF
C1
1nF
R1
R2
+
V1
1kΩ
1kΩ C2
1nF
-
V+
R7
1kΩ
V-
1
wo =
R1C1R2C2
1
Q=
R1C1
R1C2
R2C2
(1 − K )
+
+
R2C2
R2C1
R1C1
1kΩ
TUNED POWER
BYPASS NETWORK
Holp = K
VOUT
RB
RA
1kΩ
RB
RA
Vo = K
10µH
TUNED POWER
BYPASS NETWORK
Again this useful filter benefits from the characteristics of the
EL5152. The transfer function is very similar to the low pass
so only the results are presented (See Figure 36).
C5
1nF
R6
C4
1kΩ
1nF
L1
10µH
V3
5V
Holp = K
1
wo =
RC
1
Q=
3 −K
Equations simplify if we let all
components be equal R=C
FIGURE 35. SULLEN KEY LOW PASS FILTER
12
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
V2
5V
L1
10µH
TUNED POWER
BYPASS NETWORK
R5
C3
1kΩ
C5
1nF
1nF
R1
C1
Holp = K
1nF
wo =
R2
+
V1
1kΩ
1kΩ C2
1nF
-
V+
1
R1C1R2C2
VOUT
V-
1
Q=
R7
1kΩ
R1C1
R1C2
R2C2
(1 − K )
+
+
R2C2
R2C1
R1C1
RB
1kΩ
RA
1kΩ
C5
TUNED POWER
BYPASS NETWORK
1nF
R6
1kΩ
Holp =
C4
K
4 −K
2
wo =
RC
1nF
L1
10µH
Q=
Equations simplify if we let
all components be equal R=C
2
4 −K
V3
5V
FIGURE 36. SULLEN KEY HIGH PASS FILTER
Differential Output Instrumentation Amplifier
The addition of a third amplifier to the conventional three
amplifier instrumentation amplifier introduces the benefits of
differential signal realization, specifically the advantage of
using common mode rejection to remove coupled noise and
ground potential errors inherent in remote transmission. This
configuration also provides enhanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
e1
A1
+
-
R3
R3
A3
R2
+
RG
R3
R3
R3
R3
A4
R2
A2
e2
+
+
R3
e o3 = – ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
eo3
+
REF
eo
eo4
R3
e o4 = ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
e o = – 2 ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
2f C1, 2
BW = ----------------A Di
13
A Di = – 2 ( 1 + 2R 2 ⁄ R G )
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwidth and high accuracy of the EL5152.
The operation of the circuit is very straightforward. As the
strain variable component resistor in the balanced bridge is
subjected to increasing strain, its resistance changes,
14
resulting in an imbalance in the bridge. A voltage variation
from the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain is
converted into an output voltage.
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
15
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
6
N
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
Rev. E 3/00
3
NOTES:
D
2X
SYMBOL
1. Plastic or metal protrusions of 0.25mm maximum per side are
not included.
C
A2
SEATING
PLANE
3. This dimension is measured at Datum Plane “H”.
A1
0.10 C
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
NX
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
c
L
16
0.25
0° +3°
-0°
FN7386.3
June 15, 2006
EL5156, EL5157, EL5256, EL5257
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. C 6/99
0.10 C
N LEADS
0.08 M C A B
b
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
A
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN7386.3
June 15, 2006
Similar pages