Si9135 New Product Vishay Siliconix Si9135 SMBus Multi-Output Power-Supply Controller FEATURES • • • • • • • • Up to 95% Efficiency 3% Total Regulation (Each Controller) 5.5-V to 30-V Input Voltage Range 3.3-V, 5-V, and 12-V Outputs 200-kHz/300-kHz Low-Noise Frequency Operation Precision 3.3-V Reference Output 30 mA Linear Regulator Output SMBUS Interface • High Efficiency Pulse Skipping Mode Operation at Light Load • Only Three Inductors Required*No Transformer • LITTLE FOOT® Optimized Output Drivers • Internal Soft-Start • Synchronizable • Minimal External Control Components • 28-Pin SSOP Package DESCRIPTION The Si9135 is a current-mode PWM and PSM converter controller, with two synchronous buck converters (3.3 V and 5 V) and a flyback (non-isolated buck-boost) converter (12 V). Designed for portable devices, it offers a total five power outputs (three tightly regulated dc/dc converter outputs, a precision 3.3-V reference and a 5-V LDO output). It requires minimum external components and is capable of achieving conversion efficiencies approaching 95%. Along with the SMBUS interface, the Si9135 provides programmable output selection capability. The Si9135 is available in a 28-pin SSOP package and specified to operate over the extended commercial (0°C to 90°C) temperature range. FUNCTIONAL BLOCK DIAGRAM FaxBack 408-970-5600, request 70817 www.siliconix.com S-60752—Rev. B, 05-Apr-99 1 Si9135 Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36 V PGND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 V VL to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 V BST3, BST5, BSTFY to GND . . . . . . . . . . . . . . . . . . . -0.3 V to +36 V DH3 to LX3, DH5 to LX5, DHFY to LXFY . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (BSTX +0.3 V) Continuous Power Dissipation (TA = 90°C)a 28-Pin SSOPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 mW VL Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 90°C LX3 to BST3; LX5 to BST5; LXFY to BST . . . . . . . . . . . -6.5 V to 0.3 V Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -40°C to 125°C Inputs/Outputs to GND (SYNC, CS3, CS5, CSP, CSN) . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . . . . 300°C SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V a. Device mounted with all leads soldered or welded to PC board. DL3, DL5, DLFY to PGND . . . . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) b. Derate 9.52 mW/°C above 90°C. Notes Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS Limits Test Conditions Parameter VIN = 15 V , IVL = IREF = 0 mA TA = 0°C to 90°C, All Converters ON Mina Typb Maxa Unit VIN = 6 to 30 V, 0 < VCS3 - VFB3 < 90 mV 3.23 3.33 3.43 V 3.3-V Buck Controller Total Regulation (Line, Load, and Temperature) Line Regulation VIN = 6 to 30 V ±0.5 Load Regulation 0 < VCS3 - VFB3 < 90 mV ±0.5 Current Limit Bandwidth Phase Margin VCS3 - VFB3 90 125 160 % mV L = 10 µH, C = 330 µF 50 kHz RSENSE = 20 mΩ 65 ° 5-V Buck Controller Total Regulation (Line, Load, and Temperature) VIN = 6 to 30 V, 0 < VCS5 - VFB5 < 90 mV 4.88 5.03 5.18 Line Regulation VIN = 6 to 30 V ±0.5 Load Regulation 0 < VCS5 - VFB5 < 90 mV ±0.5 Current Limit Bandwidth Phase Margin VCS5 - VFB5 90 125 160 V % mV L = 10 µH, C = 330 µF 50 kHz RSENSE = 20 mΩ 65 ° 12-V Flyback Controller Total Regulation (Line, Load, and Temperature) VIN = 6 to 30 V, 0 < VCSP - VCSN < 300 mV 11.4 12.0 12.6 Line Regulation VIN = 6 to 30 V ±0.5 Load Regulation 0 < VCSP - VFBN < 300 mV ±0.5 Current Limit Bandwidth Phase Margin VCSP - VCSN 330 410 500 V % mV L = 10 µH, C = 100 µF 10 kHz RSENSE = 100 mΩ, Ccomp = 120 pF 65 ° Internal Regulator VL Output VL Fault Lockout Voltage All Converters OFF, VIN >5.5 V, 0 <IL <30 mA 4.7 5.5 3.6 4.2 VL Fault Lockout Hysteresis VL /FB5 Switchover Voltage VL /FB5 Switchover Hysteresis S-60752—Rev. B, 05-Apr-99 2 75 4.2 mV 4.7 75 V V mV FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 Vishay Siliconix New Product SPECIFICATIONS Limits Test Conditions VIN = 15 V , IVL = IREF = 0 mA TA = 0°C to 90°C, All Converters ON Mina Typb Maxa Unit No External Load 3.24 3.30 3.36 V 0 to 1 mA 30 75 mV Supply Current–Shutdown All Converters OFF, No Load 35 60 Supply Current–Operation All Converters ON, No Load, FOCS = 200 kHz 1100 1800 Parameter Reference REF Output REF Load Regulation Supply Current µA Oscillator Oscillator Frequency SYNC tied to REF 270 300 330 SYNC tied to GND or VL 180 200 220 SYNC High-Pulse Width 200 SYNC Low-Pulse Width 200 nsec SYNC Rise/Fall Range 200 SYNC VIL 0.8 VL - 0.5 SYNC VIH Oscillator SYNC Range Maximum Duty Cycle kHz 250 400 SYNC tied to GND or VL 92 95 SYNC tied to REF 89 92 V kHz % Outputs Gate Driver Sink/Source Current (Buck) Gate Driver On-Resistance (Buck) Gate Driver Sink/Source Current (Flyback) Gate Driver On-Resistance (Flyback) DL3, DH3, DL5, DH5 Forced to 2 V 1 High or Low 2 DHFY, DLFY Forced to 2 V 0.2 High or Low A 7 Ω A 15 Ω SCL, SDA VIL VIH 0.6 1.4 V Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. FaxBack 408-970-5600, request 70817 www.siliconix.com S-60752—Rev. B, 05-Apr-99 3 Si9135 Vishay Siliconix New Product PIN CONFIGURATION ORDERING INFORMATION Part Number Temperature Range VOUT Si9135LG 0 to 90°C 3.3 V, 5 V, 12 V PIN DESCRIPTION Pin Number Symbol Description 1 CS3 2 FBFY Current sense input for 3.3-V buck. 3 BSTFY Boost capacitor connection for flyback converter. 4 DHFY Gate-drive output for flyback high-side MOSFET. Feedback for flyback. 5 LXFY Inductor connection for flyback converter. 6 DLFY Gate-drive output for flyback low-side MOSFET. 7 CSP Current sense positive input for flyback converter. 8 CSN Current sense negative input for flyback converter. 9 GND Analog ground. 10 COMP Flyback compensation connection, if required. 11 REF 12 SYNC 3.3-V internal reference. 13 SCL SMBUS clock line. 14 SDA SMBUS data line. Oscillator synchronization inputs. 15 CS5 Current sense input for 5-V buck controller. 16 DH5 Inductor connection for buck 5-V. 17 LX5 Gate-drive output for 5-V buck high-side MOSFET. 18 BST5 Boost capacitor connection for 5-V buck converter. 19 DL5 20 PGND 21 FB5 22 VL 5-V logic supply voltage for internal circuitry. 23 VIN Input voltage 24 DL3 Gate-drive output for 3.3-V buck low-side MOSFET. 25 BST3 Boost capacitor connection for 3.3-V buck converter. 26 LX3 Inductor connection for 3.3-V buck low-side MOSFET. 27 DH3 Gate-drive output for 3.3-V buck high-side MOSFET. 28 FB3 Feedback for 3.3-V buck. S-60752—Rev. B, 05-Apr-99 4 Gate-drive output for 5-V buck low-side MOSFET. Power ground. Feedback for 5-V buck. FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 New Product Vishay Siliconix TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED) FaxBack 408-970-5600, request 70817 www.siliconix.com S-60752—Rev. B, 05-Apr-99 5 Si9135 Vishay Siliconix New Product TYPICAL WAVEFORMS S-60752—Rev. B, 05-Apr-99 6 FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 New Product Vishay Siliconix TYPICAL WAVEFORMS FaxBack 408-970-5600, request 70817 www.siliconix.com S-60752—Rev. B, 05-Apr-99 7 Si9135 Vishay Siliconix New Product STANDARD APPLICATION CIRCUIT FIGURE 1. S-60752—Rev. B, 05-Apr-99 8 FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 Vishay Siliconix New Product are high. The output stages of devices connected to the bus must have an open drain or open collector in order to perform the wired AND function. Data on the SMBus can be transferred at a clock rate up to 100 kHz. Si9135 is a slave with SMBus address of 0110000. SMBUS Specification SMBus: The System Management Bus is a two-wire interface through which simple power related chips can communicate with the rest of the system. It uses I2C as its backbone. Both SDA and SCL are bidirectional lines, connected to a positive voltage via a pull-up resistor. When the bus is free, both lines SMBUS TRUTH TABLE State D7 D6 D5 D4 D3 D2 D1 D0 Shutdown 0 0 0 X X X X X Buck3 On 1 0 0 X X X X X Buck5 On 0 1 0 X X X X X Flyback On 0 0 1 X X X X X Buck3, Buck5 On 1 1 0 X X X X X Buck3, Flyback On 1 0 1 X X X X X Buck5, Flyback on 0 1 1 X X X X X All On 1 1 1 X X X X X Notes a. Positive logic level is used b. X: don’t care SMBUS ELECTRICAL SPECIFICATION (Test Conditions: V+ = 5.5 to 30 V, TA = O°C) Symbol Parameter Min Max Units VIL Data, Clock Input Low Voltage -0.5 0.6 VIH Data, Clock Input High Voltage 1.4 5.5 VOL Data, Clock Output Low Voltage 0.4 ILEAK Input Leakage ±1 µA Min Max Units 100 kHz V SMBUS AC SPECIFICATIONS Symbol Parameter FSMB SMBus Operation Frequency 10 TBUF Bus free time between Stop and Start 4.7 THD Data Hold Time 300 TSU Data Setup Time 250 TLOW Clock Low Period 4.7 THIGH Clock High Period 4.0 TF Clock/Data Fall Time 300 TR Clock/Data Rise Time 1000 FaxBack 408-970-5600, request 70817 www.siliconix.com µs ns 50 µs ns S-60752—Rev. B, 05-Apr-99 9 Si9135 Vishay Siliconix New Product TIMING DIAGRAMS FIGURE 2. Start-Up Timing Sequence S-60752—Rev. B, 05-Apr-99 10 FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 New Product Vishay Siliconix DETAILED FUNCTIONAL BLOCK DIAGRAM FIGURE 3. Buck Block Diagram FIGURE 4. PWM Flyback Block Diagram FaxBack 408-970-5600, request 70817 www.siliconix.com S-60752—Rev. B, 05-Apr-99 11 Si9135 Vishay Siliconix New Product DETAILED FUNCTIONAL BLOCK DIAGRAM FIGURE 5. Complete Si9135 Block Diagram DESCRIPTION OF OPERATION Start-up Sequence Si9135 is normally controlled by its SMBus interface after VIN is applied. Initially, if there is no incoming SMBus control command, it comes up in its default power on sequence, first the LDO 5 V will come up within its tolerance, and then the precision 3.3-V reference will come up. Immediately afterwards, the oscillator will begin and 3.3-V BUCK converter will turn on and then 5-V BUCK converter and at last 12-V FLYBACK converter. If Si9135 receives any SMBus controlling command after LDO 5 V is established, the designated converters will be allowed to turn on or off independently depending on the command received. In the event of all three converters are turned off, the oscillator will be turned off, the total system would only draw 35-µA supply current. Each converter can soft-start separately. The integrated internal soft-start circuitry for each converter gradually increases the inductor maximum peak current during softstart period (approximately 4 msec), preventing excessive currents being drawn from the input during startup. The softstart is controlled by initial default start up sequence or incoming SMBus command. Si9135 converters a 5.5-V to 30-V input voltage to five outputs, two BUCK (step-down) high current, PWM, switch- S-60752—Rev. B, 05-Apr-99 12 mode supplies, one at 3.3 V and one at 5 V, one FLYBACK 12-V PWM switch-mode supply, one precision 3.3-V reference and one 5-V Low Drop Out linear regulator output. Switchmode supply output current capabilities depend on external components (can exceed 10 A). With typical application shown on the application diagram, the two BUCK converters deliver 4 A and the FLYBACK converters deliver 0.25 A. The recommended load current for precision 3.3-V reference output is less than 1 mA, the recommended load current for 5-V LDO output current is less than 30 mA. In order to maximize the power efficiency, when the 5-V BUCK converter supply is above 4.5 V, the BUCK converter’s output is internal connected to LDO output. Buck Converter Operation The 3.3-V and 5-V buck converters are both current-mode PWM and PSM (during light load operation) regulators using high-side bootstrap n-channel and low-side n-channel MOSFETs. At light load conditions, the converters switch at a lower frequency than the clock frequency, seen like some clock pulses between the actual switching are skipped, this operating condition is defined as pulse-skipping. The operation of the converter(s) switching at clock frequency is defined as normal operation. FaxBack 408-970-5600, request 70817 www.siliconix.com Si9135 New Product Vishay Siliconix Normal Operation: Buck Converters Normal Operation: Flyback Converter In normal operation, the buck converter high-side MOSFET is turned on with a delay (known as break-before-make time tBBM), after the rising edge of the clock. After a certain on time, the high-side MOSFET is turned off and then after a delay (tBBM), the low-side MOSFET is turned on until the next rising edge of the clock, or the inductor current reaches zero. The tBBM (approximately 25 ns to 60 ns), has been optimized to guarantee the efficiency is not adversely affected at the high switching frequency and a specified minimum to account for variations of possible MOSFET gate capacitances. In normal operation mode, the two MOSFETs are turned on at the rising edge of the clock, and then turned off. The on time is controlled internally to provide excellent load, line, and temperature regulation. The flyback converter has load, line and temperature regulation well within 0.5%. During the normal operation, the high-side MOSFET switch on-time is controlled internally to provide excellent line and load regulation over temperature. Both buck converters should have load, line, regulation to within 0.5% tolerance. Pulse Skipping: Buck Converters When the buck converter switching frequency is less than the internal clock frequency, its operation mode is defined as pulse skipping mode. During this mode, the high-side MOSFET is turned on until VCS-VFB reaches 20 mV, or the on time reaches its maximum duty ratio. After the high-side MOSFET is turned off, the low-side MOSFET is turned on after the tBBM delay, which will remain on until the inductor current reaches zero. The output voltage will rise slightly above the regulation voltage after this sequence, causing the controller to stay idle for the next one, or several clock cycles. When the output voltage falls slightly below the regulation level, the high-side MOSFET will be turned on again at the next clock cycle. With the converter remaining idle during some clock cycles, the switching losses are reduced in order to preserve conversion efficiency during the light output current condition. Current Limit: Buck Converters When the buck converter inductor current is too high, the voltage across pin CS3(5) and pin FB3(5) exceeds approximately 120 mV, the high-side MOSFET would be turned off instantaneously regardless of the input, or output condition. The Si9135 features clock cycle by clock cycle current limiting capability. Flyback Converter Operation Designed mainly for PCMCIA or EEPROM programming, the Si9135 has a 12-V output non-isolated buck boost converter, called for brevity a flyback. It consists of two n-channel MOSFET switches that are turned on and off in phase, and two diodes. Similar to the buck converter, during the light load conditions, the flyback converter will switch at a frequency lower than the internal clock frequency, which can be defined as pulse skipping mode (PSM); otherwise, it is operating in normal PWM mode. FaxBack 408-970-5600, request 70817 www.siliconix.com Pulse Skipping: Flyback Converter Under the light load conditions, similar to the buck converter, the flyback converter will enter pulse skipping mode. The MOSFETs will be turned on until the inductor current increases to such a level that the voltage across the pin CSP and pin CSN reaches 100 mV, or the on time reaches the maximum duty cycle. After the MOSFETs are turned off, the inductor current will conduct through two diodes until it reaches zero. At this point, the flyback converter output will rise slightly above the regulation level, and the converter will stay idle for one or several clock cycle(s) until the output falls back slightly below the regulation level. The switching losses are reduced by skipping pulses and so the efficiency during light load is preserved. Current Limit: Flyback Converter Similar to the buck converter; when the voltage across pin CSP and pin CSN exceeds 410-mV typical, the two MOSFETs will be turned off regardless of the input and output conditions. SMBus Commands After completion of startup, Si9135’s converters can be individually or as a group commanded on or off using a code word on the SMBus, as detailed in the SMBus Truth Table. The command sequence is: A. Receive a start bit, which is a falling edge on the SDA line while the SCL line is high. B. Receive a one-byte address, which for Si9135 is 01100000. C. Send an acknowledge bit. D. Receive a one-byte command. E. Send an acknowledge bit. F. Receive a stop bit, which is a rising edge on the SDA line while the SCL line is high. This is a total of 20 bits, which at the maximum clock frequency of 100 kHz translates into 200 µsec before any change in the status of Si9135 ban be accomplished. If Si9135 receives a command to turn on (respectively, off) a converter that is already on (respectively, off) it shall not falsely command the converter off (respectively, on). Si9135 must be able to receive a stop command at any time during a command sequence. If Si9135 receives a stop command during a command sequence, it must not change the state of any converter, and must be ready to receive the next command sequence. S-60752—Rev. B, 05-Apr-99 13 Si9135 Vishay Siliconix New Product Grounding There are two separate grounds on the Si9135, analog signal ground (GND) and power ground (PGND). The purpose of two separate grounds is to prevent the high currents on the power devices (both external and internal) from interfering with the analog signals. The internal components of Si9135 have their grounds tied (internally) together. These two grounds are then tied together (externally) at a single point, to ensure Si9135 noise immunity. This separation of grounds should be maintained in the external circuitry, with the power ground of all power devices being returned directly to the input capacitors, and the small signal ground being returned to the GND pin of Si9135. ON/OFF Function Logic-low shuts off the appropriate section by disabling the gate drive stage. High-side and low-side gate drivers are turned off when ON/OFF pins are logic-low. Logic-high enables the DH and DL pins. Stability Buck Converters In order to simplify designs, the Si9135 requires no specified external components except load capacitors for stability control. Meanwhile, it achieves excellent regulation and S-60752—Rev. B, 05-Apr-99 14 efficiency. The converters are current mode control, with a bandwidth substantially higher than the LC tank dominant pole frequency of the output filter. To ensure stability, the minimum capacitance and maximum ESR values are: V REF C LOAD ≥ ------------------------------------------------------------2π × V OUT × R CS × BW V OUT × R CS ESR ≤ ------------------------------VREF Where VREF = 3.3 V, VOUT is the output voltage (5 V or 3.3 V), Rcs is the current sensing resistor in ohms and BW = 50 khz With the components specified in the application circuit (L = 10 µH, RCS = 0.02 Ω, COUT = 330 µF, ESR approximately 0.1 Ω), the converter should have a bandwidth at approximately 50 kHz, with minimum phase margin of 65°, and dc gain above 50 dB. Other Outputs The Si9135 also provides a 3.3-V reference which can be external loaded up to 1 mA, as well as, a 5-V LDO output which can be loaded 30 mA, or even more depending on the system application. When the 5-V buck converter is turned on, the 5-V LDO output is shorted with the 5-V buck converter output, so its loading capability is substantially increased. For stability, the 3.3-V reference output requires a 1-µF capacitor, and 5-V LDO output requires a 4.7-µF capacitor. FaxBack 408-970-5600, request 70817 www.siliconix.com