IDT IDT7134SA55C High-speed 4k x 8 dual-port static sram Datasheet

IDT7134SA/LA
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
Description
Features
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The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the user’s responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a
very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
Dual-Port typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MILPRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
High-speed access
– Military: 25/35/45/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
– IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Functional Block Diagram
R/WL
CEL
R/WR
CER
OEL
OER
COLUMN
I/O
I/O0L- I/O7L
A0L- A11L
LEFT SIDE
ADDRESS
DECODE
LOGIC
COLUMN
I/O
MEMORY
ARRAY
I/O0R- I/O7R
RIGHT SIDE
ADDRESS
DECODE
LOGIC
A0R- A11R
2720 drw 01
JUNE 1999
1
DSC-2720/9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
8
A2L
A3L
9
A4L
A5L
A6L
R/WR
A10R
N/C
A11R
N/C
52 51 50 49 48 47
46
1
A0R
11
12
43
42
A2R
A3R
IDT7134J
J52-1(4)
41
40
A4R
52-Pin PLCC
39
38
A6R
A7R
37
36
A8R
15
16
Top View(5)
17
18
I/O6R
I/O4R
I/O5R
A5R
A9R
N/C
I/O7R
2720 drw 03
A10R
OER
I/O2R
I/O3R
I/O0R
I/O1R
A1R
A0R
8
48 47 46 45 44 43
42
41
A3L
9
40
A2R
A4L
10
39
A3R
A5L
11
38
A4R
37
A5R
36
A6R
35
A7R
34
A8R
A1L
A2L
7
13
A8L
1
IDT7134L48 or F
L48-1(4)
&
F48-1(4)
12
A6L
A7L
2
A11R
4 3
R/WR
6 5
VCC
CER
INDEX
A11L
R/WL
CEL
2720 drw 02
A10L
,
N/C
GND
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O6L
I/O7L
19
20
I/O5L
I/O1L
I/O2L
I/O3L
OER
10
14
A9L
I/O0L
2
45
44
13
A7L
A8L
48-Pin LCC/Flatpack
Top View(5)
14
A1R
17
32
I/O7R
I/O2L
31
18
19 20 21 22 23 24 25 26 27 28 29 30
I/O6R
2
I/O4R
I/O5R
I/O1L
I/O3R
A9R
I/O2R
33
GND
I/O0R
I/O1R
16
I/O7L
15
I/O0L
I/O5L
A9L
I/O3L
I/O4L
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
J52-1 package body is approximately .75 in x .75 in x .17 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approxiamtely .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of actual part-marking.
4 3
VCC
CER
7 6 5
A1L
R/WL
CEL
A10L
A11L
INDEX
I/O6L
VCC
CER
R/WR
A11R
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
I/O4L
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8 IDT7134P or C 41
P48-1(4)
9
40
&
10
39
(4)
11 C48-2
38
48-Pin
12
37
Top
13 View
36
(5)
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
A0L
OEL
CEL
R/WL
A11L
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O 0L
I/O 1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
A0L
OEL
Pin Configurations(1,2,3)
2720 drw 04
,
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1,2)
Absolute Maximum Ratings(1)
Symbol
Commercial
& Industrial
Military
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
o
C
PT(3)
Power
Dissipation
1.5
1.5
W
IOUT
DC Output
Current
50
50
mA
VTERM(2)
Rating
Grade
Military
Ambient
Temperature
GND
Vcc
-55OC to +125OC
0V
5.0V + 10%
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
Commercial
Industrial
2720 tbl 03
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
3. VTERM = 5.5V.
Recommended DC Operating
Conditions
Symbol
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions (2)
Max.
Unit
VIN = 3dV
11
pF
V OUT = 3dV
11
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
Capacitance (1) (T A = +25°C, f = 1.0MHz)
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
6.0(2)
V
____
0.8
(1)
Input Low Voltage
-0.5
V
2720 tbl 04
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5V ± 10%)
7134SA
Symbol
Parameter
(1)
Test Conditions
7134LA
Min.
Max.
Min.
Max.
Unit
V CC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
|ILI|
Input Leakage Current
|ILO|
Output Leakage Current
CE - VIH, VOUT = 0V to V CC
___
10
___
5
µA
V OL
Output Low Voltage
IOL = 6mA
___
0.4
___
0.4
V
IOL = 8mA
___
0.5
___
0.5
V
IOH = -4mA
2.4
___
2.4
___
V
V OH
Output High Voltage
2720 tbl 05
NOTES:
1. At Vcc < 2.0V input leakages are undefined.
3
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,4) (VCC = 5.0V ± 10%)
7134X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL
Outputs Open
f = fMAX(3)
CEL and CER = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
f=fMAX(3)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
One Port CE"A" or
CE"B" > V CC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
COM'L
SA
LA
170
170
280
240
160
160
280
220
150
150
260
210
mA
MIL &
IND
SA
LA
____
____
____
____
160
160
310
260
150
150
300
250
COM'L
SA
LA
25
25
100
80
25
25
80
50
25
25
75
45
MIL &
IND
SA
LA
____
____
____
____
25
25
100
80
25
25
75
55
COM'L
SA
LA
105
105
180
150
95
95
180
140
85
85
170
130
MIL &
IND
SA
LA
____
____
____
____
95
95
210
170
85
85
200
160
COM'L
SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
SA
LA
105
105
170
130
95
95
170
120
85
85
160
110
MIL &
IND
SA
LA
____
____
____
____
95
95
210
150
85
85
190
130
mA
mA
mA
mA
2720 tbl 06a
7134X45
Com'l &
Military
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Version
7134X70
Com'l &
Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
CE = VIL
Outputs Open
f = fMAX(3)
COM'L
SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
MIL &
IND
SA
LA
140
140
280
240
140
140
270
220
140
140
270
220
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
COM'L
SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
MIL &
IND
SA
LA
25
25
70
50
25
25
70
50
25
25
70
50
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
f=fMAX(3)
COM'L
SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
MIL &
IND
SA
LA
75
75
190
150
75
75
180
150
75
75
180
150
Full Standby Current
(Both Ports CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L
SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
Full Standby Current
(One Port CMOS Level Inputs)
One Port CE"A" or
CE"B" > V CC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L
SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
MIL &
IND
SA
LA
75
75
180
120
75
75
170
120
75
75
170
120
Dynamic Operating
Current
(Both Ports Active)
Test Condition
7134X55
Com'l, Ind
& Military
mA
mA
mA
mA
2720 tbl 06b
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
4
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) V LC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Condition
Min.
Typ. (1)
Max.
Unit
2.0
___
___
V
µA
VDR
VCC for Data Retention
VCC = 2V
ICCDR
Data Retention Current
CE > V HC
MIL. & IND.
___
100
4000
VIN > V HC or < V LC
COM'L.
___
100
1500
0
___
___
ns
tRC(2)
___
___
ns
tCDR (3)
Chip Dese lect to Data Retention Time
tR(3)
Operation Recovery Time
2720 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR ≥ 2V
tCDR
CE
tR
VDR
VIH
VIH
2720 drw 05
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1 and 2
2720 tbl 08
+5V
+5V
1250Ω
1250Ω
DATAOUT
775Ω
DATAOUT
30pF
775Ω
2720 drw 06 ,
5pF *
2720 drw 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ , tHZ, t WZ, tOW)
*Including scope and jig
5
,
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3,4)
7134X20
Com'l Only
Symbol
Parameter
7134X35
Com'l &
Military
7134X25
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
ns
tAOE
Output Enable Access Time
____
15
____
15
____
20
ns
tOH
Output Hold from Address Change
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
____
15
____
15
____
20
ns
0
____
0
____
0
____
ns
____
20
____
25
____
35
(1,2)
Output Low-Z Time
tLZ
tHZ
Output High-Z Time
(1,2)
(2)
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time (2)
ns
2720 tbl 09a
7134X45
Com'l &
Military
Symbol
Parameter
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
____
55
____
70
____
ns
tAA
Address Access Time
____
45
____
55
____
70
ns
tACE
Chip Enable Access Time
____
45
____
55
____
70
ns
tAOE
Output Enable Access Time
____
25
____
30
____
40
ns
tOH
Output Hold from Address Change
0
____
0
____
0
____
ns
5
____
5
____
5
____
ns
____
20
____
25
____
30
ns
0
____
0
____
0
____
ns
____
45
____
50
____
50
ns
tLZ
tHZ
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
(2)
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time (2)
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
6
2720 tbl 09b
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
tAA(5)
tOH
tOH
PREVIOUS DATA VALID
DATAOUT
DATA VALID
2720 drw 08
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
tACE
CE
tHZ(2)
tAOE(4)
OE
tHZ(2)
tLZ(1)
VALID DATA(4)
DATAOUT
tLZ(1)
ICC
CURRENT
ISB
tPU
tPD
50%
50%
2720 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,7)
7134X20
Com'l Only
Symbol
Parameter
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
15
____
20
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
____
15
____
15
____
20
ns
0
____
3
____
ns
15
____
20
ns
3
____
ns
60
ns
35
Output High-Z Time
tHZ
tDH
Data Hold Time
(1,2)
(3)
0
____
(1,2)
____
15
____
(1,2,3)
3
____
3
____
____
40
____
50
____
____
30
____
30
____
Write Enable to Output in High-Z
tWZ
tOW
tWDD
tDDD
Output Active from End-of-Write
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4,6)
ns
2720 tbl 10a
7134X45
Com'l &
Military
Symbol
Parameter
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
45
____
55
____
70
____
ns
tEW
Chip Enable to End-of-Write
40
____
50
____
60
____
ns
tAW
Address Valid to End-of-Write
40
____
50
____
60
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
40
____
50
____
60
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
25
____
30
____
ns
____
20
____
25
____
30
ns
3
____
3
____
ns
25
____
30
ns
3
____
ns
90
ns
70
tHZ
tDH
tWZ
tOW
tWDD
tDDD
Output High-Z Time
Data Hold Time
(1,2)
(3)
3
____
(1,2)
____
20
____
(1,2,3)
3
____
3
____
____
70
____
80
____
____
45
____
55
____
Write Enable to Output in High-Z
Output Active from End-of-Write
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4,6)
ns
2720 tbl 10b
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and t OW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
6. tDDD = 35ns for military temperature range.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
8
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,2,3)
tWC
MATCH
ADDR "A"
tWP
R/W "A"
tAW
(1)
tDW
VALID
DATAIN "A"
MATCH
ADDR "B"
tWDD
VALID
DATAOUT "B"
tDDD
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2720 drw 10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
OE
tAS(6)
tWR(3)
tAW
CE
tHZ (7)
tWP(2)
R/W
(7)
tWZ (7)
tLZ
DATAOUT
tOW
(4)
tHZ(7)
(4)
tDW
tDH
DATAIN
2720 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP ) of a CE =V IL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP .
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)
tWC
ADDRESS
tAW
CE
tAS(5)
tEW(2)
tWR(3)
R/W
tDW
tDH
DATAIN
2720 drw 12
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP ) of a CE =V IL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table I – Read/Write Control
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
in the table below.
Left or Right Port(1)
R/W
CE
OE
D0-7
Function
X
H
X
Z
Port Deselected and in Power-Down
Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = H, Power Down
Mode ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
X
X
H
Z
Data on port written into memory
Data in memory output on port
High impedance outputs
NOTE:
1. A0L - A11L ≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance
10
2720 tbl 11
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
Device Type
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
P
C
J
L48
F
48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
45
55
70
Commercial Only
Commercial & Military
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military
LA
SA
Low Power
Standard Power
7134
32K (4K x 8-Bit) Dual-Port RAM
Speed in nanoseconds
2720 drw 13
NOTE:
1. Industrial temperature is available for PLCC packages in standard power.
For other speeds, packages and powers contact your sales office.
Datasheet Document History
3/25/99
6/9/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
Changed drawing format
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11
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