Freescale MC100ES6139DTR2 3.3v ecl/pecl/hstl/lvds 2/4, 4/6 clock generation chip Datasheet

Freescale Semiconductor
Technical Data
3.3 V ECL/PECL/HSTL/LVDS ÷2/4,
÷4/5/6 Clock Generation Chip
The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device. If a singleended input is to be used, the VBB output should be connected to the CLK input
and bypassed to ground via a 0.01 µF capacitor.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6139s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6139,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All
VCC and VEE pins must be externally connected to power supply to guarantee
proper operation.
The 100ES Series contains temperature compensation.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
VBB Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
© Freescale Semiconductor, Inc., 2005. All rights reserved.
MC100ES6139
Rev 3, 06/2005
MC100ES6139
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
Package
MC100ES6139DT
TSSOP-20
MC100ES6139DTR2
TSSOP-20
MC100ES6139EJ
TSSOP-20 (Pb-Free)
MC100ES6139EJR2
TSSOP-20 (Pb-Free)
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
Table 1. Pin Description
Pin
VCC
EN
3
4
5
6
7
8
CLK
CLK
VBB
MR
VCC
9
Function
CLK(1)
ECL Diff Clock Inputs
EN(1)
ECL Sync Enable
MR(1)
ECL Master Reset
10
VBB
ECL Reference Output
DIVSELa
2
DIVSELb1
1
DIVSELb0
CLK(1),
Q0, Q1, Q0, Q1
ECL Diff ÷2/4 Outputs
Q2, Q3, Q2, Q3
ECL Diff ÷4/5/6 Outputs
DIVSELa(1)
ECL Freq. Select Input ÷2/4
DIVSELb0(1)
ECL Freq. Select Input ÷4/5/6
DIVSELb1(1)
ECL Freq. Select Input ÷4/5/6
VCC
ECL Positive Supply
VEE
ECL Negative Supply
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
1. Pins will default low when left open.
DIVSELa
Q0
CLK
÷2/4
Q0
R
CLK
Q1
Q1
Q2
EN
÷4/5/6
Q2
R
Q3
MR
DIVSELb0
DIVSELb1
Q3
VEE
Figure 2. Logic Diagram
Table 2. Function Tables
CLK
EN
MR
Z
ZZ
X
L
H
X
L
L
H
Function
Divide
Hold Q0:3
Reset Q0:3
X = Don’t Care
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa
Q0:1 Outputs
L
H
Divide by 2
Divide by 4
DIVSELb0
DIVSELb1
Q2:3 Outputs
L
H
L
H
L
L
H
H
Divide by 4
Divide by 6
Divide by 5
Divide by 5
MC100ES6139
2
Advanced Clock Drivers Device Data
Freescale Semiconductor
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. Timing Diagram
CLK
tRR
RESET
Q (÷n)
Figure 4. Timing Diagram
Table 3. Attributes
Characteristics
Value
Internal Input Pulldown Resistor
75 kΩ
Internal Input Pullup Resistor
75 kΩ
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MC100ES6139
Advanced Clock Drivers Device Data
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3
Table 4. Maximum Ratings(1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
3.9
V
VEE
ECL Mode Power Supply
VCC = 0 V
–3.9
V
VI
PECL Mode Input Voltage
ECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
3.9
–3.9
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature Range
–65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
74
64
°C/W
°C/W
VI ≤ VCC
VI ≥ VEE
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
1. Maximum Ratings are those values beyond which device damage may occur.
Table 5. DC Characteristics (VCC = 0 V, VEE = –3.8 V to –3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
Symbol
IEE
VOH
–40°C
Characteristic
Min
Power Supply Current
0°C to 85°C
Typ
Max
35
60
Min
Unit
Typ
Max
35
60
mA
(2)
VCC –1150 VCC –1020 VCC –800 VCC –1200 VCC –970
VCC –750
mV
(2)
VCC –1950 VCC –1620 VCC –1250 VCC –2000 VCC –1680 VCC –1300
mV
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage (Single-Ended)
VCC –1165
VCC –880 VCC –1165
VCC –880
mV
VIL
Input LOW Voltage (Single-Ended)
VCC –1810
VCC –1475 VCC –1810
VCC –1475
mV
VBB
Output Reference Voltage
VCC –1400
VCC –1200 VCC –1400
VCC –1200
mV
V
VPP
VCMR
Differential Input Voltage
(3)
Differential Cross Point Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
(4)
0.12
1.3
0.12
1.3
VEE +0.2
VCC –1.1
VEE +0.2
VCC –1.1
V
150
µA
150
0.5
0.5
µA
1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
2. All loading with 50 Ω to VCC–2.0 volts.
3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
MC100ES6139
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Advanced Clock Drivers Device Data
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Table 6. AC Characteristics (VCC = 0 V, VEE = –3.8 V to –3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
Symbol
fmax
Maximum Frequency
tPLH,
tPHL
Propagation Delay
tRR
–40°C
Characteristic
Min
25°C
Typ
Max
Min
Typ
>1
CLK, Q (Diff)
MR, Q
Max
Min
>1
550
400
Reset Recovery
85°C
850
850
550
400
Typ
Max
>1
850
850
550
400
Unit
GHz
850
850
ps
200
100
200
100
200
100
ps
ts
Setup Time
EN, CLK
DIVSEL, CLK
200
400
120
180
200
400
120
180
200
400
120
180
ps
th
Hold Time
CLK, EN
CLK, DIVSEL
100
200
50
140
100
200
50
140
100
200
50
140
ps
550
450
550
450
550
450
tPW
tSKEW
Minimum Pulse Width
tJITTER Cycle-to-Cycle Jitter
VPP
VCMR
tr
tf
MR
Within Device Skew
Q, Q
Q, Q @ Same Frequency
Device-to-Device Skew(2)
(RSM 1σ)
Input Voltage Swing (Differential)
Differential Cross Point Voltage
Output Rise/Fall Times
(20% – 80%)
200
100
50
300
100
50
300
ps
1
1
1
ps
1200
mV
1200
VEE+0.2
Q, Q
200
1200
VCC–1.2 VEE+0.2
50
ps
100
50
300
300
200
VCC–1.2 VEE+0.2
50
300
50
VCC–1.2
V
300
ps
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC –2.0 V.
2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.
Q
D
Driver
Device
Receiver
Device
Q
D
50 Ω
50 Ω
VTT
VTT = VCC –- 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
MC100ES6139
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PACKAGE DIMENSIONS
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PACKAGE DIMENSIONS
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MC100ES6139
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NOTES
MC100ES6139
Advanced Clock Drivers Device Data
Freescale Semiconductor
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NOTES
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Advanced Clock Drivers Device Data
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MC100ES6139
Rev. 3
06/2005
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