IDT IDT54FCT163652 3.3v cmos 16-bit bus transceiver/ register Datasheet


Integrated Device Technology, Inc.
IDT54/74FCT163652/A/C
PRODUCT PREVIEW
3.3V CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS
These high-speed, low-power devices are organized as two
independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and xOEBA signals control the
transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The IDT54/74FCT163652/A/C have series current limiting
resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for
external series terminating resistors.
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The IDT54/74FCT163652/A/C 16-bit registered transceivers are built using advanced dual metal CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
1OEAB
2OEAB
1OEBA
2OEBA
1CLKBA
2CLKBA
1SBA
2SBA
1CLKAB
2CLKAB
2SAB
1SAB
B REG
1A1
B REG
D
D
C
C
1B1
A REG
2A1
D
C
C
TO 7 OTHER CHANNELS
2B1
A REG
D
TO 7 OTHER CHANNELS
3084 drw 01
3084 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
8.7
AUGUST 1996
DSC-3084/2
1
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OEAB
1
56
1OEBA
1CLKAB
2
55
1CLKBA
1SBA
1SAB
3
54
1SBA
53
GND
GND
4
53
GND
5
52
1B1
1A1
5
52
1B 1
1A2
6
51
1B2
1A2
6
51
1B2
VCC
7
50
VCC
VCC
7
50
VCC
1A3
8
49
1B3
1A3
8
49
1B3
1A4
9
48
1B4
1A4
9
48
1B4
1A5
10
47
1B5
1A5
10
47
1B5
GND
11
46
GND
GND
11
46
GND
1A6
12
45
1B6
1A6
12
45
1B6
1A7
13
44
1B7
1A7
13
44
1B7
1A8
14
1B8
1A8
14
43
1B8
2A1
15
SO56-1 43
SO56-2
SO56-3 42
2B1
2A1
15
42
2B1
2A2
16
41
2B2
2A2
16
41
2B2
2A3
17
40
2B3
2A3
17
40
2B3
GND
18
39
GND
GND
18
39
GND
2A4
19
38
2B4
2A4
19
38
2B4
2A5
20
37
2B5
2A5
20
37
2B5
2A6
21
36
2B6
2A6
21
36
2B6
VCC
22
35
VCC
VCC
22
35
VCC
2A7
23
34
2B7
2A7
23
34
2B7
2A8
24
33
2B8
2A8
24
33
2B8
GND
25
32
GND
GND
25
32
GND
2SAB
26
31
2SBA
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2CLKAB
27
30
2CLKBA
2OEAB
28
29
2OEBA
2OEAB
28
29
2OEBA
1OEAB
1
56
1OEBA
1CLKAB
2
55
1CLKBA
1SAB
3
54
GND
4
1A1
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
3084 drw 03
3084 drw 04
CERPACK
TOP VIEW
PIN DESCRIPTION
Pin Names
xAx
Description
Data Register A Inputs
Data Register B Outputs
xBx
Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA
xOEAB, xOEBA
Output Data Source Select Inputs
Output Enable Inputs
3084 tbl 01
8.7
2
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(2)
Data I/O(1)
Inputs
xOEAB
xOEBA
L
L
H
H
H or L
↑
X
H
H
H
L
L
L
L
H
H
H
xCLKAB xCLKBA
Operation or Function
xSAB
xSBA
xAx
xBx
H or L
↑
X
X
X
X
Input
Input
↑
↑
H or L
↑
X
X(2)
X
X
Input
Input
X
L
H or L
↑
↑
↑
X
X
X
X(2)
Unspecified(1)
Output
Input
Input
Hold A, Store B
Store B in both Registers
L
L
H
H
L
X
X
X
H or L
H or L
X
H or L
X
X
H or L
X
X
L
H
H
L
H
X
X
H
Output
Input
Input
Output
Output
Output
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
Isolation
Store A and B Data
Unspecified(1) Store A, Hold B
Output
Store A in Both Registers
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs.
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
3084 tbl 03
Symbol
VTERM(2)
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
TSTG
Description
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Storage Temperature
I OUT
DC Output Current
VTERM(3)
pF
VTERM(4)
3084 lnk 02
Max.
–0.5 to +4.6
Unit
V
–0.5 to +7.0
V
–0.5 to
VCC + 0.5
–65 to +150
V
°C
–60 to +60
mA
3084 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
8.7
3
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
BUS
A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
B
BUS
A
BUS
B
3084 drw 05
xOEAB
L
3084 drw 06
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
L
X
X
X
L
xOEAB
H
xOEBA
H
X
xCLKBA
xSAB
xSBA
X
L
X
REAL-TIME TRANSFER
BUS A TO B
REAL-TIME TRANSFER
BUS B TO A
BUS
A
xCLKAB
BUS
A
BUS
B
BUS
B
3084 drw 07
3084 drw 08
xOEAB xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
X
X
↑
X
X
X
↑
X
X
X
H
L
X
↑
X
L
H
↑
xOEAB
H
STORAGE FROM
A AND/OR B
xOEBA
L
xCLKAB
xCLKBA
H or L
H or L
xSAB
xSBA
H
H
TRANSFER STORED
DATA TO A AND/OR B
8.7
4
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V; Military: TA = –55°C to +125°C, VCC = 2.7V to 3.6V
Symbol
VIH
Parameter
Input HIGH Level (Input pins)
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
—
Max.
5.5
2.0
—
VCC+0.5
–0.5
—
0.8
V
VI = 5.5V
—
—
±1
µA
VI = VCC
—
—
±1
VI = GND
—
—
±1
VI = GND
—
—
±1
VO = VCC
—
—
±1
Input HIGH Level (I/O pins)
VIL
Input LOW Level
Guaranteed Logic LOW Level
Unit
V
(Input and I/O pins)
II H
Input HIGH Current (Input pins)(6)
Input HIGH Current (I/O
II L
Input LOW Current (Input pins)(6)
Input LOW Current (I/O
I OZH
VCC = Max.
pins)(6)
pins)(6)
High Impedance Output Current
VCC = Max.
pins) (6)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
I ODH
Output HIGH Current
VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3)
I ODL
Output LOW Current
VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3)
VOH
Output HIGH Voltage
VCC = Min.
I OH = –0.1mA
VIN = VIH or V IL
I OH = –3mA
VCC = 3.0V
VIN = VIH or V IL
VCC = Min.
I OH = –6mA MIL.
I OH = –8mA COM'L.
I OL = 0.1mA
VIN = VIH or V IL
I OL = 16mA
VOL
Output LOW Voltage
I OS
Short Circuit Current(4)
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = GND
µA
—
—
±1
—
–0.7
–1.2
V
–36
–60
–110
mA
50
90
200
mA
VCC– 0.2
—
—
V
2.4
3.0
—
2.4 (5)
3.0
—
—
—
0.2
—
0.2
0.4
I OL = 24mA
—
0.3
0.55
VCC = 3.0V
I OL = 24mA
VIN = VIH or V IL
VCC = Max., VO = GND(3)
—
0.3
0.50
–60
–135
–240
mA
—
150
—
mV
COM'L.
—
0.1
10
µA
MIL.
—
0.1
100
—
VCC = Max.,
VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
6. The test limit for this parameter is ±5µA at TA = –55°C.
8.7
V
3084 lnk 05
5
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
VIN = VCC –0.6V(3)
Min.
—
Typ.(2)
2.0
Max.
30
Unit
µA
∆ICC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current (4)
VIN = VCC
VCC = Max.
Outputs Open
VIN = GND
xOEAB = xOEBA=GND
One Input Toggling
50% Duty Cycle
—
60
100
µA/
MHz
IC
Total Power Supply Current (6)
VCC = Max.
Outputs Open
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xOEAB = xOEBA=GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
—
0.6
1.0
mA
VIN = VCC –0.6V
VIN = GND
—
0.6
1.0
VIN = VCC
VIN = GND
—
3.0
5.0 (5)
VIN = VCC –0.6V
VIN = GND
—
3.0
5.3 (5)
VCC = Max.
VCC = Max.
Outputs Open
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xOEAB = xOEBA=GND
Sixteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
8.7
3084 tbl 08
6
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163652
Com'l.
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
Parameter
Propagation Delay
Bus to Bus
Output Enable Time
xOEAB or xOEBA to Bus
Output Disable Time
xOEAB or xOEBA to Bus
Propagation Delay
Clock to Bus
Propagation Delay xSBA or
xSAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
tW
Clock Pulse Width
HIGH or LOW
tSK(o) Output Skew (3)
Condition(1)
Min.(2)
CL = 50pF
RL = 500Ω
2.0
FCT163652A
Mil.
Max.
Min.(2)
9.0
2.0
2.0
14.0
2.0
Com'l.
Max.
Min.(2)
11.0
2.0
2.0
15.0
9.0
2.0
2.0
9.0
2.0
FCT163652C
Mil.
Max.
Min.(2)
6.3
2.0
2.0
9.8
11.0
2.0
2.0
10.0
11.0
2.0
4.0
—
2.0
Com'l.
Mil.
Max.
Min.(2)
Max.
Min.(2)
7.7
1.5
5.4
—
—
ns
2.0
10.5
1.5
7.8
—
—
ns
6.3
2.0
7.7
1.5
6.3
—
—
ns
2.0
6.3
2.0
7.0
1.5
5.7
—
—
ns
12.0
2.0
7.7
2.0
8.4
1.5
6.2
—
—
ns
4.5
—
2.0
—
2.0
—
2.0
—
—
—
ns
—
2.0
—
1.5
—
1.5
—
1.5
—
—
—
ns
6.0
—
6.0
—
5.0
—
5.0
—
5.0
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
—
ns
Max. Unit
3084 tbl 09
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.7
7
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
6V
←
V
CC
500Ω
V
V
IN
Pulse
Generator
Open
GND
OUT
D.U.T.
50pF
R
T
C
Switch
6V
GND
Open
3084 lnk 10
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
L
3084 drw 09
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
3084 drw 11
3084 drw 10
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPLZ
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
6V
3084 drw 12
SWITCH
GND
3V
3V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
1.5V
0V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
3084 drw 13
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
8.7
8
IDT54/74FCT163652/A/C
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT XXXX
Device Type
Temperature
Range
X
Package
X
Process
Blank
B
PV
PA
PF
E
163652
163652A
163652C
54
74
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
Non-Inverting 16-Bit Bus Transceiver/Register
–55°C to +125°C
–40°C to +85°C
3084 drw 14
8.7
9
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