TI ADS5440IPFPR 13-bit 210 msps analog-to-digital converter Datasheet

ADS5440
www.ti.com
SLAS467 – JULY 2005
13-BIT 210 MSPS ANALOG-TO-DIGITAL CONVERTER
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FEATURES
13-Bit Resolution
210 MSPS Sample Rate
SNR = 69.1 dBc at 100-MHz IF and 210 MSPS
SFDR = 81 dBc at 100-MHz IF and 210 MSPS
SNR = 68.1 dBc at 230-MHz IF and 210 MSPS
SFDR = 79 dBc at 230-MHz IF and 210 MSPS
2.2 VPP Differential Input Voltage
Fully Buffered Analog Inputs
5 V Analog Supply Voltage
3.3 V LVDS Compatible Outputs
Total Power Dissipation: 2.0 W
2's Complement Output Format
TQFP-80 PowerPAD™ package
Industrial Temperature Range = –40°C to 85°C
APPLICATIONS
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Test and Measurement
Software-Defined Radio
Multi-channel Basestation Receivers
Basestation TX Digital Predistortion
Communication Instrumentation
DESCRIPTION
The ADS5440 is a 13-bit 210 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while
providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5440 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator
is also provided to further simplify the system design. The ADS5440 has outstanding low noise and linearity over
input frequency.
AVDD
AIN
AIN
A1
TH1
+
TH2
Σ
A2
+
TH3
ADC1
DAC1
Reference
A3
ADC3
−
−
VREF
Σ
DVDD
ADC2
5
DAC2
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[12:0]
GND
B0061-01
The ADS5440 is available in an 80-pin TQFP PowerPAD™ package. The ADS5440 is built on state of the art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial
temperature range (–40°C to 85°C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW
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ADS5440
www.ti.com
SLAS467 – JULY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
Product
ADS5440
(1)
(2)
PackageLead
Package
Designator
HTQFP-80 (2)
PowerPAD
(1)
PFP
Specified
Temperature
Range
Package
Marking
–40°C to 85°C
ADS5440I
Ordering
Number
Transport
Media,
Quantity
ADS5440IPFP
Tray, 96
ADS5440IPFPR
Tape and Reel, 1000
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 7,5 mm x 7,5 mm (typ)
ABSOLUTE MAXIMUM RATINGS
PRODUCT PREVIEW
over operating free-air temperature range (unless otherwise noted) (1)
VALUE / UNIT
Supply voltage
AVDD to GND
6V
DRVDD to GND
5V
Analog input to GND
–0.3 V to AVDD+0.3 V
Clock input to GND
–0.3 V to AVDD+0.3 V
CLK to CLK
±2.5
Digital data output to GND
–0.3 V to DRVDD+0.3 V
Operating temperature range
–40°C to 85°C
Maximum junction temperature
150°C
Storage temperature range
(1)
–65°C to 150°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS (1)
PARAMETER
θJA
θJC
(1)
2
TYP
UNIT
Soldered slug, no airflow
TEST CONDITIONS
21.7
°C/W
Soldered slug, 250-LFPM airflow
15.4
°C/W
50
°C/W
Unsoldered slug, 250-LFPM airflow
43.4
°C/W
Bottom of package (heatslug)
2.99
°C/W
Unsoldered slug, no airflow
Using 36 thermal vias (6 x 6 array). See the Application Section.
ADS5440
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SLAS467 – JULY 2005
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
4.75
5.0
5.25
V
3.0
3.3
3.6
V
SUPPLIES
AVDD
Analog supply voltage
DRVDD
Output driver supply voltage
ANALOG INPUT
VCM
Differential input range
2.2
VPP
Input common mode
2.4
V
CLOCK INPUT
1/tC
ADCLK input sample rate (sine wave)
210
Clock amplitude, differential sine wave
Clock duty cycle
TA
MSPS
3
Vpp
50%
Open free air temperature
–40
°C
85
ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
PRODUCT PREVIEW
MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 210 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise
noted
UNIT
13
Bits
2.2
Vpp
1
kΩ
ANALOG INPUTS
Differential input range
Differential input resistance (DC)
Differential input capacitance
1.5
pF
Analog input bandwidth
500
MHz
2.4
V
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
DYNAMIC ACCURACY
No missing codes
Tested
DNL
Differential linearity error
fIN = 10 MHz
INL
Integral linearity error
fIN = 10 MHz
Offset error
±0.9
LSB
±1.5
–5
LSB
5
Offset temperature coefficient
mV
mV/°C
Gain error
–5
5
%FS
Gain temperature coefficient
∆%/°C
PSRR
mV/V
POWER SUPPLY
IAVDD
Analog supply current
IDRVDD
Output buffer supply current
350
mA
84
mA
Power dissipation
2.0
W
Power-up time
20
ms
VIN = full scale, fIN = 70 MHz, FS = 210 MSPS
DYNAMIC AC CHARACTERISTICS
SNR
Signal-to-noise ratio
fIN = 10 MHz
69.5
fIN = 70 MHz
69.3
fIN = 100 MHz
69.1
fIN = 170 MHz
69.1
fIN = 230 MHz
68.1
fIN = 300 MHz
67.5
fIN = 400 MHz
66.5
dBc
3
ADS5440
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SLAS467 – JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 210 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise
noted
PARAMETER
SFDR
HD2
PRODUCT PREVIEW
HD3
Spurious free dynamic range
Second harmonic
Third harmonic
Worst other harmonic/spur (other than
HD2 and HD3)
TEST CONDITIONS
MIN
fIN = 10 MHz
88
fIN = 70 MHz
80
fIN = 100 MHz
82
fIN = 170 MHz
71
fIN = 230 MHz
79
fIN = 300 MHz
71
fIN = 400 MHz
66
fIN = 10 MHz
88
fIN = 70 MHz
83
fIN = 100 MHz
82
fIN = 170 MHz
71
fIN = 230 MHz
79
fIN = 300 MHz
74
fIN = 400 MHz
75
fIN = 10 MHz
90
fIN = 70 MHz
80
fIN = 100 MHz
86
fIN = 170 MHz
75
fIN = 230 MHz
85
fIN = 300 MHz
72
fIN = 400 MHz
66
fIN = 10 MHz
95
fIN = 70 MHz
95
fIN = 100 MHz
90
fIN = 170 MHz
89
fIN = 230 MHz
85
fIN = 300 MHz
93
fIN = 400 MHz
SINAD
ENOB
TYP
MAX
UNIT
dBc
dBc
dBc
dBc
70
fIN = 10 MHz
69.4
fIN = 70 MHz
68.8
fIN = 100 MHz
68.6
fIN = 170 MHz
65.8
fIN = 230 MHz
67.4
fIN = 300 MHz
65.4
fIN = 400 MHz
61.6
dBc
Effective number of bits
fIN = 70 MHz
11
Bits
RMS idle channel noise
Inputs tied to common-mode
0.4
LSB
DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS
Differential output voltage
Output offset voltage
4
0.35
1.125
V
1.375
V
ADS5440
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SLAS467 – JULY 2005
TIMING CHARACTERISTICS
tA
N+3
N
AIN
N+1
N+2
CLK, CLK
tCLKH
N+1
N
N+4
tCLKL
N+2
N+3
N+4
tC_DR
D[12:0],
OVR, OVR
N−3
tr
N−2
tf
tsu_c
N−1
tsu_DR
th_c
N
th_DR
PRODUCT PREVIEW
tCLK
DRY, DRY
tDR
T0073-01
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
tA
Aperature delay
tJ
Clock slope independent aperature uncertainty (jitter)
kJ
Clock slope jitter factor dependency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ps
fs
s/V
Latency
4
cycles
Clock Input
tCLK
Clock period
4.76
ns
tCLKH
Clock pulsewidth high
2.38
ns
tCLKL
Clock pulsewidth low
2.38
ns
3.06
ns
5.44
ns
Clock to DataReady (DRY)
tDR
Clock rising to DataReady falling
tC_DR
Clock rising to DataReady rising
Clock to DATA,
Clock duty cycle = 50%
(1)
OVR (2)
tr
Data VOL to Data VOH (rise time)
ns
tf
Data VOH to Data VOL (fall time)
ns
tsu_c
Data valid to clock (setup time)
0.64
ns
th_c
Clock to invalid Data (hold time)
4.39
ns
2.42
ns
DataReady (DRY)/DATA, OVR (2)
tsu(DR)
(1)
(2)
Data valid to DRY
tC_DR = tDR + tCLKH for clock duty cycles other than 50%
Data is updated with clock rising edge or DRY falling edge.
5
ADS5440
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SLAS467 – JULY 2005
TIMING CHARACTERISTICS (continued)
over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
th(DR)
TEST CONDITIONS
DRY to invalid Data
MIN
TYP
MAX
1.33
ns
DEVICE INFORMATION
PFP PACKAGE
(TOP VIEW)
D5
D5
D6
D6
GND
DVDD
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
DRY
DRY
61
39
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
1 2 3
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
4 5
6
GND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
PRODUCT PREVIEW
DVDD
GND
AVDD
NC
NC
VREF
GND
AVDD
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
AVDD
GND
D4
D4
D3
D3
D2
D2
D1
D1
GND
DVDD
D0
D0
NC
NC
NC
NC
NC
NC
OVR
OVR
GND
AVDD
GND
AVDD
GND
AVDD
GND
NC
GND
AVDD
GND
NC
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
P0027-01
TERMINAL FUNCTIONS
TERMINAL
NAME
AVDD
DVDD
6
NO.
DESCRIPTION
3, 8, 13, 14, 19, 21,
23, 25, 27, 31, 35, 37, Analog power supply
39
1, 51, 66
Output driver power supply
UNIT
ADS5440
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SLAS467 – JULY 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
DESCRIPTION
VREF
6
Reference voltage
CLK
10
Differential input clock (positive). Conversion initiated on rising edge
CLK
11
Differential input clock (negative)
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
OVR, OVR
42, 41
Over range indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range.
D0, D0
50, 49
LVDS digital output pair
D1–D6, D1–D6
53–64
LVDS digital output pairs
D7–D11, D7–D11
67–76
LVDS digital output pairs
D12, D12
78, 77
LVDS digital output pair, most-significant bit (MSB
DRY, DRY
80, 79
Data ready LVDS output pair
NC
4, 5, 29, 33, 43–48
No connect
DEFINITION OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic
high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is
performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart.
The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a least
squares curve fit of that transfer function. The INL at each analog input value is the difference between the
actual transfer function and this best fit line, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the
nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters
over the whole temperature range divided by TMIN– TMAX.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding
the power at dc and the first five harmonics.
SNR 10log
P
S
10 P
N
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
7
PRODUCT PREVIEW
2, 7, 9, 12, 15, 18, 20,
22, 24, 26, 28, 30, 32, Ground
34, 36, 38, 40, 52, 65
GND
ADS5440
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SLAS467 – JULY 2005
DEFINITION OF SPECIFICATIONS (continued)
Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other
spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD 10log
P
S
10 P P
N
D
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale input
amplitude.
Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five
harmonics (PD).
P
THD 10log
10 P
S
D
(3)
THD is typically given in units of dBc (dB to carrier).
PRODUCT PREVIEW
Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power
of the worst spectral component at either frequency 2f1– f2 or 2f2– f1). IMD3 is either given in units of dBc (dB
to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to the converter’s full-scale range.
8
ADS5440
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SLAS467 – JULY 2005
TYPICAL CHARACTERISTICS
Spectral Performance
(FFT For 10-MHz Input Signal)
Spectral Performance
(FFT For 100-MHz Input Signal)
0
0
SFDR = 90.6 dBc
SNR = 69.7 dBc
THD = 85.4 dBc
SINAD = 69.5 dBc
−20
−40
Amplitude − dB
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
20
f − Frequency − MHz
30
40
50
60
70
80
90 100
f − Frequency − MHz
G001
G002
Figure 2.
Figure 3.
Spectral Performance
(FFT For 230-MHz Input Signal)
Spectral Performance
(FFT For 300-MHz Input Signal)
0
0
SFDR = 76.6 dBc
SNR = 67.8 dBc
THD = 72.5 dBc
SINAD = 66.5 dBc
−20
SFDR = 72.2 dBc
SNR = 67.5 dBc
THD = 70 dBc
SINAD = 65.5 dBc
−20
−40
Amplitude − dB
Amplitude − dB
PRODUCT PREVIEW
Amplitude − dB
−20
SFDR = 82.9 dBc
SNR = 69.5 dBc
THD = 79.2 dBc
SINAD = 69 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
f − Frequency − MHz
10
20
30
40
50
60
G003
Figure 4.
70
80
90 100
f − Frequency − MHz
G004
Figure 5.
9
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