To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. HD74ALVCH16245 6-bit Bus Transceivers with 3-state Outputs REJ03D0049-0500Z (Previous ADE-205-134C(Z)) Rev.5.00 Oct.02.2003 Description The HD74ALVCH16245 is designed for asynchronous communication between data buses. The control function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The output enable (OE) input can be used to disable the device so that the buses are effectively isolated. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • • • • VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs Operation OE DIR L L B data to A bus L H A data to B bus H X Isolation H : High level L : Low level X : Immaterial Rev.5.00, Oct.02.2003, page 1 of 8 HD74ALVCH16245 Pin Arrangement 1DIR 1 48 1OE 1B1 2 47 1A1 1B2 3 46 1A2 GND 4 45 GND 1B3 5 44 1A3 1B4 6 VCC 7 43 1A4 1B5 8 41 1A5 1B6 9 40 1A6 GND 10 39 GND 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 2A2 GND 15 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 42 VCC VCC 18 31 VCC 2B5 19 30 2A5 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE (Top view) Rev.5.00, Oct.02.2003, page 2 of 8 HD74ALVCH16245 Absolute Maximum Ratings Item Supply voltage Input voltage *1, 2 Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V –0.5 to VCC +0.5 Conditions Except I/O ports I/O ports Output voltage *1, 2 VO –0.5 to VCC +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin ICC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 0.85 W Storage temperature Tstg –65 to 150 °C TSSOP Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current IOH — –12 mA — –12 VCC = 2.7 V — –24 VCC = 3.0 V — 12 — 12 VCC = 2.7 V — 24 VCC = 3.0 V Low level output current IOL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. Rev.5.00, Oct.02.2003, page 3 of 8 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH16245 Logic Diagram 1DIR 1 48 1A1 1OE 47 2 1B1 To seven other channels 2DIR 24 25 2A1 2OE 36 13 To seven other channels Rev.5.00, Oct.02.2003, page 4 of 8 2B1 HD74ALVCH16245 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) *1 Input voltage VIH VIL Output voltage VOH Min Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 IOH = –100 µA Min to Max VCC–0.2 — 2.3 2.0 — IOH = –6 mA, VIH = 1.7 V 2.3 1.7 — IOH = –12 mA, VIH = 1.7 V 2.7 2.2 — IOH = –12 mA, VIH = 2.0 V 3.0 2.4 — IOH = –12 mA, VIH = 2.0 V 3.0 2.0 — IOH = –24 mA, VIH = 2.0 V Min to Max — 0.2 IOL = 100 µA 2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V 2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V 2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V 3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V IIN 3.6 — ±5 IIN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V IOZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current ICC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at VCC or GND VOL Input current Off state output current *2 ∆ICC V Test Conditions µA VIN = VCC or GND Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current. Rev.5.00, Oct.02.2003, page 5 of 8 HD74ALVCH16245 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Propagation delay time tPLH tPHL Output enable time Output disable time Min Typ Max Unit FROM (Input) TO (Output) 2.5±0.2 1.0 — 3.9 ns A or B B or A 2.7 — — 3.6 3.3±0.3 1.0 — 3.2 tZH 2.5±0.2 1.0 — 5.7 ns OE B or A tZL 2.7 — — 5.4 ns OE B or A 3.3±0.3 1.0 — 4.4 tHZ 2.5±0.2 1.0 — 5.2 tLZ 2.7 — — 4.6 3.3±0.3 1.0 — 4.1 Input capacitance CIN 3.3 — 4.0 — pF Control inputs Output capacitance CO 3.3 — 9.0 — pF A or B ports • Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 4.6 V 6.0 V Note: 1. C L includes probe and jig capacitance. Rev.5.00, Oct.02.2003, page 6 of 8 HD74ALVCH16245 • Waveforms – 1 tr tf VIH 90 % Vref 90 % Input Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL • Waveforms – 2 Output Control tf tr 90 % Vref VIH 90 % Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈VOL1 TEST VIH Vref VOH1 VOL1 Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.5.00, Oct.02.2003, page 7 of 8 HD74ALVCH16245 Package Dimensions As of January, 2003 12.5 12.7 Max Unit: mm 25 6.10 48 1 *0.19 ± 0.05 0.50 24 0.08 M 1.0 8.10 ± 0.20 0.65 Max *Ni/Pd/Au plating Rev.5.00, Oct.02.2003, page 8 of 8 0.10 ± 0.05 0.10 *0.15 ± 0.05 1.20 Max 0˚ – 8˚ 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TTP-48DBV — — 0.20 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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