Infineon HYB25D256800BC-7 256-mbit double data rate sdram, die rev. b Datasheet

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data Sheet Jan. 2003, V1.1
Features
CAS Latency and Frequency
CAS Latency
2
2.5
Maximum Operating Frequency (MHz)
DDR200 DDR266A DDR266
DDR333
-8
-7
-7F
-6
100
133
133
133
125
143
143
166
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: (1.5), 2, 2.5, (3)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh
Interval (8K refresh)
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V / VDD = 2.5V ± 0.2V
• TSOP66 package
• 60 balls BGA w/ 3 depop rows (“chipsize package”) 12 mm x 8 mm.
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
row to be accessed. The address bits registered coincident with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
2003-01-09, V1.1
Page 1 of 77
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Ordering Information
Part Numbera
Org.
CAS-RCD-RP
Latencies
Clock
(MHz)
CAS-RCD-RP
Latencies
Clock
(MHz)
Speed
Package
HYB25D256400BT(L)-6
x4
2.5-3-3
166
2-3-3
133
DDR333
66 Pin P-TSOP-II
HYB25D256800BT(L)-6
x8
HYB25D256160BT(L)-6
x16
HYB25D256400BT(L)-7
x4
HYB25D256800BT(L)-7
x8
HYB25D256160BT(L)-7
x16
HYB25D256400BT(L)-7F
x4
HYB25D256800BT(L)-7F
x8
HYB25D256160BT(L)-7F
x16
HYB25D256400BT(L)-8
x4
HYB25D256800BT(L)-8
x8
HYB25D256160BT(L)-8
x16
HYB25D256400BC(L)-6
x4
HYB25D256800BC(L)-6
x8
HYB25D256160BC(L)-6
x16
HYB25D256400BC(L)-7
x4
HYB25D256800BC(L)-7
x8
HYB25D256160BC(L)-7
x16
HYB25D256400BC(L)-7F
x4
HYB25D256800BC(L)-7F
x8
HYB25D256160BC(L)-7F
x16
HYB25D256400BC(L)-8
x4
HYB25D256800BC(L)-8
x8
HYB25D256160BC(L)-8
x16
143
DDR266A
2-2-2
125
2.5-3-3
166
2-3-3
DDR266
100
DDR200
133
DDR333
143
DDR266A
2-2-2
125
60 Balls P-FBGA
DDR266
100
DDR200
a. HYB: designator for memory components
25D: DDR-I SDRAMs at Vddq=2.5V
256: 256Mb density
400/800/160: Product variations x4, x8 and x16
B: Die revision B
C/T: Package type FBGA and TSOP
L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents
-5/6/7/7F/8: speed grade - see table
Page 2 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Pin Configuration (TSOP66)
VDD
VDD
VDD
1
66
VSS
VSS
VSS
NC
VDDQ
NC
DQ0
VDDQ
NC
DQ0
VDDQ
DQ1
2
3
4
65
64
63
DQ15
VSSQ
DQ14
DQ7
VSSQ
NC
NC
VSSQ
NC
DQ0
DQ1
DQ2
5
62
DQ13
DQ6
DQ3
VSSQ
NC
NC
VDDQ
NC
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
DQ3
DQ4
VDDQ
DQ5
6
7
8
9
10
61
60
59
58
57
VDDQ
DQ12
DQ11
VSSQ
DQ10
VDDQ
NC
DQ5
VSSQ
NC
VDDQ
NC
NC
VSSQ
NC
DQ6
11
56
DQ9
DQ4
DQ2
VSSQ
VSSQ
12
55
VDDQ
VDDQ
VDDQ
54
53
52
51
DQ8
NC
NC
NC
VSSQ
UDQS
NC
VSSQ
DQS
NC
VSSQ
DQS
DQ1
VSSQ
NC
NC
NC
NC
DQ7
NC
VDDQ
NC
VDDQ
NC
VDDQ
LDQS
13
14
15
16
NC
VDD
NC
NC
VDD
NC
NC
VDD
NC
17
18
19
50
49
48
NC
VREF
VSS
NC
VREF
VSS
NC
VREF
VSS
NC
NC
LDM
20
47
UDM
DM
DM
WE
CAS
WE
CAS
WE
CAS
CK
CK
CK
CK
RAS
RAS
46
45
44
CK
CK
RAS
21
22
23
CKE
CKE
CKE
CS
NC
CS
NC
CS
NC
24
25
43
42
NC
A12
NC
A12
NC
A12
BA0
BA1
A10/AP
BA0
BA1
A10/AP
BA0
BA1
A10/AP
A11
A9
A8
A11
A9
A8
A0
A1
A2
A0
A1
A2
41
40
39
38
A11
A9
A8
A0
A1
A2
26
27
28
29
A7
A7
A7
30
31
37
36
A6
A5
A6
A5
A6
A5
A3
VDD
A3
VDD
A3
VDD
32
33
35
34
A4
VSS
A4
VSS
A4
VSS
16Mb x 16
32Mb x 8
64Mb x 4
Page 3 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Pin Configuration (FBGA)
1
2
3
7
8
9
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
VREF
VSS
DM
F
NC
VDD
NC
CLK
CLK
G
WE
CAS
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
A4
VSS
M
VDD
A3
(x4)
( x8 )
Top View (see the balls through the package)
1
2
7
8
9
A
VDD
DQ0
VDDQ
DQ14 VDDQ DQ13
B
DQ2
VSSQ
DQ1
DQ12 VSSQ DQ11
C
DQ4
VDDQ
DQ3
DQ10 VDDQ
D
DQ6
VSSQ
DQ5
LDQS VDDQ
DQ7
VSSQ DQ15
DQ8
VREF
3
VSS
DQ9
VSSQ UDQS
E
VSS
UDM
F
LDM
VDD
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
NC
( x 16 )
Page 4 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command
code. The standard pinout includes one CS pin.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0 - A12
Input
Address Inputs: Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
DQ
Input/Output
Data Input/Output: Data bus.
DQS
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data.
NC
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 2.5V ± 0.2V.
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 2.5V ± 0.2V.
VSS
Supply
Ground
VREF
Supply
SSTL_2 reference voltage: (VDDQ / 2)
Page 5 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Control Logic
2
Bank2
Bank3
CK, CK
DLL
2
8192
4
4
1
DQS
Generator
COL0
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
8
8
Write
FIFO
&
Drivers
Column-Address
Counter/Latch
COL0
1
Input
Register
1
Mask 1
1
1
4
4
4
clk clk
out in Data
4
2
8
10
11
Drivers
8
Sense Amplifiers
Data
4
MUX
Bank0
Memory
Array
(8192 x 1024 x 8)
Read Latch
8192
CK,
CK
DQ0-DQ3,
DM
DQS
DQS
1
Receivers
15
Address Register
A0-A12,
BA0, BA1
Refresh Counter 13
13
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (64Mb x 4)
4
COL0
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Page 6 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Control Logic
2
Bank2
Bank3
CK, CK
DLL
2
8192
8
512
(x16)
1
16
16
Write
FIFO
&
Drivers
Input
Register
1
Mask 1
1
1
8
8
8
clk clk
out in Data
8
2
16
Column
Decoder
9
10
8
DQS
Generator
COL0
I/O Gating
DM Mask Logic
Column-Address
Counter/Latch
COL0
1
Drivers
16
Sense Amplifiers
Data
8
MUX
Bank0
Memory
Array
(8192 x 512x 16)
Read Latch
8192
CK,
CK
DQ0-DQ7,
DM
DQS
DQS
1
Receivers
15
Address Register
A0-A12,
BA0, BA1
Refresh Counter 13
13
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (32Mb x 8)
8
COL0
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Page 7 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Control Logic
2
Bank3
CK, CK
2
8192
16
256
(x32)
1
DQS
Generator
32
32
Write
FIFO
&
Drivers
Input
Register
1
Mask 1
1
1
16
16
16
clk clk
out in Data
16
2
32
Column
Decoder
8
9
16
COL0
I/O Gating
DM Mask Logic
Column-Address
Counter/Latch
COL0
1
Drivers
32
Sense Amplifiers
Data
16
MUX
Bank0
Memory
Array
(8192 x 256x 32)
Read Latch
8192
CK,
CK
DQ0-DQ15,
DM
DQS
LDQS, UDQS
1
Receivers
15
Address Register
A0-A11,
BA0, BA1
Refresh Counter 13
13
13
Bank2
DLL
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (16Mb x 16)
16
COL0
2
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the
load of the bidirectional DQ , UDQS and LDQS signals.
Page 8 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456
bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a
single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
VDD and VDDQ are driven from a single power converter output AND
VTT meets the specification AND
VREF tracks VDDQ/2
or
The following relationship must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200ms delay prior to applying an executable command.
Once the 200ms delay has been satisfied, a Deselect or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During
the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock
cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters
without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal
operation.
Page 9 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai
when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed burst length applies to both Read
and Write bursts.
Page 10 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Mode Register Operation
BA1
BA0
0*
0*
A12 - A9
A8
A12
A11 A10
A9
A8
A7
A5
A4
CAS Latency
Operating Mode
A7
A6
A3
BT
A2
Burst Length
A6 - A0
Operating Mode
A3
Burst Type
0
Sequential
1
Interleave
0
0
0
Valid
Normal operation
Do not reset DLL
0
1
0
Valid
Normal operation
in DLL Reset
0
0
1
Reserved
-
-
-
Reserved
CAS Latency
A1
A0
Address Bus
Mode Register
Burst Length
A6
A5
A4
Latency
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
3 (optional)
0
1
1
8
1
0
0
Reserved
1
0
0
Reserved
1
0
1
1.5 (optional)
1
0
1
Reserved
1
1
0
2.5
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
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Burst Definition
Starting Column Address
Order of Accesses Within a Burst
Burst Length
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
2
4
8
Notes:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the
block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within
the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access
within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown in Burst Definition on page 12.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command
and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS
latency of 1.5 is an optional feature on this device.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A
Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Required CAS Latencies
CAS Latency = 2, BL = 4
CK
CK
Command
Read
NOP
NOP
NOP
NOP
NOP
CL=2
DQS
DQ
CAS Latency = 2.5, BL = 4
CK
CK
Command
Read
NOP
NOP
NOP
NOP
NOP
CL=2.5
DQS
DQ
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 13 of 77
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions
are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is
programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded
when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The
DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit
of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command
can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon
exit of self refresh operation.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
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Extended Mode Register Definition
BA1
BA0
0*
1*
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Operating Mode
A2
A1
A0
Address Bus
0
DS
DLL
Extended
Mode Register
Drive Strength
An - A3
A2 - A0
Operating Mode
0
Valid
Normal Operation
-
-
All other states
Reserved
A1
Drive Strength
0
Normal
1
Weak
A2
0
must be set to 0
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
Page 15 of 77
A0
DLL
0
Enable
1
Disable
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Commands
CommandsDeselect
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM
is effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no
bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is
issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for
x16, [i = 9, j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open
for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;
where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or
not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end
of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input
data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the
DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that
byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in
all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any
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256-Mbit Double Data Rate SDRAM, Die Rev. B
Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no
open row in that bank, or if the previously open row is already in the process of precharging.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above,
but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in
conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the
Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command.
Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if
an explicit Precharge command was issued at the earliest possible time, as described for each burst type in
the Operation section of this data sheet.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a
refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t
Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8 ms (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system,
meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh
command is 9 * 7.8 ms (70.2ms). This maximum absolute interval is short enough to allow for DLL updates
internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC
between updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The
Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The
DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self
Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except
CKE (low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to
CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because
time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
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Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Notes
Deselect (Nop)
H
X
X
X
X
NOP
1, 9
No Operation (Nop)
L
H
H
H
X
NOP
1, 9
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1, 3
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1, 4
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1, 4
Burst Terminate
L
H
H
L
X
BST
1, 8
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR / SR
1, 6, 7
Mode Register Set
L
L
L
L
Op-Code
MRS
1, 2
1. CKE is HIGH for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the
selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH
enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with
Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1
Write Inhibit
H
X
1
1. Used to mask write data; provided coincident with the corresponding data.
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Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and
BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row
to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued
to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same
bank can only be issued after the previous active row has been “closed” (precharged). The minimum time
interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval between successive Active commands to different
banks is defined by tRRD.
Activating a Specific Row in a Specific Bank
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
Page 19 of 77
A0-A12
RA
BA0, BA1
BA
RA = row address.
BA = bank address.
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2003-01-09, V1.1
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tRCD and tRRD Definition
CK
CK
NOP
ACT
A0-A12
ROW
ROW
COL
BA0, BA1
BA x
BA y
BA y
tRRD
ACT
NOP
NOP
RD/WR
Command
NOP
NOP
tRCD
Don’t Care
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts
are initiated with a Read command, as shown on Read Command on page 21.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands
used in the following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the
CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). Read Burst: CAS Latencies (Burst Length
= 4) on page 22 shows general timing for each supported CAS latency setting. DQS is driven by the DDR
SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state
coincident with the last data-out element is known as the read postamble. Upon completion of a burst,
assuming no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be
concatenated with or truncated with data from a subsequent Read command. In either case, a continuous
flow of data can be maintained. The first data element from the new burst follows either the last element of a
completed burst or the last desired data element of a longer burst which is being truncated. The new Read
command should be issued x cycles after the first Read command, where x equals the number of desired
data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Consecutive Read
Bursts: CAS Latencies (Burst Length = 4 or 8) on page 23. A Read command can be initiated on any clock
cycle following a previous Read command. Nonconsecutive Read data is illustrated on Non-Consecutive
Read Bursts: CAS Latencies (Burst Length = 4) on page 24. Full-speed Random Read Accesses: CAS
Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25.
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Read Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
CA
EN AP
A10
DIS AP
BA0, BA1
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
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Read Burst: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,COL n
CL=2
DQS
DOa-n
DQ
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,COL n
CL=2.5
DQS
DQ
DOa-n
DO a-n = data out from bank a, column n.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 22 of 77
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256-Mbit Double Data Rate SDRAM, Die Rev. B
Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
Read
BAa, COL n
NOP
NOP
NOP
BAa, COL b
CL=2
DQS
DQ
DOa-b
DOa-n
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
Read
BAa, COL n
NOP
NOP
NOP
BAa,COL b
CL=2.5
DQS
DQ
DOa- n
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 23 of 77
DOa- b
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Read
Command
Address
NOP
NOP
Read
BAa, COL n
NOP
NOP
BAa, COL b
CL=2
DQS
DO a-n
DQ
DOa- b
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
BAa, COL n
NOP
Read
NOP
NOP
NOP
BAa, COL b
CL=2.5
DQS
DQ
DO a-n
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 24 of 77
DOa- b
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
Read
Read
Read
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
NOP
NOP
CL=2
DQS
DQ
DOa-n
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
DOa-g
CAS Latency = 2.5
CK
CK
Command
Address
Read
Read
Read
Read
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
NOP
NOP
CL=2.5
DQS
DQ
DOa-n
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 25 of 77
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Terminating a
Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where
x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be
issued. If truncation is necessary, the Burst Terminate command must be used, as shown on Read to Write:
CAS Latencies (Burst Length = 4 or 8) on page 28. The example is shown for tDQSS(min). The tDQSS(max)
case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are defined in the section on
Writes.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that
Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read
latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot
be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data
elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and
address busses be available at the appropriate time to issue the command. The advantage of the Precharge
command is that it can be used to truncate bursts.
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HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BAa, COL n
CL=2
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BAa, COL n
CL=2.5
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 27 of 77
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HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Read to Write: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
BST
NOP
BAa, COL n
Write
NOP
NOP
BAa, COL b
CL=2
tDQSS (min)
DQS
DQ
DI a-b
DOa-n
DM
CAS Latency = 2.5
CK
CK
Command
Address
Read
BST
NOP
NOP
BAa, COL n
Write
NOP
BAa, COL b
CL=2.5
tDQSS (min)
DQS
DQ
DOa-n
Dla-b
DM
DO a-n = data out from bank a, column n
.DI a-b = data in to bank a, column b
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 28 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
Address
BA a or all
BA a, COL n
BA a, ROW
CL=2
DQS
DQ
DOa-n
CAS Latency = 2.5
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
Address
BA a or all
BA a, COL n
BA a, ROW
CL=2.5
DQS
DQ
DOa-n
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Page 29 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Writes
Write bursts are initiated with a Write command, as shown on Write Command on page 31.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at
the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the
write command, and subsequent data elements are registered on successive edges of DQS. The Low state
on DQS between the Write command and the first rising edge is known as the write preamble; the Low state
on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from
75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme
cases (i.e. tDQSS(min) and tDQSS(max)). Write Burst (Burst Length = 4) on page 32 shows the two extremes of
tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the
DQs and DQS enters High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either
case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied
after either the last element of a completed burst or the last desired data element of a longer burst which is
being truncated. The new Write command should be issued x cycles after the first Write command, where x
equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Write to
Write (Burst Length = 4) on page 33 shows concatenated bursts of 4. An example of non-consecutive Writes
is shown on Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 34. Full-speed random
write accesses within a page or pages can be performed as shown on Random Write Cycles (Burst Length =
2, 4 or 8) on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a
Write without truncating the write burst, tWTR (Write to Read) should be met as shown on Write to Read: NonInterrupting (CAS Latency = 2; Burst Length = 4) on page 36.
Data for any Write burst may be truncated by a subsequent Read command, as shown in the figures on Write
to Read: Interrupting (CAS Latency = 2; Burst Length = 8) on page 37 to Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) on page 39. Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with
DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without
truncating the write burst, tWR should be met as shown on Write to Precharge: Non-Interrupting (Burst Length
= 4) on page 40.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in the figures on
Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 41 to Write to Precharge: Nominal DQSS (2
bit Write), Interrupting (Burst Length = 4 or 8) on page 43. Note that only the data-in pairs that are registered
prior to the tWR period are written to the internal array, and any subsequent data in should be masked with
DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP
is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time
(as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is
that it can be used to truncate bursts.
Page 30 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
CA
EN AP
A10
DIS AP
BA0, BA1
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
Page 31 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write Burst (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (max)
DQS
Dla-b
DQ
DM
Minimum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (min)
DQS
DQ
Dla-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
A10 is Low with the Write command (Auto Precharge is disabled).
Don’t Care
Page 32 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Write (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
Write
NOP
Write
BAa, COL b
NOP
NOP
NOP
BAa, COL n
tDQSS (max)
DQS
DI a-b
DQ
DI a-n
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
Write
NOP
BA, COL b
Write
NOP
NOP
NOP
BA, COL n
tDQSS (min)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
Page 33 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
NOP
NOP
BAa, COL b
Write
NOP
BAa, COL n
tDQSS (max)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b, etc. = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
Page 34 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Random Write Cycles (Burst Length = 2, 4 or 8)
Maximum DQSS
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
Write
BAa, COL b
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
BAa, COL g
tDQSS (max)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DM
Minimum DQSS
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
Write
BAa, COL b
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
BAa, COL g
tDQSS (min)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DI a-g
DM
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
Page 35 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL b
BAa, COL n
CL = 2
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
tDQSS (min)
CL = 2
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
Page 36 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (max)
DQS
DQ
DIa- b
1
DM
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Page 37 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS
Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (min)
DQS
DQ
DM
DI a-b
1
2
2
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
Don’t Care
2 = These bits are incorrectly written into the memory array if DM is low.
Page 38 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (nom)
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Page 39 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Non-Interrupting (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tRP
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tDQSS (min)
tRP
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
Page 40 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Interrupting (Burst Length = 4 or 8)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA (a or all)
BA a, COL b
tDQSS (max)
tRP
2
DQS
DQ
DI a-b
3
DM
1
3
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Page 41 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting
(Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
4
4
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Page 42 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (nom)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
1
DI a-b = Data In for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Page 43 of 77
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Precharge Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9, A11, A12
All Banks
A10
BA0, BA1
One Bank
BA
BA = bank address
(if A10 is Low, otherwise Don’t Care).
Don’t Care
Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks.
The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged,
inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and
must be activated prior to any Read or Write commands being issued to that bank.
Page 44 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Power-Down
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down
mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Powerdown. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a Read command can be issued. In power-down mode, CKE Low and a stable clock signal must be
maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, powerdown duration is limited by the refresh requirements of the device, so in most applications, the self refresh
mode is preferred over the DLL-disabled power-down mode.
The power-down state is synchronously exited when CKE is registered HIGH (along with a Nop or Deselect
command). A valid, executable command may be applied one clock cycle later.
Power Down
CK
CK
tIS
CKE
Command
VALID
NOP
No column
access in
progress
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
Page 45 of 77
tIS
NOP
VALID
Exit
power down
mode
Don’t Care
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 2: Clock Enable (CKE)
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
CKE n-1
CKEn
Current State
Previous
Cycle
Current
Cycle
Command n
Self Refresh
L
L
X
Self Refresh
L
H
Deselect or NOP
Power Down
L
L
X
Power Down
L
H
Deselect or NOP
Exit Power-Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 47
Action n
Notes
Maintain Self-Refresh
Exit Self-Refresh
1
Maintain Power-Down
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Page 46 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation
1-6
L
H
H
H
No Operation
NOP. Continue previous operation
1-6
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
AUTO REFRESH
L
L
L
L
MODE REGISTER SET
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
Truncate Read burst, start Precharge
1-6, 8
BURST TERMINATE
1-6, 9
1-7
1-7
L
L
H
L
Precharge
L
H
H
L
BURST TERMINATE
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Truncate Write burst, start Precharge
1-6, 8, 11
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the
idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the
“row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP
has been met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP
has been met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each
positive clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR
SDRAM is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once
tMRD is met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in
the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes
with Auto Precharge disabled.
11. Requires appropriate DM masking.
Page 47 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
Any
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
Read (With
Auto Precharge)
Write (With
Auto Precharge)
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP/continue previous operation
1-6
L
H
H
H
No Operation
NOP/continue previous operation
1-6
X
X
X
X
Any Command Otherwise
Allowed to Bank m
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7
L
H
L
L
Write
Select column and start Write burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-8
L
H
L
L
Write
Select column and start new Write burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
L
H
L
H
Read
Select column and start new Read burst
L
H
L
L
Write
Select column and start Write burst
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
L
H
L
H
Read
Select column and start Read burst
1-7,10
L
H
L
L
Write
Select column and start new Write burst
1-7,10
L
L
H
L
Precharge
1-6
1-6
1-6
1-6
1-6
1-7,10
1-7,9,10
1-6
1-6
1-6
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown
are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes
with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any
command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other
limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum delay from a read or write
command with auto precharge enable, to a command to a different banks is summarized in table 5.
Page 48 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 5: Concurrent Auto Precharge
From Command
WRITE w/AP
Minimum Delay with Concurrent Auto Precharge
Support
Units
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write ot Write w/AP
BL/2
tCK
1
tCK
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL (rounded up)+ BL/2
tCK
1
tCK
To Command
(different bank)
Precharge or Activate
Read w/AP
Precharge or Activate
Page 49 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Simplified State Diagram
Power
Applied
Power
On
Self
Refresh
Precharge
PREALL
REFS
REFSX
MRS
EMRS
MRS
Auto
Refresh
REFA
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Write
Write A
Write
Read
Read A
Read
Read
Read A
Write A
Read
A
PRE
Write
A
PRE
PRE
PRE
Read
A
Precharge
PREALL
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
Page 50 of 77
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Operating Conditions
Absolute Maximum Ratings
Symbol
VIN, VOUT
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
Parameter
Rating
Units
-0.5 to VDDQ+ 0.5
V
Voltage on Inputs relative to VSS
-0.5 to +3.6
V
Voltage on VDD supply relative to VSS
-0.5 to +3.6
V
Voltage on VDDQ supply relative to VSS
-0.5 to +3.6
V
0 to +70
°C
-55 to +150
°C
Power Dissipation
1.0
W
Short Circuit Output Current
50
mA
Voltage on I/O pins relative to VSS
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Input and Output Capacitances
Parameter
Package
Symbol
TSOP
Input Capacitance: CK, CK
BGA
CI1
TSOP
Delta Input Capacitance CK, CK
BGA
CdI1
TSOP
Input Capacitance: All other input-only pins
BGA
CI2
TSOP
Delta Input Capacitance: All other input-only pins
BGA
CdI2
TSOP
Input/Output Capacitance: DQ, DQS, DM
BGA
CIO
TSOP
Delta Input/Output Capacitance : DQ, DQS, DM
BGA
CdIO
Min.
Max.
2.0
3.0
1.5
2.5
-
0.25
-
0.25
2.0
3.0
1.5
2.5
-
0.5
-
0.5
4.0
5.0
3.5
4.5
-
0.5
-
0.5
Units
Notes
pF
1
pF
1
pF
1
pF
1
pF
1, 2
pF
1
1. These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5V ± 0.2V, f = 100MHz, TA = 25°C,
VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) 0.2V. Unused pins are tied to ground .
2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching
at the board level
Page 51 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics and DC Operating Conditions
(0°C £ TA £ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V )
Symbol
Min
Max
Units
Notes
Supply Voltage
2.3
2.7
V
1
I/O Supply Voltage
2.3
2.7
V
1
VSS, VSSQ Supply Voltage, I/O Supply Voltage
0
0
V
I/O Reference Voltage
0.49 x VDDQ
0.51 x VDDQ
V
1, 2
I/O Termination Voltage (System)
VREF - 0.04
VREF + 0.04
V
1, 3
VIH(DC)
Input High (Logic1) Voltage
VREF + 0.15
VDDQ + 0.3
V
1
VIL(DC)
Input Low (Logic0) Voltage
- 0.3
VREF - 0.15
V
1
VIN(DC)
Input Voltage Level, CK and CK Inputs
- 0.3
VDDQ + 0.3
V
1
VID(DC)
Input Differential Voltage, CK and CK Inputs
0.36
VDDQ + 0.6
V
1, 4
VIRatio
VI-Matching Pullup Current to Pulldown Current
0.71
1.4
Input Leakage Current. Any input 0V £ VIN £ VDD
(All other pins not under test = 0V)
-2
2
mA
1
IOZ
Output Leakage Current
(DQs are disabled; 0V £ Vout £ VDDQ
-5
5
mA
1
IOH
Output High Current, Normal Strength Driver
(VOUT = 1.95 V, VTT = 1.13 V)
- 16.2
mA
1
IOL
Output Low Current, Normal Strength Driver
(VOUT = 0.35 V, VTT = 1.17 V)
16.2
mA
1
VDD
VDDQ
VREF
VTT
II
Parameter
5
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK
5. The ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the
entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Page 52 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Normal Strength Pulldown and Pullup Characteristics
1. The nominal pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve.
2. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage
lie within the outer bounding lines of the V-I curve.
Normal Strength Pulldown Characteristics
140
Maximum
1OUT (mA)
120
100
Nominal High
80
60
Nominal Low
40
Minimum
20
0
0
0.5
1
1.5
2
2.5
VOUT (V)
3. The nominal pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve.
4. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie
within the outer bounding lines of the V-I curve.
Normal Strength Pullup Characteristics
0
-20
Minimum
1OUT (mA)
-40
Nominal Low
-60
-80
-100
-120
-140
Nominal High
-160
Maximum
0
0.5
1
1.5
VOUT (V)
2
2.5
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed
1.7, for device drain to source voltages from 0.1 to 1.0.
6. The full variation in the ratio of the nominal pullup to pulldown current should be unity ± 10%, for device
drain to source voltages from 0.1 to 1.0V.
Page 53 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Normal Strength Pulldown and Pullup Currents
Pulldown Current (mA)
Pullup Current (mA)
Voltage (V)
Nominal
Low
Nominal
High
Min
Max
Nominal
Low
Nominal
High
Min
Max
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10.0
0.2
12.2
13.5
9.2
18.2
-12.2
-14.5
-9.2
-20.0
0.3
18.1
20.1
13.8
26.0
-18.1
-21.2
-13.8
-29.8
0.4
24.1
26.6
18.4
33.9
-24.0
-27.7
-18.4
-38.8
0.5
29.8
33.0
23.0
41.8
-29.8
-34.1
-23.0
-46.8
0.6
34.6
39.1
27.7
49.4
-34.3
-40.5
-27.7
-54.4
0.7
39.4
44.2
32.2
56.8
-38.1
-46.9
-33.2
-61.8
0.8
43.7
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
0.9
47.5
55.2
39.6
69.9
-43.8
-59.4
-38.2
-77.3
1.0
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
1.1
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.9
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Evaluation Conditions for I/O Driver Characteristics
Nominal
Minimum
Maximum
Operating Temperature
25 °C
70 °C
0 °C
VDD / VDDQ
2.5V
2.3V
2.7V
Process Corner
typical
slow-slow
fast-fast
Page 54 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Weak Strength Pulldown and Pullup Characteristics
Weak Strength Pulldown Characteristics
80
Maximum
70
Iout [mA]
60
Typical high
50
Typical low
40
30
Minimum
20
10
0
0,0
0,5
1,0
1,5
2,0
2,5
Vout [V]
1. The weak pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve
2. The weak pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve.
3. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie
within the outer bounding lines of the V-I curve.
Weak Strength Pullup Characteristics
0,0
0,0
0,5
1,0
1,5
2,0
2,5
-10,0
Minimum
-20,0
Iout [V]
-30,0
Typical low
-40,0
-50,0
Typical high
-60,0
-70,0
Maximum
-80,0
Vout [V]
4. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed
1.7, for device drain to source voltages from 0.1 to 1.0.
5. The full variation in the ratio of the nominal pullup to pulldown current should be unity ± 10%, for device
drain to source voltages from 0.1 to 1.0V.
Page 55 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Weak Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA)
Pullup Current (mA)
Voltage (V)
Nominal
Low
Nominal
High
Min
Max
Nominal
Low
Nominal
High
Min
Max
0.1
3.4
3.8
2.6
5.0
-3.5
-4.3
-2.6
-5.0
0.2
6.9
7.6
5.2
9.9
-6.9
-8.2
-5.2
-9.9
0.3
10.3
11.4
7.8
14.6
-10.3
-12.0
-7.8
-14.6
0.4
13.6
15.1
10.4
19.2
-13.6
-15.7
-10.4
-19.2
0.5
16.9
18.7
13.0
23.6
-16.9
-19.3
-13.0
-23.6
0.6
19.6
22.1
15.7
28.0
-19.4
-22.9
-15.7
-28.0
0.7
22.3
25.0
18.2
32.2
-21.5
-26.5
-18.2
-32.2
0.8
24.7
28.2
20.8
35.8
-23.3
-30.1
-20.4
-35.8
0.9
26.9
31.3
22.4
39.5
-24.8
-33.6
-21.6
-39.5
1.0
29.0
34.1
24.1
43.2
-26.0
-37.1
-21.9
-43.2
1.1
30.6
36.9
25.4
46.7
-27.1
-40.3
-22.1
-46.7
1.2
31.8
39.5
26.2
50.0
-27.8
-43.1
-22.2
-50.0
1.3
32.8
42.0
26.6
53.1
-28.3
-45.8
-22.3
-53.1
1.4
33.5
44.4
26.8
56.1
-28.6
-48.4
-22.4
-56.1
1.5
34.0
46.6
27.0
58.7
-28.7
-50.7
-22.6
-58.7
1.6
34.3
48.6
27.2
61.4
-28.9
-52.9
-22.7
-61.4
1.7
34.5
50.5
27.4
63.5
-28.9
-55.0
-22.7
-63.5
1.8
34.8
52.2
27.7
65.6
-29.0
-56.8
-22.8
-65.6
1.9
35.1
53.9
27.8
67.7
-29.2
-58.7
-22.9
-67.7
2.0
35.4
55.0
28.0
69.8
-29.2
-60.0
-22.9
-69.8
2.1
35.6
56.1
28.1
71.6
-29.3
-61.2
-23.0
-71.6
2.2
35.8
57.1
28.2
73.3
-29.5
-62.4
-23.0
-73.3
2.3
36.1
57.7
28.3
74.9
-29.5
-63.1
-23.1
-74.9
2.4
36.3
58.2
28.3
76.4
-29.6
-63.8
-23.2
-76.4
2.5
36.5
58.7
28.4
77.7
-29.7
-64.4
-23.2
-77.7
2.6
36.7
59.2
28.5
78.8
-29.8
-65.1
-23.3
-78.8
2.7
36.8
59.6
28.6
79.7
-29.9
-65.8
-23.3
-79.7
Evaluation Conditions for I/O Driver Characteristics
Nominal
Minimum
Maximum
Operating Temperature
25 °C
70 °C
0 °C
VDD / VDDQ
2.5V
2.3V
2.7V
Process Corner
typical
slow-slow
fast-fast
Page 56 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
IDD Specification and Conditions
(0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR200
-8
Symbol Parameter/Condition
DDR266A
-7
DDR266
-7F
DDR333
-6
typ.
max.
typ.
max.
typ.
max.
typ.
max.
Notes
Unit
4
Operating Current: one bank; active / precharge; tRC = tRC MIN;
DQ, DM, and DQS inputs changing once per clock cycle; address
and control inputs changing once every two clock cycles
x4/x8
70
90
75
100
83
110
85
110
mA
x16
72
95
77
105
86
115
88
115
mA
Operating Current: one bank; active/read/precharge;
burst length 4;
Refer to the following page for detailed test conditions.
x4/x8
80
100
90
110
98
120
100
120
mA
x16
83
105
94
115
102
125
104
125
mA
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE <= VIL MAX
5
7
6
8
6
8
6
9
mA
1, 2
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
IDD2F CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN
= VREF for DQ, DQS and DM.
30
35
35
40
35
40
45
55
mA
1, 2
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; address and other control inputs stable
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
18
22
20
25
20
25
25
28
mA
1, 2
13
16
15
18
15
18
18
21
mA
1, 2
x4/x8
40
45
50
55
50
55
60
65
mA
x16
42
50
52
60
52
60
63
70
mA
x4/x8
79
95
95
115
95
115
110
140
mA
x16
89
110
107
130
107
130
124
160
mA
x4/x8
85
105
105
125
105
125
125
145
mA
x16
96
120
119
140
119
140
141
165
mA
126
170
135
180
135
180
144
190
mA
standard version
1.5
2.5
1.5
2.5
1.5
2.5
1.5
2.5
mA
low power version
1.20
1.25
1.20
1.25
1.20
1.25
1.20
1.25
mA
x4/x8
150
210
171
225
171
225
208
270
x16
158
220
180
235
180
235
218
285
IDD0
IDD1
IDD2P
IDD3P
1, 2
1, 2
Active Power-Down Standby Current: one bank active; power-down mode;
CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Standby Current: one bank active; CS >= VIH MIN;
CKE >= VIH MIN; tRC = tRAS MAX; DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank active; BL2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of
IDD4R
data outputs changing on every clock edge; CL2 for DDR200 and
DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
IDD4W
50% of data outputs changing on every clock edge; CL2 for
DDR200 and DDR266(A), CL3 for DDR333 and DDR400
1, 2
IDD3N
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
IDD6
Self-Refresh Current: CKE <= 0.2V; external clock on
IDD7
Operating Current: four bank; four bank interleaving with burst
length 4;
Refer to the following page for detailed test conditions.
1, 2
1, 2
1, 2, 3
mA
1. IDD specifications are tested after the device is properly initialized and measured
at 100 MHz for DDR200, 133 MHz for DDR266(A) and 166 MHz for DDR333
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters
4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C
Page 57 of 77
1, 2
2003-01-09, V1.1
1, 2
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Detailed test conditions for DDR SDRAM IDD1 and IDD7
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0 mA
2. Timing patterns
- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 * tCK, tRAS = 5 * tCK
Setup: A0 N R0 N N P0 N
Read : A0 N R0 N N P0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0 mA
2. Timing patterns
- DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD= 3 * tCK, Read with autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2
Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Page 58 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
AC Characteristics
(Notes 1-6 apply to the following Tables: Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC
input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between
VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level)
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM
Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC
specification for DDR components
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50W
Output
Timing Reference Point
(VOUT)
30pF
AC Operating Conditions )
(0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
Symbol
Parameter/Condition
VIH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VIL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VID(AC)
Input Differential Voltage, CK and CK Inputs
VIX(AC)
Input Closing Point Voltage, CK and CK Inputs
1.
2.
3.
4.
Min
Max
Unit
Notes
V
1, 2
VREF - 0.31
V
1, 2
VDDQ + 0.6
V
1, 2, 3
V
1, 2, 4
VREF + 0.31
0.7
0.5*VDDQ - 0.2 0.5*VDDQ + 0.2
Input slew rate = 1V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Page 59 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) (Part 1 of 2)
Symbol
DDR200
-8
Parameter
DQ output access time from CK/CK
tAC
tDQSCK DQS output access time from CK/CK
DDR266A
-7
DDR266
-7F
DDR333
-6
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
- 0.8
+ 0.8
- 0.75
+ 0.75
- 0.75
+ 0.75
- 0.7
+ 0.7
ns
1-4
- 0.8
+ 0.8
- 0.75
+ 0.75
- 0.75
+ 0.75
- 0.6
+ 0.6
ns
1-4
tCH
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
tCL
CK low-level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
tHP
Clock Half Period
min (tCL, tCH)
ns
1-4
tCK
tCK
Clock cycle time
tCK
min (tCL, tCH)
min (tCL, tCH)
min (tCL, tCH)
CL = 3.0
8
12
7
12
7
12
6
12
ns
1-4
CL = 2.5
8
12
7
12
7
12
6
12
ns
1-4
CL = 2.0
10
12
7.5
12
7.5
12
7.5
12
ns
1-4
tDH
DQ and DM input hold time
0.6
0.5
0.5
0.45
ns
1-4
tDS
DQ and DM input setup time
0.6
0.5
0.5
0.45
ns
1-4
tIPW
Control & Addr. input pulse width (each
input)
2.5
2.2
2.2
2.2
ns
1-4,10
tDIPW
DQ and DM input pulse width (each input)
2.0
1.75
1.75
1.75
ns
1-4, 10
tHZ
Data-out high-impedence time from
CK/CK
- 0.8
+ 0.8
- 0.75
+ 0.75
- 0.75
+ 0.75
- 0.7
+ 0.7
ns
1-4, 5
tLZ
Data-out low-impedence time from CK/CK
- 0.8
+ 0.8
- 0.75
+ 0.75
- 0.75
+ 0.75
- 0.7
+ 0.7
ns
1-4, 5
tDQSS
Write command to 1st DQS latching
transition
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
1-4
DQS-DQ skew
(DQS & associated DQ
signals)
TSOP66
+ 0.6
+ 0.5
+ 0.5
+ 0.45
ns
1-4
tDQSQ
BGA
+ 0.6
+ 0.5
+ 0.5
+ 0.40
ns
1-4
Data hold skew factor
TSOP66
1.0
0.75
0.75
0.55
ns
1-4
BGA
1.0
0.75
0.75
0.5
ns
1-4
tQHS
tQH
DQ output hold time from DQS
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns
1-4
DQS input low (high) pulse width (write
cycle)
0.35
0.35
0.35
0.35
tCK
1-4
tDSS
DQS falling edge to CK setup time (write
cycle)
0.2
0.2
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK (write
cycle)
0.2
0.2
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
2
2
2
2
tCK
1-4
0
0
0
0
ns
1-4, 7
tCK
1-4, 6
1-4
tDQSL,H
tWPRES Write preamble setup time
tWPST
Write postamble
0.40
tWPRE
Write preamble
0.25
0.25
0.25
0.25
tCK
fast slew rate
1.1
0.9
0.9
0.75
ns
slow slew rate
1.1
1.0
1.0
0.8
ns
fast slew rate
1.1
0.9
0.9
0.75
ns
slow slew rate
1.1
1.0
1.0
0.8
ns
tIS
tIH
Address and control input
setup time
Address and control input
hold time
Page 60 of 77
0.60
0.40
0.60
0.40
0.60
0.40
0.60
2-4,
10,11
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) (Part 2 of 2)
Symbol
DDR200
-8
Parameter
DDR266A
-7
DDR266
-7F
DDR333
-6
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tRPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
1-4
tRPST
Read postamble
0.40
0.60
0.40
0.60
0.40
0.60
0.40
0.60
tCK
1-4
tRAS
Active to Precharge command
50
120,000
45
120,000
45
120,000
42
70,000
ns
1-4
tRC
Active to Active/Auto-refresh command
period
70
65
60
60
ns
1-4
tRFC
Auto-refresh to Active/Auto-refresh command period
80
75
75
72
ns
1-4
tRCD
Active to Read or Write delay
20
20
15
18
ns
1-4
tRP
Precharge command period
20
20
15
18
ns
1-4
tRAP
Active to Autoprecharge delay
20
20
20
18
ns
1-4
tRRD
Active bank A to Active bank B command
15
15
15
12
ns
1-4
tWR
Write recovery time
15
15
15
15
ns
1-4
tDAL
Auto precharge write recovery
+ precharge time
tCK
1-4,9
tWTR
Internal write to read command delay
1
1
1
1
tCK
1-4
tXSNR
Exit self-refresh to non-read command
80
75
75
75
ns
1-4
tXSRD
Exit self-refresh to read command
200
200
200
200
tCK
1-4
tREFI
Average Periodic Refresh Interval (8192
refresh commands per 64ms refresh
period)
ms
1-4, 8
(twr/tck) + (trp/tck)
7.8
7.8
7.8
7.8
1. Input slew rate >= 1V/ns for DDR266 & DDR333 and = 1V/ns for DDR 200
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other
than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage
level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance
(bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS
will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at
this time, depending on tDQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarilty tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between
VOH(ac) and VOL(ac)
Page 61 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles (tCK=133Mhz) (0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V,
tCK = 133MHz
Symbol
Parameter
sort
Units
Notes
2
tCK
1-54
0.25
tCK
1-5
tCK
1-5
Min
tMRD
Mode register set command cycle time
tWPRE
Write preamble
tRAS
Active to Precharge command
tRC
Active to Active/Auto-refresh command period
tRFC
Auto-refresh to Active/Auto-refresh
command period
tRCD
Active to Read or Write delay
tRP
6
Max
16000
DDR266A
9
tCK
1-5
DDR266
8
tCK
1-5
10
tCK
1-5
DDR266A
3
tCK
1-5
DDR266
2
tCK
1-5
DDR266A
3
tCK
1-5
DDR266
2
tCK
1-5
Precharge command period
tRRD
Active bank A to Active bank B command
2
tCK
1-5
tWR
Write recovery time
2
tCK
1-5
tDAL
Auto precharge write recovery + precharge time
5
tCK
1-5
tWTR
Internal write to read command delay
1
tCK
1-5
tXSNR
Exit self-refresh to non-read command
10
tCK
1-5
tXSRD
Exit self-refresh to read command
200
tCK
1-5
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note
3) is VTT.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Page 62 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Timing Diagrams
Data Input (Write)
(Timing Burst Length = 4)
tDQSL
tDQSH
DQS
tDH
tDS
DI n
DQ
tDH
tDS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Data Output (Read)
Don’t Care
(Timing Burst Length = 4)
DQS
tDQSQ max
tQH
DQ
tQH (Data output hold time from DQS)
tDQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration.
t.DQSQ and tQH both apply to each of the four relevant edges of DQS.
tDQSQ max. is used to determine the worst case setup time for controller data capture.
tQH is used to determine the worst case hold time for controller data capture.
Page 63 of 77
2003-01-09, V1.1
Page 64 of 77
tVTD
High-Z
High-Z
200ms
Power-up:
VDD and CK
stable
LVCMOS LOW LEVEL
Don’t Care
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
DM
Command
CKE
CK
CK
VREF
VTT (System*)
VDDQ
VDD
tIH
tIH
NOP
tIS
tIS
tCH
tIS
tIH
PRE
tCL
tIH
tIH
tIH
BA1=L
BA0=H
tIS
CODE
tIS
CODE
tIS
EMRS
tIH
CODE
CODE
MRS
tMRD
Load Mode
Register
(with A8 = L)
BA0=L
AR
tRFC
BA1=L
AR
tRFC
200 cycles of CK**
BA0=L
ALL BANKS
tIS
PRE
tRP
BA1=L
CODE
CODE
MRS
tMRD
Load Mode
Register, Reset DLL
tMRD
Extended Mode
Register Set
ALL BANKS
tCK
The two Autorefresh commands may be moved to follow the first MRS,
but precede the second Precharge All command.
** tMRD is required before any command can be applied and
200 cycles of CK are required before a Read command can be applied.
* VTT is not applied directly to the device, however tVTD must be
greater than or equal to zero to avoid device latchup.
BA
RA
RA
ACT
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Initialize and Mode Register Sets
2003-01-09, V1.1
Page 65 of 77
tIH
tIH
tIH
VALID
tIS
VALID*
tIS
tIS
tCK
Enter Power
Down Mode
NOP
tIS
tCH
tCL
No column accesses are allowed to be in progress at the time power down is entered.
* = If this command is a Precharge (or if the device is already in the idle state) then the power down mode
shown is Precharge power down. If this command is an Active (or if at least one row is already active), then
the power down mode shown is Active power down.
DM
DQ
DQS
ADDR
Command
CKE
CK
CK
Exit Power
Down Mode
NOP
tIS
Don’t Care
VALID
VALID
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Power Down Mode
2003-01-09, V1.1
Page 66 of 77
tIH
tIH
NOP
AR
NOP
AR
NOP
VALID
tRFC
NOP
ACT
tIH
BANK(S)
tIS
ONE BANK
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
DM
DQ
DQS
BA0, BA1
A10
Don’t Care
BA
RA
RA
ALL BANKS
NOP
tRFC
A9, A11,A12
PRE
VALID
tCL
RA
NOP
tIS
tIS
tCK
tRP
A0-A8
Command
CKE
CK
CK
tCH
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Auto Refresh Mode
2003-01-09, V1.1
Page 67 of 77
DM
DQ
DQS
ADDR
Command
CKE
CK
CK
NOP
tIH
tIH
tCH
tCK
tIS
AR
Enter Self
Refresh Mode
tCL
* = Device must be in the all banks idle state before entering Self Refresh Mode.
** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK).
are required before a Read command can be applied.
tIS
tIS
tRP*
Exit Self
Refresh Mode
NOP
tXSRD, tXSRN
tIS
200 cycles
tIH
Don’t Care
VALID
tIS
VALID
Clock must be stable before exiting Self Refresh Mode
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Self Refresh Mode
2003-01-09, V1.1
Page 68 of 77
Case 2:
tAC/tDQSCK = max
Case 1:
tAC/tDQSCK = min
tIH
tIH
NOP
tIS
tIS
tIH
tIH
tIH
BA x
tIS
DIS AP
tIS
COL n
tIS
Read
tCK
CL=2
tLZ (max)
tLZ (max)
tRPRE
NOP
DO n
tAC (max)
DO n
tAC (min)
BA x*
ONE BANK
ALL BANKS
PRE
tCL
tLZ (min)
tRPRE
NOP
tCH
NOP
tDQSCK (max)
NOP commands are shown for ease of illustration; other commands may be valid at these times.
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
BA x
RA
RA
ACT
tHZ (max)
tRPST
tHZ (min)
tIH
tDQSCK (min)
tRPST
tRP
3 subsequent elements of data out are provided in the programmed order following DO n.
DO n = data out from column n.
DQ
DQS
DQ
DQS
DM
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
NOP
VALID
NOP
VALID
Don’t Care
NOP
VALID
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Read without Auto Precharge (Burst Length = 4)
2003-01-09, V1.1
Page 69 of 77
Case 2:
tAC/tDQSCK = max
Case 1:
tAC/tDQSCK = min
DQ
DQS
DQ
DQS
DM
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tIH
BA x
tIS
EN AP
tIS
COL n
tIS
Read
tLZ (max)
tRPRE
tLZ (max)
CL=2
tLZ (min)
NOP
DO n
tAC (max)
DO n
tAC (min)
NOP
tCL
tLZ (min)
tRPRE
NOP
tCH
tHZ (min)
BA x
RA
RA
ACT
tDQSCK (max)
tHZ (max)
tRPST
NOP
tIH
tDQSCK (min)
tRPST
tRP
NOP
VALID
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
EN AP = enable Auto Precharge.
ACT = active; RA = row address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
NOP
tIS
tIS
tCK
NOP
VALID
Don’t Care
NOP
VALID
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Read with Auto Precharge (Burst Length = 4)
2003-01-09, V1.1
Page 70 of 77
tIH
tIH
DQ
DQS
DQ
BA x
tIH
tRCD
NOP
tCH
tIH
tRAS
BA x
DIS AP
tIS
COL n
Read
tCL
tLZ (max)
NOP
DO n
tAC (max)
DO n
tAC (min)
BA x*
ONE BANK
tLZ (max)
tRPRE
tLZ (min)
CL=2
PRE
ALL BANKS
tRC
tLZ (min)
tRPRE
NOP
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
DIS AP = disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
Case 2:
tAC/tDQSCK = max
Case 1:
tAC/tDQSCK = min
DQS
DM
BA0, BA1
tIS
RA
tIH
A10
tIS
ACT
RA
NOP
tIS
tIS
A0-A9, A11, A12
Command
CKE
CK
CK
tCK
BA x
RA
RA
ACT
tHZ (max)
tHZ (min)
tRPST
tDQSCK (max)
tDQSCK (min)
tRPST
tRP
NOP
Don’t Care
NOP
VALID
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Bank Read Access (Burst Length = 4)
2003-01-09, V1.1
Page 71 of 77
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tWPRES
tDQSS
tIH
BA x
tIS
DIS AP
tIS
COL n
tIS
Write
DIn
tDQSH
tWPRE
NOP
tDQSL
tCH
tCL
NOP
tWPST
tDSH
NOP
tIH
NOP
tWR
PRE
BA x*
ONE BANK
ALL BANKS
tDQSS = min.
DIn = Data in for column n.
3 subsequent elements of data in are applied in the programmed order following DIn.
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
NOP
tIS
tIS
tCK
NOP
VALID
tRP
NOP
Don’t Care
BA
RA
RA
ACT
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write without Auto Precharge (Burst Length = 4)
2003-01-09, V1.1
Page 72 of 77
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tWPRE
tWPRES
tDQSS
tIH
BA x
tIS
EN AP
tIS
COL n
tIS
Write
DIn
tDQSH
NOP
tCH
tDQSL
NOP
tCL
tWPST
tDSH
NOP
NOP
VALID
tWR
DIn = Data in for column n.
3 subsequent elements of data in are applied in the programmed order following DIn.
EN AP = Enable Auto Precharge.
ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tDQSS = min.
tIH
tIH
NOP
tIS
tIS
tCK
NOP
VALID
tDAL
NOP
VALID
tRP
NOP
Don’t Care
BA
RA
RA
ACT
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write with Auto Precharge (Burst Length = 4)
2003-01-09, V1.1
Page 73 of 77
tIH
tIH
DM
DQ
DQS
BA0, BA1
tRCD
NOP
tCH
tIH
tWPRES
BA x
tDQSS
DIS AP
tIS
Col n
Write
tCL
DIn
tDSH
tDQSL
tWPRE
tDQSH
NOP
tRAS
NOP
tWPST
NOP
tDQSS = min.
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n.
DIS AP = Disable Auto Precharge.
* = don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tIH
tIH
BA x
tIS
RA
A10
tIS
ACT
RA
NOP
tIS
tIS
A0-A9, A11, A12
Command
CKE
CK
CK
tCK
tWR
NOP
BA x
ONE BANK
ALL BANKS
PRE
Don’t Care
NOP
VALID
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Bank Write Access (Burst Length = 4)
2003-01-09, V1.1
Page 74 of 77
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tIH
tWPRES
BA x
tIS
tDQSS
DIS AP
tIS
COL n
tIS
Write
DIn
tDQSH
NOP
tCH
tDQSL
tCL
NOP
tWPST
tDSH
tDSS
NOP
tWR
NOP
BA x*
ONE BANK
ALL BANKS
PRE
NOP
VALID
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked).
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tDQSS = min.
NOP
tIS
tIS
tCK
tRP
NOP
Don’t Care
BA
RA
RA
ACT
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Write DM Operation (Burst Length = 4)
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Package Dimensions
60 balls FBGA-Package
12mm x 8mm
0 ,3
Lead #1
Page 75 of 77
±0,0 8
0 ,8 0 5 R E F
2 2 ,2 2 ±0 ,1 3
G a u g e P la n e
1 0 ,1 6 ±0 ,1 3
0,25 Basic
0 ,6 5 B a s ic
1,20 max
0,05 min
Plastic Package, P-TSOPII-66
(400mil; 66 lead)
Thin Small Outline Package
0 .1
S e a tin g P la n e
0 ,5 ±0 ,1
1 1 ,7 6 ±0 ,2
TSOP66
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data Sheet Jan. 2003, V1.1
TABLE OF CONTENT
Features
1
Description
Pin Configuration TSOP
Pin Configuration BGA
Input/Output Functional Description
Ordering Information
Block Diagram (32Mb x 4)
Block Diagram (16Mb x 8)
Block Diagram (8Mb x 16)
1
2
3
4
5
6
7
8
Functional Description
Initialization
Register Definition
Mode Register Operation
Burst Definition
Required CAS Latencies
Extended Mode Register
Extended Mode Register Definition
9
10
10
11
12
13
14
15
Commands
Delesect, No Operation
Mode Register Set
Active
Read
Write
Precharge
Auto Precharge
Burst Terminate
Auto Refresh
Self Refresh
Truth Table 1a: Commands
Truth Table 1b: DM Operation
16
16
16
16
16
16
16
17
17
17
17
18
18
Operations
Activating a Specific Row in a Specific Bank
tRCD and tRRD Definition
Read Command
Read Burst
Consecutive Read Bursts
Non-Consecutive Read Bursts
Random Read Accesses
Terminating a Read Burst
Read to Write
Read to Precharge
Write Command
Write Burst (Burst Length = 4)
Write to Write (Burst Length = 4)
19
19
20
21
22
23
24
25
26
27
29
30
32
33
2003-01-09, V1.1
Write to Write
Random Write Cycles
Write to Read
Write to Read Interrupting
Write to Read: Minimum DQSS
Write to Read: Nominal DQSS
Write to Precharge Non-Interrupting
Write to Precharge Interrupting
Write to Precharge Minimum DQSS
Write to Precharge: Nominal DQSS
Precharge
Power-Down
34
35
36
37
38
40
40
41
42
43
44
45
Truth Table 2: Clock Enable (CKE)
Truth Table 3: Current State, SameBank)
Truth Table 4: Current State,Different Bank
Truth Table 5: Concurrent Auto Precharge
46
47
48
49
Simplified State Diagram
50
Operating Conditions
Absolute Maximum Ratings
Input and Output Capacitances
DC Electrical Operating Conditions
Normal Strength Characterisitcs
Weak Strength Characterisitcs
IDD Specifications and Conditions
AC Characteristics
AC Output Load Circuit Diagram
Electrical Characteristics & AC Timing
51
51
51
52
53
55
57
59
59
60
Timing Diagrams
Data Input (Write)
Data Output (Read)
Initialize and Mode Register Sets
Power Down Mode
Auto Refresh Mode
Self Refresh Mode
Read without Auto Precharge
Read with Auto Precharge
Bank Read Access
Write without Auto Precharge.
Write with Auto Precharge
Bank Write Access
Write DM Operation
63
63
63
64
65
66
67
68
69
70
71
72
73
74
Package Dimensions
Table of Content
Security Information
75
76
77
Page 76 of 77
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data Sheet Jan. 2003, V1.1
Attention please !
As far as patents or other rights of third parties are concerned, liability is only
assumed for components, not for applications, processes and circuits
implemented within components or assemblies. This information describes
the type of components and shall not be considered as assured
characteristics. Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact INFINEON
Technologies Offices in Munich or the INFINEON Technologies Sales Offices
and Representatives worldwide.
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact your
nearest INFINEON Technologies office or representative.
Packing
Please use the recycling operators known to you. We can help you - get in
touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport. For packing
material that is returned to us unsorted or which we are not obliged to accept,
we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly
authorized for such purpose!
Critical components1 of INFINEON Technologies, may only be used in lifesupport devices or systems2 with the express written approval of INFINEON
Technologies.
1. A critical component is a component used in a life-support device or system
whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device
or system.
2. Life support devices or systems are intended (a) to be implanted in the
human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
2003-01-09, V1.1
Page 77 of 77
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