Cypress CY7C09379V-6AC 3.3v 16k/32k/64k x 16/18 synchronous dual-port static ram Datasheet

25/0251
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
• 3 Modes
— Flow-Through
• High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns
(max.)
• 3.3V low operating power
— Active = 115 mA (typical)
— Standby = 10 µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
•
•
•
•
•
— Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Upper and Lower Byte Controls for Bus Matching
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
LBL
1
CE0R
CE1R
LBR
1
0
0
0/1
0/1
OEL
OER
0/1
FT/PipeL
1b 0b 1a 0a
b
0a 1a 0b 1b
a
a
b
0/1
8/9
[3]
FT/PipeR
8/9
I/O8/9L–I/O15/17L
[4]
[3]
I/O8/9R–I/O15/17R
I/O
Control
8/9
I/O
Control
8/9
I/O0L–I/O7/8L
[5]
A0L–A13/14/15L
CLKL
ADSL
CNTENL
CNTRSTL
[4]
I/O0R–I/O7/8R
14/15/16
14/15/16
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
[5]
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06056 Rev. **
Revised September 21, 2001
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Functional Description
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to
any location in memory.[6] Registers on control, address, and
data lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow-through
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available tCD1 = 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter Reset (CNTRST) is
used to reset the burst counter.
Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW
to HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
[7]
[8]
[9]
A9L
1
75
A9R
A10L
2
74
A10R
A11L
3
73
A11R
A12L
4
72
A12R
A13L
5
71
A13R
A14L
6
70
A14R
A15L
7
69
A15R
[7]
[8]
NC
8
68
NC
NC
9
67
NC
LBL
10
66
LBR
UBL
11
65
UBR
CE0L
12
64
CE0R
CE1L
13
63
CE1R
CNTRSTL
14
62
CNTRSTR
VCC
15
61
GND
R/WL
16
60
R/WR
OEL
17
59
OER
FT/PIPEL
18
58
FT/PIPER
GND
19
57
GND
I/O15L
20
56
I/O15R
I/O14L
21
55
I/O14R
I/O13L
22
54
I/O13R
I/O12L
23
53
I/O12R
I/O11L
24
52
I/O11R
I/O10L
25
51
I/O10R
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
[9]
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
6. When writing simultaneously to the same location, the final value cannot be guaranteed.
7. This pin is NC for CY7C09269V.
8. This pin is NC for CY7C09269V and CY7C09279V.
9. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5V x16 flow-through device.
Document #: 38-06056 Rev. **
Page 2 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Configurations (continued)
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
1
75
A8R
A10L
2
74
A9R
A11L
3
73
A10R
A12L
4
72
A11R
A13L
5
71
A12R
[10]
A14L
6
70
A13R
[11]
A15L
7
69
A14R
LBL
8
68
A15R
[10]
[11]
UBL
9
67
LBR
CE0L
10
66
UBR
CE1L
11
65
CE0R
CNTRSTL
12
64
CE1R
R/WL
13
63
CNTRSTR
OEL
14
62
R/WR
VCC
15
61
GND
FT/PIPEL
16
60
OER
I/O17L
17
59
FT/PIPER
I/O16L
18
58
I/O17R
GND
19
57
GND
I/O15L
20
56
I/O16R
I/O14L
21
55
I/O15R
I/O13L
22
54
I/O14R
1/012L
23
53
I/O13R
I/O11L
24
52
I/O12R
I/O10L
25
51
I/O11R
CY7C09389V (64K x 18)
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
I/10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/01R
I/O0R
GND
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V
CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V
-6[1, 2]
-7[2]
-9
-12
fMAX2 (MHz) (Pipelined)
100
83
67
50
Max. Access Time (ns)
(Clock to Data,
Pipelined)
6.5
7.5
9
12
Typical Operating
Current ICC (mA)
175
155
135
115
Typical Standby Current
for ISB1 (mA) (Both
Ports TTL Level)
25
25
20
20
Typical Standby Current
for ISB3 (µA) (Both Ports
CMOS Level)
10 µA
10 µA
10 µA
10 µA
Notes:
10. This pin is NC for CY7C09369V.
11. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. **
Page 3 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Definitions
Left Port
Right Port
Description
A0L–A15L
A0R–A15R
Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L
I/O0R–I/O17R
Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBL
LBR
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UBL
UBR
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ........................................... >1100V
Latch-Up Current...................................................... >200mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Ambient
Temperature
VCC
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to VCC+0.5V
Commercial
0°C to +70°C
3.3V ± 300 mV
–40°C to +85°C
3.3V ± 300 mV
DC Input Voltage......................................–0.5V to VCC+0.5V
Document #: 38-06056 Rev. **
Industrial
Page 4 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Electrical Characteristics Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Output HIGH Voltage (VCC = Min.
lOH = –4.0 mA)
VOL
Output LOW Voltage (VCC = Min.
lOH = +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
ISB1
ISB2
ISB3
ISB4
2.4
2.4
175 320
Indust.
Standby Current (Both
Com’l.
Ports TTL Level)[12] CEL & Indust.
CER ≥ VIH, f = fMAX
25
95
Standby Current (One Port Com’l.
TTL Level)[12] CEL | CER ≥ Indust.
VIH, f = fMAX
115 175
Standby Current (Both
Com’l.
Ports CMOS Level)[12] CEL Indust.
& CER ≥ VCC – 0.2V, f = 0
10
Standby Current (One Port Com’l.
CMOS Level)[12] CEL | CER Indust.
≥ VIH, f = fMAX
105 135
250
10
10
155 275
135
230
275 390
185
300
25
85
20
75
85
120
35
85
105 165
95
155
165 210
105
165
10
250
10
250
10
250
10
250
95
125
85
115
125 170
95
125
V
V
0.8
–10
Unit
Max.
Typ.
Max.
Typ.
Min.
Min.
0.4
2.0
0.8
–10
V
0.4
2.0
0.8
10
2.4
0.4
2.0
–10
-12
2.4
0.4
2.0
Com’l.
-9
Max.
Typ.
Min.
-7[2]
Max.
Description
VOH
Typ.
Parameter
Min.
-6[1, 2]
–10
115
0.8
V
10
µA
180 mA
mA
20
70
mA
mA
85
140 mA
mA
10
250
µA
µA
75
100 mA
mA
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
10
pF
10
pF
Note:
12. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Document #: 38-06056 Rev. **
Page 5 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
AC Test Loads
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
RTH = 250Ω
OUTPUT
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
C = 5 pF
R2 = 435Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to -6 and -7 only)[13]
Z0 = 50Ω
OUTPUT
ALL INPUT PULSES
R = 50Ω
3.0V
C
GND
90%
10%
90%
10%
≤ 3 ns
≤ 3 ns
VTH = 1.4V
(a) Load 1 (-6 and -7 only)
0. 60
∆ (ns) for all -7 access times
0. 50
0. 40
0. 30
0. 20
0. 1 0
0. 00
10
15
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
13. Test Conditions: C = 10 pF.
Document #: 38-06056 Rev. **
Page 6 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Characteristics Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
tF
tSA
tHA
tSC
tHC
tSW
tHW
tSD
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
tOLZ[14,15]
tOHZ[14,15]
tCD1
tCD2
tDC
tCKZ[14,15]
tCKZ[14,15]
fMax Flow-Through
fMax Pipelined
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
Clock Fall Time
Address Set-Up Time
Address Hold Time
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
R/W Hold Time
Input Data Set-Up Time
Input Data Hold Time
ADS Set-Up Time
ADS Hold Time
CNTEN Set-Up Time
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
53
100
19
10
6.5
6.5
4
4
22
12
7.5
7.5
5
5
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
3.5
0
2
2
2
9
2
2
2
9
3
3
4
1
4
1
4
1
4
1
4
1
5
1
4
1
10
2
1
2
2
2
7
20
9
9
12
2
1
2
2
2
7
25
12
9
Unit
Max.
Min.
30
20
12
12
8
8
4
1
4
1
4
1
4
1
4
1
5
1
4
1
7
18
7.5
33
50
3
3
9
2
1
Max.
25
15
12
12
6
6
4
0
4
0
4
0
4
0
4
0
4.5
0
4
0
7
15
6.5
40
67
3
3
8
-12
Min.
45
83
3
3
2
1
Max.
Description
-9
Min.
Min.
Parameter
-7[2]
Max.
-6[1, 2]
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Port to Port Delays
tCWDD
tCCS
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
30
9
35
10
40
15
40
15
ns
ns
Notes:
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06056 Rev. **
Page 7 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
An
ADDRESS
An+1
An+2
An+3
tCKHZ
tDC
tCD1
DATAOUT
Qn
Qn+1
Qn+2
tDC
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSW
tSA
tHW
tHA
tSC
tHC
CE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = VIL, CNTEN and CNTRST = VIH.
18. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
Document #: 38-06056 Rev. **
Page 8 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Bank Select Pipelined Read[20, 21]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE0(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
tDC
A0
ADDRESS(B2)
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
D3
D1
D0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE0(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
D4
D2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL
NO
MATCH
MATCH
tHD
tSD
DATAINL
VALID
tCCS
CLKR
R/WR
tCD1
tSW
tSA
ADDRESSR
tHW
tHA
NO
MATCH
MATCH
tCWDD
DATAOUTR
tCD1
VALID
tDC
VALID
tDC
Notes:
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
21. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
24. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
25. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06056 Rev. **
Page 9 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
An+2
An+2
An+3
An+4
tSD tHD
tHA
DATAIN
tCD2
tCKHZ
Dn+2
tCD2
tCKLZ
Qn
DATAOUT
READ
Qn+3
NO OPERATION
WRITE
READ
[19, 26, 27, 28]
Pipelined Read-to-Write-to-Read (OE Controlled)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCKLZ
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes:
26. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
27. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
28. During “No Operation”, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06056 Rev. **
Page 10 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 27, 28]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
An+1
tSA
DATAIN
An+2
An+2
tSD
tHA
An+3
tHD
Dn+2
tCD1
tCD1
DATAOUT
An+4
tCD1
Qn
Qn+1
tDC
tCKHZ
READ
tCD1
Qn+3
tCKLZ
NO
OPERATION
WRITE
tDC
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 19, 26, 27, 28]
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
DATAIN
tSD
tHA
DATAOUT
Dn+2
tDC
tCD1
tHD
Dn+3
tOE
tCD1
Qn
tCD1
Qn+4
tOHZ
tCKLZ
tDC
OE
READ
Document #: 38-06056 Rev. **
WRITE
READ
Page 11 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[29]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx-1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Qn
Qn+1
tDC
READ WITH COUNTER
Qn+2
COUNTER HOLD
Qn+3
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[29]
tCH1
tCYC1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
tCD1
Qx
Qn
Qn+1
Qn+2
Qn+3
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ
WITH
COUNTER
Note:
29. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Document #: 38-06056 Rev. **
Page 12 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[30, 31]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Notes:
30. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
31. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Document #: 38-06056 Rev. **
Page 13 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[19, 26, 32, 33]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
AX
0
tSW
tHW
tSD
tHD
1
An+1
An
An+1
R/W
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
ADS
CNTEN
CNTRST
DATAIN
D0
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
Q1
Qn
READ
ADDRESS n
Notes:
32. CE0, UB, and LB = VIL; CE1 = VIH.
33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06056 Rev. **
Page 14 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Read/Write and Enable Operation[34, 35, 36]
Inputs
OE
CLK
CE0
Outputs
CE1
R/W
I/O0–I/O17
Operation
[37]
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected[37]
X
L
H
L
DIN
L
L
H
H
DOUT
Read[35]
L
H
X
High-Z
Outputs Disabled
H
X
Write
Address Counter Control Operation[34, 38, 39, 40]
Address
Previous
Address
X
CLK
ADS
CNTEN
CNTRST
I/O
Mode
Operation
X
X
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
H
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
Notes:
34. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
35. ADS, CNTEN, CNTRST = “Don’t Care”.
36. OE is an asynchronous input signal.
37. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
38. CE0 and OE = VIL; CE1 and R/W = VIH.
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE0 and CE1.
Document #: 38-06056 Rev. **
Page 15 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns)
[1, 2]
6.5
7.5[2]
9
12
Ordering Code
Package Name
Package Type
Operating Range
CY7C09269V-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09269V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09269V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09269V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C09269V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
32K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns)
6.5
[1, 2]
Ordering Code
Package Name
Package Type
Operating Range
CY7C09279V-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5[2]
CY7C09279V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09279V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09279V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C09279V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
12
64K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
6.5[1, 2]
CY7C09289V-6AC
A100
100-Pin Thin Quad Flat Pack
7.5[2]
CY7C09289V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09289V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09289V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
12
CY7C09289V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
Commercial
16K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
6.5[1, 2]
CY7C09369V-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5[2]
CY7C09369V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5[2]
CY7C09369V-7AI
A100
100-Pin Thin Quad Flat Pack
Industrial
9
CY7C09369V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09369V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C09369V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
12
32K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
6.5[1, 2]
CY7C09379V-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5[2]
CY7C09379V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09379V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09379V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
12
CY7C09379V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
Document #: 38-06056 Rev. **
Page 16 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
64K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns)
[1, 2]
Ordering Code
Package Name
Package Type
Operating Range
CY7C09389V-6AC
A100
100-Pin Thin Quad Flat Pack
Commercial
7.5[2]
CY7C09389V-7AC
A100
100-Pin Thin Quad Flat Pack
Commercial
9
CY7C09389V-9AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C09389V-9AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C09389V-12AC
A100
100-Pin Thin Quad Flat Pack
Commercial
6.5
12
Document #: 38-06056 Rev. **
Page 17 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
Document #: 38-06056 Rev. **
Page 18 of 19
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K X 16/18 Synchronous Dual Port Static
RAM
Document Number: 38-06056
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110215
12/18/01
SZV
Document #: 38-06056 Rev. **
Description of Change
Change from Spec number: 38-00668 to 38-06056
Page 19 of 19
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