LINER LTC4000 High voltage high current controller for battery charging with maximum power point control Datasheet

LTC4000-1
High Voltage High Current
Controller for Battery Charging with
Maximum Power Point Control
Description
Features
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Maximum Power Control: Solar Panel Input
Compatible
Complete High Performance Battery Charger When
Paired with a DC/DC Converter
Wide Input and Output Voltage Range: 3V to 60V
Input Ideal Diode for Low Loss Reverse Blocking
and Load Sharing
Output Ideal Diode for Low Loss PowerPath™ and
Load Sharing with the Battery
Programmable Charge Current: ±1% Accuracy
±0.25% Accurate Programmable Float Voltage
Programmable C/X or Timer Based Charge
Termination
NTC Input for Temperature Qualified Charging
28-Lead 4mm × 5mm QFN or SSOP Packages
The LTC®4000-1 is a high voltage, high performance
controller that converts many externally compensated
DC/DC power supplies into full-featured battery chargers
with maximum power point control. In contrast to the
LTC4000, the LTC4000-1 has an input voltage regulation
loop instead of the input current regulation loop.
Features of the LTC4000-1’s battery charger include:
accurate (±0.25%) programmable float voltage, selectable timer or current termination, temperature qualified
charging using an NTC thermistor, automatic recharge,
C/10 trickle charge for deeply discharged cells, bad battery
detection and status indicator outputs. The battery charger
also includes precision current sensing that allows lower
sense voltages for high current applications.
The LTC4000-1 supports intelligent PowerPath control. An
external PFET provides low loss reverse current protection. Another external PFET provides low loss charging
or discharging of the battery. This second PFET also
facilitates an instant-on feature that provides immediate
downstream system power even when connected to a
heavily discharged or shorted battery.
Applications
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Solar Powered Battery Charger Systems
Battery Charger with High Impedance Input Source,
e.g., Fuel Cell or Wind Turbine
Battery Equipped Industrial or Portable Military
Equipments
The LTC4000-1 is available in a low profile 28-lead
4mm × 5mm QFN and SSOP packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
10.8V at 10A Charger for Three LiFePO4 Cells with a Solar Panel Input
5mΩ
IN
LT3845A
Si7135DP
OUT
VC
100µF
14.7k
ITH
1.15M
47nF
CC
IID IGATE CSP
5mΩ
CSN
BGATE
Si7135DP
BAT
CLN
IN
OFB
127k
LTC4000-1
1µF
332k
FBG
133k
IFB
20k
BFB
3V
1.13M
NTC
IIMON
TMR
CL
10nF
0.1µF
24.9k
10k
GND BIAS
CX
22.1k
Solar Panel Input Regulation,
Achieves Max Power Point
to Greater than 98%
VOUT
12V, 15A
1µF
10k
VBAT
10.8V FLOAT
10A MAX CHARGE
CURRENT
3-CELL LiFePO4
BATTERY PACK
20
INPUT REGULATION VOLTAGE: VINREG (V)
SOLAR PANEL INPUT
<60V OPEN
CIRCUIT VOLTAGE
17.6V PEAK
POWER VOLTAGE
TA = 25°C
18
16
14
98% TO 95% PEAK POWER
12
100% TO 98% PEAK POWER
10
1
5
6
7
8
9
2
3
4
CHARGER OUTPUT CURRENT: IRCS (A)
10
40001 TA01b
40001 TA01a
40001f
1
LTC4000-1
Absolute Maximum Ratings
(Note 1)
IN, CLN, IID, CSP, CSN, BAT........................ –0.3V to 62V
IN-CLN, CSP-CSN.............................................–1V to 1V
OFB, BFB, FBG............................................ –0.3V to 62V
FBG.............................................................–1mA to 2mA
IGATE............Max (VIID, VCSP) – 10V to Max (VIID, VCSP)
BGATE........Max (VBAT, VCSN) – 10V to Max (VBAT, VCSN)
ENC, CX, NTC, VM....................................–0.3V to VBIAS
IFB, CL, TMR, IIMON, CC..........................–0.3V to VBIAS
BIAS..............................................–0.3V to Min (6V, VIN)
IBMON...................................–0.3V to Min (VBIAS, VCSP)
ITH................................................................ –0.3V to 6V
CHRG, FLT, RST........................................... –0.3V to 62V
CHRG, FLT, RST...........................................–1mA to 2mA
Operating Junction Temperature Range
(Note 2).................................................................. 125°C
Lead Temperature (Soldering, 10 sec)
SSOP Package................................................... 300°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
TOP VIEW
26 RST
CL
4
25 VM
TMR
5
24 GND
GND
6
23 IN
FLT
7
22 CLN
CHRG
8
21 CC
BIAS
9
20 ITH
NTC 10
19 IID
FBG 11
18 IGATE
BFB 12
17 OFB
BAT 13
16 CSP
BGATE 14
15 CSN
ITH
27 IIMON
3
CC
2
CX
CLN
IBMON
28 27 26 25 24 23
IN
28 IFB
GND
ENC
1
IID
TOP VIEW
22 IGATE
VM 1
RST 2
21 OFB
IIMON 3
20 CSP
IFB 4
19 CSN
29
GND
ENC 5
18 BGATE
IBMON 6
17 BAT
CX 7
16 BFB
CL 8
15 FBG
NTC
BIAS
CHRG
FLT
GND
TMR
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 80°C/W, θJC = 25°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4000EUFD-1#PBF
LTC4000EUFD-1#TRPBF
40001
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC4000IUFD-1#PBF
LTC4000IUFD-1#TRPBF
40001
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC4000EGN-1#PBF
LTC4000EGN-1#TRPBF
LTC4000GN-1
28-Lead Plastic SSOP
–40°C to 125°C
LTC4000IGN-1#PBF
LTC4000IGN-1#TRPBF
LTC4000GN-1
28-Lead Plastic SSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
40001f
2
LTC4000-1
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3).
SYMBOL
PARAMETER
VIN
Input Supply Operating Range
IIN
Input Quiescent Operating Current
IBAT
Battery Pin Operating Current
Battery Only Quiescent Current
CONDITIONS
MIN
l
TYP
3
MAX
60
0.4
UNITS
V
mA
VIN ≥ 3V, VCSN = VCSP ≥ VBAT
l
50
100
µA
VIN = 0V, VCSN = VCSP ≤ VBAT
l
10
20
μA
0.4
V
Shutdown
ENC Input Voltage Low
l
ENC Input Voltage High
l
1.5
–4
–2
l
1.5
2.5
l
0.985
1.000
ENC Pull-Up Current
VENC = 0V
ENC Open Circuit Voltage
VENC = Open
V
–0.5
µA
V
Voltage Regulation
VIFB_REG
Input Feedback Voltage
IFB Input Current
VBFB_REG
± 0.1
Battery Feedback Voltage
BFB Input Current
VOFB_REG
VIFB = 1.0V
OFB Input Current
l
1.133
1.120
1.136
1.136
l
1.176
1.193
VBFB = 1.2V
Output Feedback Voltage
RFBG
Ground Return Feedback Resistance
Rising Recharge Battery Threshold Voltage
VRECHRG(HYS)
Recharge Battery Threshold Voltage Hysteresis % of VBFB_REG
1.139
1.147
l
96.9
VOUT(INST_ON)
Instant-On Battery Voltage Threshold
% of VBFB_REG
VLOBAT
Falling Low Battery Threshold Voltage
% of VBFB_REG
l
VLOBAT(HYS)
Low Battery Threshold Voltage Hysteresis
% of VBFB_REG
V
µA
100
400
Ω
97.6
98.3
%
0.5
l
V
V
µA
1.204
± 0.1
l
% of VBFB_REG
V
µA
± 0.1
VOFB = 1.2V
VRECHRG(RISE)
1.010
%
82
86
90
%
65
68
71
%
3
%
Current Monitoring and Regulation
VOS
Ratio of Monitored-Current Voltage to Sense
Voltage
VIN,CLN ≤ 50mV, VIIMON/VIN,CLN
VCSP,CSN ≤ 50mV, VIBMON/VCSP,CSN
Sense Voltage Offset
VCSP,CSN ≤ 50mV, VCSP = 60V or
VIN,CLN ≤ 50mV, VIN = 60V (Note 4)
CLN, CSP, CSN Common Mode Range
(Note 4)
l
l
18.5
21
V/V
–300
300
µV
3
60
V
CLN Pin Current
20
±1
µA
CSP Pin Current
VIGATE = Open, VIID = 0V
90
μA
CSN Pin Current
VBGATE = Open, VBAT = 0V
45
μA
ICL
Pull-Up Current for the Charge Current Limit
Programming Pin
ICL_TRKL
Pull-Up Current for the Charge Current Limit
Programming Pin in Trickle Charge Mode
VBFB < VLOBAT
l
–55
–50
–45
μA
l
–5.5
–5.0
–4.5
μA
40
90
140
kΩ
Input Current Monitor Resistance to GND
Charge Current Monitor Resistance to GND
A5 Error Amp Offset for the Charge Current
Loop (See Figure 1)
Maximum Programmable Current Limit
Voltage Range
VCL = 0.8V
40
90
140
kΩ
l
–10
0
10
mV
l
0.985
1.0
1.015
V
40001f
3
LTC4000-1
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Charge Termination
CX Pin Pull-Up Current
VCX = 0.1V
l
–5.5
–5.0
–4.5
µA
VCX,IBMON(OS)
CX Comparator Offset Voltage, IBMON Falling
VCX = 0.1V
l
0.5
10
25
mV
VCX,IBMON(HYS)
CX Comparator Hysteresis Voltage
5
mV
TMR Pull-Up Current
VTMR = 0V
–5.0
μA
TMR Pull-Down Current
VTMR = 2V
5.0
μA
TMR Pin Frequency
CTMR = 0.01μF
400
500
600
Hz
2.1
2.5
V
tT
Charge Termination Time
CTMR = 0.1μF
l
2.3
2.9
3.5
h
tT/tBB
Ratio of Charge Terminate Time to Bad Battery CTMR = 0.1μF
Indicator Time
l
3.95
4
4.05
h/h
VNTC(COLD)
NTC Cold Threshold
VNTC Rising, % of VBIAS
l
73
75
77
%
VNTC(HOT)
NTC Hot Threshold
VNTC Falling, % of VBIAS
l
33
35
37
%
VNTC(HYS)
NTC Thresholds Hysteresis
% of VBIAS
VNTC(OPEN)
NTC Open Circuit Voltage
% of VBIAS
RNTC(OPEN)
NTC Open Circuit Input Resistance
TMR Threshold for CX Termination
l
5
l
45
50
%
55
300
%
kΩ
Voltage Monitoring and Open Drain Status Pins
VVM(TH)
VM Input Falling Threshold
VVM(HYS)
VM Input Hysteresis
VM Input Current
l
1.176
VVM = 1.2V
1.193
1.204
V
40
mV
±0.1
µA
IRST,CHRG,FLT(LKG) Open Drain Status Pins Leakage Current
VPIN = 60V
VRST,CHRG,FLT(VOL) Open Drain Status Pins Voltage Output Low
IPIN = 1mA
l
±1
µA
Input PowerPath Forward Regulation Voltage
VIID,CSP, 3V ≤ VCSP ≤ 60V
l
0.1
Input PowerPath Fast Reverse Turn-Off
Threshold Voltage
VIID,CSP, 3V ≤ VCSP ≤ 60V,
VIGATE = VCSP – 2.5V,
∆IIGATE/∆ VIID,CSP ≥ 100μA/mV
l
Input PowerPath Fast Forward Turn-On
Threshold Voltage
VIID,CSP, 3V ≤ VCSP ≤ 60V,
VIGATE = VIID – 1.5V,
∆IIGATE/∆ VIID,CSP ≥ 100μA/mV
l
Input Gate Turn-Off Current
VIID = VCSP, VIGATE = VCSP – 1.5V
–0.3
μA
Input Gate Turn-On Current
VCSP = VIID – 20mV,
VIGATE = VIID – 1.5V
0.3
μA
IIGATE(FASTOFF)
Input Gate Fast Turn-Off Current
VCSP = VIID + 0.1V,
VIGATE = VCSP – 5V
–0.5
mA
IIGATE(FASTON)
Input Gate Fast Turn-On Current
VCSP = VIID – 0.2V,
VIGATE = VIID – 1.5V
0.7
mA
VIGATE(ON)
Input Gate Clamp Voltage
IIGATE = 2µA, VIID = 12V to 60V,
VCSP = VIID – 0.5V, Measure
VIID – VIGATE
l
13
15
V
Input Gate Off Voltage
IIGATE = – 2μA, VIID = 3V to 59.5V,
VCSP = VIID + 0.5V, Measure
VCSP – VIGATE
l
0.45
0.7
V
0.4
V
8
20
mV
–90
–50
–20
mV
40
80
130
mV
Input PowerPath Control
40001f
4
LTC4000-1
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Battery PowerPath Control
Battery Discharge PowerPath Forward
Regulation Voltage
VBAT,CSN, 2.8V ≤ VBAT ≤ 60V
l
0.1
8
20
mV
Battery PowerPath Fast Reverse Turn-Off
Threshold Voltage
VBAT,CSN, 2.8V ≤ VBAT ≤ 60V, Not
Charging, VBGATE = VCSN – 2.5V,
∆IBGATE/∆VBAT,CSN ≥ 100μA/mV
l
–90
–50
–20
mV
Battery PowerPath Fast Forward Turn-On
Threshold Voltage
VBAT,CSN, 2.8V ≤ VCSN ≤ 60V,
VBGATE = VBAT – 1.5V,
∆IBGATE/∆ VBAT,CSN ≥ 100μA/mV
l
40
80
130
mV
Battery Gate Turn-Off Current
VBGATE = VCSN – 1.5V, VCSN ≥ VBAT,
VOFB < VOUT(INST_ON) and Charging
in Progress, or VCSN = VBAT and Not
Charging
–0.3
μA
Battery Gate Turn-On Current
VBGATE = VBAT – 1.5V, VCSN ≥ VBAT,
VOFB > VOUT(INST_ON) and Charging in
Progress, or VCSN = VBAT – 20mV
0.3
μA
IBGATE(FASTOFF)
Battery Gate Fast Turn-Off Current
VCSN = VBAT + 0.1V and Not
Charging, VBGATE = VCSN – 5V
–0.5
mA
IBGATE(FASTON)
Battery Gate Fast Turn-On Current
VCSN = VBAT – 0.2V,
VBGATE = VBAT – 1.5V
0.7
mA
VBGATE(ON)
Battery Gate Clamp Voltage
IBGATE = 2μA, VBAT = 12V to 60V,
VCSN = VBAT – 0.5V, Measure
VBAT – VBGATE
Battery Gate Off Voltage
IBGATE = – 2μA, VBAT = 2.8V to 59.5V, l
VCSN = VBAT + 0.5V and not Charging,
Measure VCSN – VBGATE
l
13
15
V
0.45
0.7
V
2.9
3.5
V
–10
BIAS Regulator Output and Control Pins
VBIAS
BIAS Output Voltage
No Load
ΔVBIAS
BIAS Output Voltage Load Regulation
IBIAS = – 0.5mA
–0.5
BIAS Output Short-Circuit Current
VBIAS = 0V
–20
mA
Transconductance of Error Amp
CC = 1V
0.5
mA/V
l
Open Loop DC Voltage Gain of Error Amp
CC = Open
IITH(PULL_UP)
Pull-Up Current on the ITH Pin
VITH = 0V, CC = 0V
IITH(PULL_DOWN)
Pull-Down Current on the ITH Pin
VITH = 0.4V, CC = Open
Open Loop DC Voltage Gain of ITH Driver
ITH = Open
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4000-1 is tested under conditions such that TJ ≈ TA.
The LTC4000E-1 is guaranteed to meet specifications from 0°C to 85°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC4000I-1 is
guaranteed over the full –40°C to 125°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
2.4
80
–6
l
0.5
–5
%
dB
–4
μA
1
mA
60
dB
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. The junction temperature (TJ, in °C) is
calculated from the ambient temperature (TA, in °C) and power dissipation
(PD, in Watts) according to the following formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
Note 3: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 4: These parameters are guaranteed by design and are not 100%
tested.
40001f
5
LTC4000-1
Typical Performance Characteristics
Input Quiescent Current and
Battery Quiescent Current Over
Temperature
1.0
Input Voltage Regulation Feedback,
Battery Float Voltage Feedback, Output
Voltage Regulation Feedback and VM
Falling Threshold Over Temperature
Battery Only Quiescent Current
Over Temperature
1.20
100
VIN = VBAT = 15V
VCSN = 15.5V
IIN
1.18
VBAT = 60V
10
1.16
PIN VOLTAGE (V)
1
IBAT (µA)
IIN/IBAT (mA)
IBAT
VBAT = 3V
0.1
1.015
1.010
–47.5
1.005
ICL (µA)
VOUT(INST_ON)
VIBMON (V)
PERCENT OF VBFB_REG (%)
Maximum Programmable Current
Limit Voltage Over Temperature
CL Pull-Up Current Over
Temperature
–50.0
75
0.995
0.990
60
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
–55.0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G04
40001 G06
CX Comparator Offset Voltage with
VIBMON Falling Over Temperature
Current Sense Offset Voltage Over
Common Mode Voltage Range
300
VMAX(IN,CLN) = VMAX(CSP, CSN) = 15V
200
100
VOS (µV)
VOS(CSP, CSN)
0
VOS(IN, CSN)
VOS(CSP, CSN)
0
VOS(IN, CSN)
–100
–200
–200
–300
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
–300
40001 G07
VCX,IBMON (mV)
200
VOS (µV)
0.985
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G05
Current Sense Offset Voltage
Over Temperature
–100
1.000
–52.5
VLOBAT
65
100
40001 G03
–45.0
80
300
VIFB_REG
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VRECHRG(RISE)
90
70
1.06
40001 G02
100
85
1.08
1.00
0.001
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Battery Thresholds: Rising Recharge,
Instant-On Regulation and Falling Low
Battery As a Percentage of Battery
Float Feedback Over Temperature
VBFB_REG
1.00
1.02
40001 G01
95
1.12
1.04
0.01
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VOFB_REG
1.14
VBAT = 15V
0.1
VVM(TH)
0 3
10
20
30
40
50
VMAX(IN, CLN) /VMAX(CSP, CSN) (V)
60
40001 G08
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G09
40001f
6
LTC4000-1
Typical Performance Characteristics
Charge Termination Time with 0.1µF
Timer Capacitor Over Temperature
NTC Thresholds Over
Temperature
3.5
80
VNTC(COLD)
75
3.3
14
12
2.9
2.7
65
60
55
VNTC(OPEN)
50
45
VNTC(HOT)
40
2.5
VIID,CSP / VBAT,CSN (mV)
PERCENT OF VBIAS (%)
70
3.1
TT (h)
PowerPath Forward Voltage
Regulation Over Temperature
15.0
VIID = VBAT = 15V
PowerPath Turn-Off Gate Voltage
Over Temperature
600
VIID = VBAT = 15V
0
–30
VCSP,IGATE/VCSN,BGATE (mV)
30
VCSP = VCSN = 15V
550
14.5
VIGATE (ON)/VBGATE(ON) (V)
14.0
13.5
13.0
12.5
12.0
500
450
400
350
300
–60
11.5
250
–90
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
11.0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
200
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G13
BIAS Voltage at 0.5mA Load Over
Temperature
ITH Pull-Down Current Over
Temperature
3.2
1.5
1.4
3.1
VIN = 60V
VIN = 15V
2.9
2.8
VIN = 3V
2.7
2.5
VITH = 0.4V
1.3
IITH(PULL-DOWN) (mA)
3.0
ITH Pull-Down Current
vs VITH
2.0
1.2
1.1
1.0
0.9
0.8
0.7
2.6
40001 G15
40001 G14
IITH(PULL-DOWN) (mA)
VIID,CSP /VBAT,CSN (mV)
40001 G12
PowerPath Turn-On Gate Clamp
Voltage Over Temperature
90
VBIAS (V)
4
40001 G11
PowerPath Fast Off, Fast On
and Forward Regulation Over
Temperature
60
VIID = VBAT = 60V
6
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
30
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G10
120
VIID = VBAT = 3V
8
2
35
2.3
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VIID = VBAT = 15V
10
1.5
1.0
0.5
0.6
2.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G16
0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
40001 G17
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VITH (V)
1
40001 G18
40001f
7
LTC4000-1
Pin Functions
(QFN/SSOP)
VM (Pin 1/Pin 25): Voltage Monitor Input. High impedance
input to an accurate comparator with a 1.193V threshold
(typical). This pin controls the state of the RST output
pin. Connect a resistor divider (RVM1, RVM2) between the
monitored voltage and GND, with the center tap point connected to this pin. The falling threshold of the monitored
voltage is calculated as follows:
VVM _ RST
R
+R
= VM1 VM2 • 1.193V
RVM2
where RVM2 is the bottom resistor between the VM pin
and GND. Tie to the BIAS pin if voltage monitoring function is not used.
RST (Pin 2/Pin 26): High Voltage Open Drain Reset Output.
When the voltage at the VM pin is below 1.193V, this status
pin is pulled low. When driven low, this pin can disable
a DC/DC converter when connected to the converter’s
enable pin. This pin can also drive an LED to provide a
visual status indicator of a monitored voltage. Short this
pin to GND when not used.
IIMON (Pin 3/Pin 27): Input Current Monitor. The voltage
on this pin is 20 times (typical) the sense voltage (VIN,CLN)
across the input current sense resistor(RIS), therefore
providing a voltage proportional to the input current.
Connect an appropriate capacitor to this pin to obtain a
voltage representation of the time-average input current.
Leave this pin open when input current monitoring function is not needed.
IFB (Pin 4/Pin 28): Input Voltage Feedback Pin. This pin is
a high impedance input pin used to sense the input voltage
level. In regulation, the input voltage loop sets the voltage
on this feedback pin to 1.000V. When the input feedback
voltage drops below 1.000V, the ITH pin is pulled down
to reduce the load on the input source. Connect this pin
to the center node of a resistor divider between the IN
pin and GND to set the input voltage regulation level. This
regulation level can then be obtained as follows:
R

VIN _ REG =  OFB1 + 1 • 1.000V
 ROFB2 
If the input voltage regulation feature is not used, connect
the IFB pin to the BIAS pin.
ENC (Pin 5/Pin 1): Enable Charging Pin. High impedance
digital input pin. Pull this pin above 1.5V to enable charging and below 0.5V to disable charging. Leaving this pin
open causes the internal 2µA pull-up current to pull the
pin to 2.5V (typical).
IBMON (Pin 6/Pin 2): Battery Charge Current Monitor. The
voltage on this pin is 20 times (typical) the sense voltage
(VCSP,CSN) across the battery current sense resistor (RCS),
therefore providing a voltage proportional to the battery
charge current. Connect an appropriate capacitor to this
pin to obtain a voltage representation of the time-average
battery charge current. Short this pin to GND to disable
charge current limit feature.
CX (Pin 7/Pin 3): Charge Current Termination Programming. Connect the charge current termination programming resistor (RCX) to this pin. This pin is a high
impedance input to a comparator and sources 5μA of
current. When the voltage on this pin is greater than the
charge current monitor voltage (VIBMON), the CHRG pin
40001f
8
LTC4000-1
Pin Functions
(QFN/SSOP)
turns high impedance indicating that the CX threshold is
reached. When this occurs, the charge current is immediately terminated if the TMR pin is shorted to the BIAS
pin, otherwise charging continues until the charge termination timer expires. The charge current termination value
is determined using the following formula:
IC / X =
(0.25µA • R CX ) − 0.5mV
R CS
Where RCS is the sense resistor connected to the CSP
and the CSN pins. Note that if RCX = RCL ≤ 19.1kΩ, where
RCL is the charge current programming resistor, then the
charge current termination value is one tenth the full charge
current, more familiarly known as C/10. Short this pin to
GND to disable CX termination.
CL (Pin 8/Pin 4): Charge Current Limit Programming. Connect the charge current programming resistor (RCL) to this
pin. This pin sources 50µA of current. The regulation loop
compares the voltage on this pin with the charge current
monitor voltage (VIBMON), and drives the ITH pin accordingly to ensure that the programmed charge current limit
is not exceeded. The charge current limit is determined
using the following formula:
R 
ICLIM = 2.5µA •  CL 
 RCS 
Where RCS is the sense resistor connected to the CSP
and the CSN pins. Leave the pin open for the maximum
charge current limit of 50mV/RCS.
TMR (Pin 9/Pin 5): Charge Timer. Attach 1nF of external
capacitance (CTMR) to GND for each 104 seconds of charge
termination time and 26 seconds of bad battery indicator
time. Short to GND to prevent bad battery indicator time
and charge termination time from expiring – allowing a
continuous trickle charge and top off float voltage regulation charge. Short to BIAS to disable bad battery detect
and enable C/X charging termination.
GND (Pins 10, 28, 29/Pins 6, 24): Device Ground Pins.
Connect the ground pins to a suitable PCB copper ground
plane for proper electrical operation. The QFN package
exposed pad must be soldered to PCB ground for rated
thermal performance.
FLT, CHRG (Pin 11, Pin 12/Pin 7, Pin 8): Charge Status
Indicator Pins. These pins are high voltage open drain pull
down pins. The FLT pin pulls down when there is an under
or over temperature condition during charging or when
the voltage on the BFB pin stays below the low battery
threshold during charging for a period longer than the bad
battery indicator time. The CHRG pin pulls down during
a charging cycle. Please refer to the application information section for details on specific modes indicated by the
combination of the states of these two pins. Pull up each
of these pins with an LED in series with a resistor to a
voltage source to provide a visual status indicator. Short
these pins to GND when not used.
BIAS (Pin 13/Pin 9): 2.9V Regulator Output. Connect a
capacitor of at least 470nF to bypass this 2.9V regulated
voltage output. Use this pin to bias the resistor divider to
set up the voltage at the NTC pin.
40001f
9
LTC4000-1
Pin Functions
(QFN/SSOP)
NTC (Pin 14/Pin 10): Thermistor Input. Connect a thermistor from NTC to GND, and a corresponding resistor
from BIAS to NTC. The voltage level on this pin determines
if the battery temperature is safe for charging. The charge
current and charge timer are suspended if the thermistor
indicates a temperature that is unsafe for charging. Once the
temperature returns to the safe region, charging resumes.
Leave the pin open or connected to a capacitor to disable
the temperature qualified charging function.
FBG (Pin 15/Pin 11): Feedback Ground Pin. This is the
ground return pin for the resistor dividers connected to
the BFB and OFB pins. As soon as the voltage at IN is valid
(>3V typical), this pin has a 100Ω resistance to GND. When
the voltage at IN is not valid, this pin is disconnected from
GND to ensure that the resistor dividers connected to the
BFB and OFB pins do not continue to drain the battery
when the battery is the only available power source.
BFB (Pin 16/Pin 12): Battery Feedback Voltage Pin. This
pin is a high impedance input pin used to sense the battery
voltage level. In regulation, the battery float voltage loop
sets the voltage on this pin to 1.136V (typical). Connect
this pin to the center node of a resistor divider between
the BAT pin and the FBG pin to set the battery float voltage.
The battery float voltage can then be obtained as follows:
VFLOAT =
RBFB2 + RBFB1
• 1.136V
RBFB2
BAT (Pin 17/Pin 13): Battery Pack Connection. Connect
the battery to this pin. This pin is the anode of the battery
ideal diode driver (the cathode is the CSN pin).
BGATE (Pin 18/Pin 14): External Battery PMOS Gate Drive
Output. When not charging, the BGATE pin drives the
external PMOS to behave as an ideal diode from the BAT
pin (anode) to the CSN pin (cathode). This allows efficient
delivery of any required additional power from the battery
to the downstream system connected to the CSN pin.
When charging a heavily discharged battery, the BGATE
pin is regulated to set the output feedback voltage (OFB
pin) to 86% of the battery float voltage (0.974V typical).
This allows the instant-on feature, providing an immediate
valid voltage level at the output when the LTC4000-1 is
charging a heavily discharged battery. Once the voltage
on the OFB pin is above the 0.974V typical value, then the
BGATE pin is driven low to ensure an efficient charging
path from the CSN pin to the BAT pin.
CSN (Pin 19/Pin 15): Charge Current Sense Negative Input
and Battery Ideal Diode Cathode. Connect a sense resistor
between this pin and the CSP pin. The LTC4000-1 senses
the voltage across this sense resistor and regulates it to a
voltage equal to 1/20th (typical) of the voltage set at the
CL pin. The maximum regulated sense voltage is 50mV.
The CSN pin is also the cathode input of the battery ideal
diode driver (the anode input is the BAT pin). Tie this pin
to the CSP pin if no charge current limit is desired. Refer to
the Applications Information section for complete details.
CSP (Pin 20/Pin 16): Charge Current Sense Positive Input
and Input Ideal Diode Cathode. Connect a sense resistor between this pin and the CSN pin for charge current
sensing and regulation. This input should be tied to CSN
to disable the charge current regulation function. This
pin is also the cathode of the input ideal diode driver (the
anode is the IID pin).
40001f
10
LTC4000-1
Pin Functions
(QFN/SSOP)
OFB (Pin 21/Pin 17): Output Feedback Voltage Pin. This
pin is a high impedance input pin used to sense the output
voltage level. In regulation, the output voltage loop sets the
voltage on this feedback pin to 1.193V. Connect this pin
to the center node of a resistor divider between the CSP
pin and the FBG pin to set the output voltage when battery
charging is terminated and all the output load current is
provided from the input. The output voltage can then be
obtained as follows:
VOUT
+ ROFB1
R
= OFB2
• 1.193V
ROFB2
When charging a heavily discharged battery (such that VOFB
< VOUT(INST_ON)), the battery PowerPath PMOS connected
to BGATE is regulated to set the voltage on this feedback
pin to 0.974V (approximately 86% of the battery float
voltage). The instant-on output voltage is then as follows:
VOUT(INST _ ON) =
ROFB2 + ROFB1
• 0.974V
ROFB2
IGATE (Pin 22/Pin 18): Input PMOS Gate Drive Output. The
IGATE pin drives the external PMOS to behave as an ideal
diode from the IID pin (anode) to the CSP pin (cathode).
IID (Pin 23/Pin 19): Input Ideal Diode Anode. This pin is
the anode of the input ideal diode driver (the cathode is
the CSP pin).
ITH (Pin 24/Pin 20): High Impedance Control Voltage Pin.
When any of the regulation loops (input voltage, charge
current, battery float voltage or the output voltage) indicate
that its limit is reached, the ITH pin will sink current (up to
1mA) to regulate that particular loop at the limit. In many
applications, this ITH pin is connected to the control/
compensation node of a DC/DC converter. Without any
external pull-up, the operating voltage range on this pin
is GND to 2.5V. With an external pull-up, the voltage on
this pin can be pulled up to 6V. Note that the impedance
connected to this pin affects the overall loop gain. For
details, refer to the Applications Information section.
CC (Pin 25/Pin 21): Converter Compensation Pin. Connect
an R-C network from this pin to the ITH pin to provide a
suitable loop compensation for the converter used. Refer
to the Applications Information section for discussion and
procedure on choosing an appropriate R-C network for a
particular DC/DC converter.
CLN (Pin 26/Pin 22): Input Current Sense Negative Input.
Connect a sense resistor between this pin and the IN pin. The
LTC4000-1 senses the voltage across this sense resistor
and sets the voltage on the IIMON pin equal to 20 times
this voltage. Tie this pin to the IN pin if the input current
monitoring feature is not used. Refer to the Applications
Information section for complete details.
IN (Pin 27/Pin 23): Input Supply Voltage: 3V to 60V.
Supplies power to the internal circuitry and the BIAS pin.
Connect the power source to the downstream system and
the battery charger to this pin. This pin is also the positive
sense pin for the input current monitor. Connect a sense
resistor between this pin and the CLN pin. Tie this pin to
CLN if the input current monitoring feature is not used. A
local 0.1µF bypass capacitor to ground is recommended
on this pin.
40001f
11
LTC4000-1
Block Diagram
RIS
CIN
RVM1
OUT
DC/DC CONVERTER
CCLN
RC
IN
CLN
RST
VM
–
CIBMON
CC
ITH
CC
IID
IBMON
IGATE
CSP
CP1
RVM2
1.193V
8mV
+
+
–
–
+
A8
gm = 0.33m
A9
gm = 0.33m
60k
A1
+–
INPUT IDEAL
DIODE DRIVER
8mV
gm
A11
RIFB1
A4
IFB
1V
RIFB2
gm–
BIAS
A5
–g
m
+
–
ROFB1
5µA/
50µA
1V
gm+
CL
–
A7
+
–
IN
LDO,
BG,
REF
CBIAS
BATTERY IDEAL DIODE
AND INSTANT-ON DRIVER
ITH AND CC DRIVER
A10
BGATE
ENABLE
CHARGING
0.974V
60k
RCS
CSN
LINEAR
GATE
DRIVER
AND
VOLTAGE
CLAMP
A2
IIMON
CIIMON
A6
+
–
REF
gm
RCL
OFB
gm
BIAS
OFB
1.193V
CP6
BFB
–
0.771V
ROFB2
1.136V
+
BFB
+
CP4
TOO COLD
–
–
RBFB2
1.109V
FBG
NTC FAULT
+
RBFB1
+
CP5
NTC
SYSTEM
LOAD
CL
CIID
–
+
IN
LOGIC
CP3
–
CP2
BAT
–
BIAS
TOO HOT
+
CBAT
5µA
10mV
–+
BIAS
+
–
RNTC
CX
BATTERY PACK
2µA
TMR
CTMR
RCX
OSCILLATOR
GND
ENC
CHRG
FLT
40001 BD
R3
Figure 1. LTC4000-1 Functional Block Diagram
40001f
12
LTC4000-1
Operation
Overview
The LTC4000-1 is designed to simplify the conversion of
any externally compensated DC/DC converter into a high
performance battery charger with PowerPath control. It
only requires the DC/DC converter to have a control or
external-compensation pin (usually named VC or ITH)
whose voltage level varies in a positive monotonic way
with its output. The output variable can be either output
voltage or output current. For the following discussion,
refer to the Block Diagram in Figure 1.
The LTC4000-1 includes four different regulation loops:
input voltage, charge current, battery float voltage and
output voltage (A4-A7). Whichever loop requires the lowest voltage on the ITH pin for its regulation controls the
external DC/DC converter.
The input voltage regulation loop ensures that the input
voltage level does not drop below the programmed level.
The charge current regulation loop ensures that the programmed battery charge current limit (using a resistor
at CL) is not exceeded. The float voltage regulation loop
ensures that the programmed battery stack voltage (using a resistor divider from BAT to FBG via BFB) is not
exceeded. The output voltage regulation loop ensures that
the programmed system output voltage (using a resistor
divider from CSP to FBG via OFB) is not exceeded. The
LTC4000-1 also provides monitoring pins for the input
current and charge current at the IIMON and IBMON pins
respectively.
The LTC4000-1 features an ideal diode controller at the
input from the IID pin to the CSP pin and a PowerPath
controller at the output from the BAT pin to the CSN pin.
The output PowerPath controller behaves as an ideal
diode controller when not charging. When charging, the
output PowerPath controller has two modes of operation.
If VOFB is greater than VOUT(INST_ON), BGATE is driven low.
When VOFB is less than VOUT(INST_ON), a linear regulator
implements the instant-on feature. This feature provides
regulation of the BGATE pin so that a valid voltage level is
immediately available at the output when the LTC4000-1 is
charging an over-discharged, dead or short faulted battery.
The state of the ENC pin determines whether charging is
enabled. When ENC is grounded, charging is disabled and
the battery float voltage loop is disabled. Charging is enabled
when the ENC pin is left floating or pulled high (≥1.5V)
The LTC4000-1 offers several user configurable battery
charge termination schemes. The TMR pin can be configured for either C/X termination, charge timer termination or
no termination. After a particular charge cycle terminates,
the LTC4000-1 features an automatic recharge cycle if the
battery voltage drops below 97.6% of the programmed
float voltage.
Trickle charge mode drops the charge current to one
tenth of the normal charge current (programmed using a
resistor from the CL pin to GND) when charging into an
over discharged or dead battery. When trickle charging,
a capacitor on the TMR pin can be used to program a
time out period. When this bad battery timer expires and
the battery voltage fails to charge above the low battery
threshold (VLOBAT), the LTC4000-1 will terminate charging
and indicate a bad battery condition through the status
pins (FLT and CHRG).
The LTC4000-1 also includes an NTC pin, which provides
temperature qualified charging when connected to an NTC
thermistor thermally coupled to the battery pack. To enable
this feature, connect the thermistor between the NTC and
the GND pins, and a corresponding resistor from the BIAS
pin to the NTC pin. The LTC4000-1 also provides a charging status indicator through the FLT and the CHRG pins.
Aside from biasing the thermistor-resistor network, the
BIAS pin can also be used for a convenient pull up voltage.
This pin is the output of a low dropout voltage regulator
that is capable of providing up to 0.5mA of current. The
regulated voltage on the BIAS pin is available as soon as
the IN pin is within its operating range (≥3V).
Input Ideal Diode
The input ideal diode feature provides low loss conduction
and reverse blocking from the IID pin to the CSP pin. This
reverse blocking prevents reverse current from the output
(CSP pin) to the input (IID pin) which causes unnecessary drain on the battery and in some cases may result
in unexpected DC/DC converter behavior.
The ideal diode behavior is achieved by controlling an
external PMOS connected to the IID pin (drain) and the
40001f
13
LTC4000-1
Operation
CSP pin (source). The controller (A1) regulates the external
PMOS by driving the gate of the PMOS device such that the
voltage drop across IID and CSP is 8mV (typical). When
the external PMOS ability to deliver a particular current
with an 8mV drop across its source and drain is exceeded,
the voltage at the gate clamps at VIGATE(ON) and the PMOS
behaves like a fixed value resistor (RDS(ON)).
Input Voltage Regulation
One of the loops driving the ITH and CC pins is the input
voltage regulation loop (Figure 2). This loop prevents the
input voltage from dropping below the programmed level.
RIS
IN
CCLN
(OPTIONAL)
IN
CLN
LTC4000-1
CC
RIFB1
RIFB2
IFB
1V
–
+
A4
CC
–
+
ITH
Once the battery voltage is above VLOBAT, the charge current
regulation loop begins charging in full power constantcurrent mode. In this case, the programmed full charge
current is set with a resistor on the CL pin.
Depending on available input power and external load
conditions, the battery charger may not be able to charge
at the full programmed rate. The external load is always
prioritized over the battery charge current. The input voltage programming is always observed, and only additional
power is available to charge the battery. When system
loads are light, battery charge current is maximized.
DC/DC INPUT
CIN
loop to set the battery charge current to 10% of the programmed full-scale value. If the TMR pin is connected
to a capacitor or open, the bad battery detection timer is
enabled. When this bad battery detection timer expires
and the battery voltage is still below VLOBAT, the battery
charger automatically terminates and indicates, via the
FLT and CHRG pins, that the battery was unresponsive
to charge current.
RC
TO DC/DC
40001 FO2
Figure 2. Input Voltage Regulation Loop
When the input source is high impedance, the input voltage drops as the load current increases. In that case there
exists a voltage level at which the available power from
the input is maximum. For example, solar panels often
specify VMP, corresponding to the panel voltage at which
maximum power is achieved. With the LTC4000-1 input
voltage regulation, this maximum power voltage level can
be programmed at the IFB pin. The input voltage regulation
loop regulates ITH to ensure that the input voltage level
does not drop below this programmed level.
Battery Charger Overview
In addition to the input voltage regulation loop, the
LTC4000-1 regulates charge current, battery voltage and
output voltage.
When a battery charge cycle begins, the battery charger
first determines if the battery is over-discharged. If the
battery feedback voltage is below VLOBAT, an automatic
trickle charge feature uses the charge current regulation
Once the float voltage is achieved, the battery float voltage regulation loop takes over from the charge current
regulation loop and initiates constant voltage charging. In
constant voltage charging, charge current slowly declines.
Charge termination can be configured with the TMR pin
in several ways. If the TMR pin is tied to the BIAS pin,
C/X termination is selected. In this case, charging is
terminated when constant voltage charging reduces the
charge current to the C/X level programmed at the CX
pin. Connecting a capacitor to the TMR pin selects the
charge timer termination and a charge termination timer
is started at the beginning of constant voltage charging.
Charging terminates when the termination timer expires.
When continuous charging at the float voltage is desired,
tie the TMR pin to GND to disable termination.
Upon charge termination, the PMOS connected to BGATE
behaves as an ideal diode from BAT to CSN. The diode
function prevents charge current but provides current
to the system load as needed. If the system load can be
completely supplied from the input, the battery PMOS turns
off. While terminated, if the input voltage loop is not in
regulation, the output voltage regulation loop takes over to
ensure that the output voltage at CSP remains in control.
40001f
14
LTC4000-1
Operation
The output voltage regulation loop regulates the voltage
at the CSP pin such that the output feedback voltage at
the OFB pin is 1.193V.
If the system load requires more power than is available
from the input, the battery ideal diode controller provides
supplemental power from the battery. When the battery
voltage discharges below 97.1% of the float voltage
(VBFB < VRECHRG(FALL)), the automatic recharge feature
initiates a new charge cycle.
Charge Current Regulation
The first loop involved in a normal charging cycle is the
charge current regulation loop (Figure 3). This loop drives
the ITH and CC pins. This loop ensures that the charge
current sensed through the charge current sense resistor
(RCS) does not exceed the programmed full charge current.
BAT PMOS
CIBMON
(OPTIONAL)
CSP
CSN
+
–
A9
gm = 0.33m
60k
BIAS
RCL
LTC4000-1
BFB
+
–
FBG
1.136V
A6
CC
CC
–
+
ITH
RC
TO DC/DC
40001 FO4
Figure 4. Battery Float Voltage Regulation Loop with FBG
Output Voltage Regulation
When charging terminates and the system load is completely supplied from the input, the PMOS connected to
BGATE is turned off. In this scenario, the output voltage
regulation loop takes over from the battery float voltage
regulation loop (Figure 5). The output voltage regulation
loop regulates the voltage at the CSP pin such that the
output feedback voltage at the OFB pin is 1.193V.
ROFB1
CCSP
IBMON
RBFB2
BAT
TO SYSTEM
RIS
CSP
RBFB1
50µA AT NORMAL 1V
5µA AT TRICKLE
ROFB2
LTC4000-1
CSP
LTC4000-1
OFB
+
–
FBG
1.193V
A7
CC
CC
–
+
ITH
RC
TO DC/DC
CC
+
–
–
A5
CC
–
+
40001 FO5
RC
ITH
TO DC/DC
Figure 5. Output Voltage Regulation Loop with FBG
Battery Instant-On and Ideal Diode
CL
40001 FO3
Figure 3. Charge Current Regulation Loop
Battery Voltage Regulation
Once the float voltage is reached, the battery voltage regulation loop takes over from the charge current regulation
loop (Figure 4).
The float voltage level is programmed using the feedback
resistor divider between the BAT pin and the FBG pin with
the center node connected to the BFB pin. Note that the
ground return of the resistor divider is connected to the
FBG pin. The FBG pin disconnects the resistor divider
load when VIN < 3V to ensure that the float voltage resistor divider does not consume battery current when the
battery is the only available power source. For VIN ≥ 3V,
the typical resistance from the FBG pin to GND is 100Ω.
The LTC4000-1 controls the external PMOS connected to
the BGATE pin with a controller similar to the input ideal
diode controller driving the IGATE pin. When not charging, the PMOS behaves as an ideal diode between the BAT
(anode) and the CSN (cathode) pins. The controller (A2)
regulates the external PMOS to achieve low loss conduction by driving the gate of the PMOS device such that the
voltage drop from the BAT pin to the CSN pin is 8mV.
When the ability to deliver a particular current with an 8mV
drop across the PMOS source and drain is exceeded, the
voltage at the gate clamps at VBGATE(ON) and the PMOS
behaves like a fixed value resistor (RDS(ON)).
The ideal diode behavior allows the battery to provide current to the load when the input supply is in current limit
or the DC/DC converter is slow to react to an immediate
load increase at the output. In addition to the ideal diode
40001f
15
LTC4000-1
Operation
behavior, BGATE also allows current to flow from the CSN
pin to the BAT pin during charging.
There are two regions of operation when current is
flowing from the CSN pin to the BAT pin. The first is
when charging into a battery whose voltage is below
the instant-on threshold (VOFB < VOUT(INST_ON)). In this
region of operation, the controller regulates the voltage
at the CSP pin to be approximately 86% of the final float
voltage level (VOUT(INST_ON)). This feature provides a CSP
voltage significantly higher than the battery voltage when
charging into a heavily discharged battery. This instant-on
feature allows the LTC4000-1 to provide sufficient voltage
at the output (CSP pin), independent of the battery voltage.
The second region of operation is when the battery feedback
voltage is greater than or equal to the instant-on threshold
(VOUT(INST_ON)). In this region, the BGATE pin is driven
low and clamped at VBGATE(ON) to allow the PMOS to turn
completely on, reducing any power dissipation due to the
charge current.
Battery Temperature Qualified Charging
The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the
battery pack. The comparators CP3 and CP4 implement
the temperature detection as shown in the Block Diagram
in Figure 1. The rising threshold of CP4 is set at 75% of
VBIAS (cold threshold) and the falling threshold of CP3 is
set at 35% of VBIAS (hot threshold). When the voltage at
the NTC pin is above 75% of VBIAS or below 35% of VBIAS
then the LTC4000-1 pauses any charge cycle in progress.
When the voltage at the NTC pin returns to the range of
40% to 70% of VBIAS, charging resumes.
When charging is paused, the external charging PMOS
turns off and charge current drops to zero. If the LTC4000-1
is charging in the constant voltage mode and the charge
termination timer is enabled, the timer pauses until the
thermistor indicates a return to a valid temperature. If the
battery charger is in the trickle charge mode and the bad
battery detection timer is enabled, the bad battery timer
pauses until the thermistor indicates a return to a valid
temperature.
Input UVLO and Voltage Monitoring
The regulated voltage on the BIAS pin is available as soon
as VIN ≥ 3V. When VIN ≥ 3V, the FBG pin is pulled low to
GND with a typical resistance of 100Ω and the rest of the
chip functionality is enabled.
When the IN pin is high impedance and a battery is connected to the BAT pin, the BGATE pin is pulled down with
a 2μA (typical) current source to hold the battery PMOS
gate voltage at VBGATE(ON) below VBAT. This allows the
battery to power the output. The total quiescent current
consumed by LTC4000-1 from the battery when IN is not
valid is typically ≤ 10µA.
Besides the internal input UVLO, the LTC4000-1 also provides voltage monitoring through the VM pin. The RST pin
is pulled low when the voltage on the VM pin falls below
1.193V (typical). On the other hand, when the voltage on
the VM pin rises above 1.233V (typical), the RST pin is
high impedance.
One common use of this voltage monitoring feature is to
ensure that the converter is turned off when the voltage
at the input is below a certain level. In this case, connect
the RST pin to the DC/DC converter chip select or enable
pin (see Figure 6).
RIS
IN
RVM1
IN
VM
IN
CLN
–
DC/DC
CONVERTER
EN
RST
CP1
RVM2
1.193V
+
LTC4000-1
40001 FO6
Figure 6. Input Voltage Monitoring with RST Connected to
the EN Pin of the DC/DC Converter
40001f
16
LTC4000-1
Applications Information
Input Ideal Diode PMOS Selection
The input external PMOS is selected based on the expected
maximum current, power dissipation and reverse voltage drop. The PMOS must be able to withstand a gate to
source voltage greater than VIGATE(ON) (15V maximum) or
the maximum regulated voltage at the IID pin, whichever
is less. A few appropriate external PMOS for a number of
different requirements are shown at Table 1.
The voltage on the IIMON pin can be filtered further by
putting a capacitor on the pin (CIIMON).
Charge Current Limit Setting and Monitoring
The regulated full charge current is set according to the
following formula:
Table 1. PMOS
RDS(ON) AT
VGS = 10V
(Ω)
MAX ID
(A)
SiA923EDJ
0.054
4.5
–20
Vishay
Si9407BDY
0.120
4.7
–60
Vishay
Si4401BDY
0.014
10.5
–40
Vishay
Si4435DDY
0.024
11.4
–30
Vishay
SUD19P06-60
0.060
18.3
–60
Vishay
Si7135DP
0.004
60
–30
Vishay
PART NUMBER
is strongly recommended. Where the highest accuracy is
important, pick the value of CCLN such that the AC content
is less than or equal to 50% of the average voltage across
the sense resistor.
MAX VDS
(V)
MANUFACTURER
Note that in general the larger the capacitance seen on
the IGATE pin, the slower the response of the ideal diode
driver. The fast turn off and turn on current is limited to
–0.5mA and 0.7mA typical respectively (IIGATE(FASTOFF) and
IIGATE(FASTON)). If the driver can not react fast enough to a
sudden increase in load current, most of the extra current
is delivered through the body diode of the external PMOS.
This increases the power dissipation momentarily. It is
important to ensure that the PMOS is able to withstand
this momentary increase in power dissipation.
Input Current Monitoring
The input current through the sense resistor is available
for monitoring through the IIMON pin. The voltage on
the IIMON pin varies with the current through the sense
resistor as follows:
VIIMON = 20 • IRIS • RIS = 20 • ( VIN – VCLN )
If the input current is noisy, add a filter capacitor to the
CLN pin to reduce the AC content. For example, when using a buck DC/DC converter, the use of a CCLN capacitor
RCS =
VCL
20 • ICLIM
where VCL is the voltage on the CL pin. The CL pin is
internally pulled up with an accurate current source of
50µA. Therefore, an equivalent formula to obtain the
charge current limit is:
RCL =
ICLIM • RCS
R
⇒ ICLIM = CL • 2.5µA
2.5µA
RCS
The charge current through the sense resistor is available
for monitoring through the IBMON pin. The voltage on
the IBMON pin varies with the current through the sense
resistor as follows:
VIBMON = 20 • IRCS • RCS = 20 • ( VCSP – VCSN )
The regulation voltage level at the IBMON pin is clamped
at 1V with an accurate internal reference. At 1V on the
IBMON pin, the charge current limit is regulated to the
following value:
ICLIM(MAX)(A) =
0.050V
RCS (Ω)
When this maximum charge current limit is desired, leave
the CL pin open or set it to a voltage >1.05V such that
amplifier A5 can regulate the IBMON pin voltage accurately
to the internal reference of 1V.
When the output current waveform of the DC/DC converter
or the system load current is noisy, it is recommended that
40001f
17
LTC4000-1
Applications Information
a capacitor is connected to the CSP pin (CCSP). This is to
reduce the AC content of the current through the sense
resistor (RCS). Where the highest accuracy is important,
pick the value of CCSP such that the AC content is less
than or equal to 50% of the average voltage across the
sense resistor. Similar to the IIMON pin, the voltage on the
IBMON pin is filtered further by putting a capacitor on the
pin (CIBMON). This filter capacitor should not be arbitrarily
large as it will slow down the overall compensated charge
current regulation loop. For details on the loop compensation, refer to the Compensation section.
Battery Float Voltage Programming
When the value of RBFB1 is much larger than 100Ω, the final
float voltage is determined using the following formula:
V

RBFB1 =  FLOAT – 1 RBFB2
 1.136V 
When higher accuracy is important, a slightly more accurate final float voltage can be determined using the
following formula:

R
 R
+R
VFLOAT =  BFB1 BFB2 •1.136V  –  BFB1 • VFBG 
RBFB2


  RBFB2
where VFBG is the voltage at the FBG pin during float
voltage regulation, which accounts for all the current
from all resistor dividers that are connected to this pin
(RFBG = 100Ω typical).
Low Battery Trickle Charge Programming and Bad
Battery Detection
When charging into an over-discharged or dead battery
(VBFB < VLOBAT), the pull-up current at the CL pin is reduced
to 10% of the normal pull-up current. Therefore, the trickle
charge current is set using the following formula:
RCL =
ICLIM(TRKL) • RCS
0.25µA
⇒ ICLIM(TRKL) = 0.25µA •
RCL
RCS
Therefore, when 50µA•RCL is less than 1V, the following
relation is true:
ICLIM(TRKL) =
ICLIM
10
Once the battery voltage rises above the low battery voltage
threshold, the charge current level rises from the trickle
charge current level to the full charge current level.
The LTC4000-1 also features bad battery detection. This
detection is disabled if the TMR pin is grounded or tied
to BIAS. However, when a capacitor is connected to the
TMR pin, a bad battery detection timer is started as soon
as trickle charging starts. If at the end of the bad battery
detection time the battery voltage is still lower than the
low battery threshold, charging is terminated and the part
indicates a bad battery condition by pulling the FLT pin low
and leaving the CHRG pin high impedance.
The bad battery detection time can be programmed according to the following formula:
CTMR (nF) = tBADBAT (h) • 138.5
Note that once a bad battery condition is detected, the
condition is latched. In order to re-enable charging, remove the battery and connect a new battery whose voltage
causes BFB to rise above the recharge battery threshold
(VRECHRG(RISE)). Alternatively toggle the ENC pin or remove
and reapply power to IN.
C/X Detection, Charge Termination and Automatic
Recharge
Once the constant voltage charging is reached, there are
two ways in which charging can terminate. If the TMR pin
is tied to BIAS, the battery charger terminates as soon as
the charge current drops to the level programmed by the
CX pin. The C/X current termination level is programmed
according to the following formula:
RCX =
IC/ X • RCS
(0.25µA • RCX ) − 0.5mV
+ 0.5mV ⇒ IC/X =
0.25µA
RCS
40001f
18
LTC4000-1
Applications Information
where RCS is the charge current sense resistor connected
between the CSP and the CSN pins.
When the voltage at BFB is higher than the recharge
threshold (97.6% of float), the C/X comparator is enabled.
In order to ensure proper C/X termination coming out of
a paused charging condition, connect a capacitor on the
CX pin according to the following formula:
CCX = 100CBGATE
where CBGATE is the total capacitance connected to the
BGATE pin.
For example, a typical capacitance of 1nF requires a capacitor greater than 100nF connected to the CX pin to ensure
proper C/X termination behavior.
If a capacitor is connected to the TMR pin, as soon as the
constant voltage charging is achieved, a charge termination timer is started. When the charge termination timer
expires, the charge cycle terminates. The total charge
termination time can be programmed according to the
following formula:
CTMR (nF) = t TERMINATE (h) • 34.6
If the TMR pin is grounded, charging never terminates and
the battery voltage is held at the float voltage. Note that
regardless of which termination behavior is selected, the
CHRG and FLT pins will both assume a high impedance
state as soon as the charge current falls below the programmed C/X level.
As in the battery float voltage calculation, when higher
accuracy is important, a slightly more accurate output is
determined using the following formula:
R
 R

+R
VOUT =  OFB1 OFB2 • 1.193V  –  OFB1 • VFBG 
ROFB2

  ROFB2

where VFBG is the voltage at the FBG pin during output
voltage regulation, which accounts for all the current from
all resistor dividers that are connected to this pin.
Battery Instant-On and Ideal Diode External PMOS
Consideration
The instant-on voltage level is determined using the following formula:
ROFB1 + ROFB2
• 0.974V
ROFB2
Note that ROFB1 and ROFB2 are the same resistors that
program the output voltage regulation level. Therefore,
the output voltage regulation level is always 122.5% of
the instant-on voltage level.
VOUT(INST _ ON) =
During instant-on operation, it is critical to consider the
charging PMOS power dissipation. When the battery voltage is below the low battery threshold (VLOBAT), the power
dissipation in the PMOS can be calculated as follows:
PTRKL = [0.86 • VFLOAT – VBAT ] • ICLIM(TRKL)
where ICLIM(TRKL) is the trickle charge current limit.
After the charger terminates, the LTC4000-1 automatically
restarts another charge cycle if the battery feedback voltage
drops below 97.1% of the programmed final float voltage
(VRECHRG(FALL)). When charging restarts, the CHRG pin
pulls low and the FLT pin remains high impedance.
On the other hand, when the battery voltage is above the
low battery threshold but still below the instant-on threshold, the power dissipation can be calculated as follows:
Output Voltage Regulation Programming
where ICLIM is the full scale charge current limit.
The output voltage regulation level is determined using
the following formula:
For example, when charging a 3-cell Lithium Ion battery
with a programmed full charged current of 1A, the float
voltage is 12.6V, the bad battery voltage level is 8.55V and
the instant-on voltage level is 10.8V. During instant-on
operation and in the trickle charge mode, the worst case
V

ROFB1 =  OUT − 1 • ROFB2
 1.193 
PINST _ ON = [0.86 • VFLOAT – VBAT ] • ICLIM
40001f
19
LTC4000-1
Applications Information
maximum power dissipation in the PMOS is 1.08W. When
the battery voltage is above the bad battery voltage level,
then the worst case maximum power dissipation is 2.25W.
RBFB1 + RBFB2
• 1.136V
RBFB2
+R
R
= OFB1 OFB2 • 1.193V
ROFB2
VFLOAT =
VOUT
When overheating of the charging PMOS is a concern, it is
recommended that the user add a temperature detection
circuit that pulls down on the NTC pin. This pauses charging whenever the external PMOS temperature is too high.
A sample circuit that performs this temperature detection
function is shown in Figure 7.
VOUT(INST _ ON) =
ROFB1 + ROFB2
• 0.974V
ROFB2
In the typical application, VOUT is set higher than VFLOAT
to ensure that the battery is charged fully to its intended
float voltage. On the other hand, VOUT should not be
programmed too high since VOUT(INST_ON), the minimum
voltage on CSP, depends on the same resistors ROFB1 and
ROFB2 that set VOUT. As noted before, this means that the
output voltage regulation level is always 122.5% of the
instant-on voltage. The higher the programmed value of
VOUT(INST_ON), the larger the operating region when the
charger PMOS is driven in the linear region where it is
less efficient.
Similar to the input external PMOS, the charging external
PMOS must be able to withstand a gate to source voltage
greater than VBGATE(ON) (15V maximum) or the maximum
regulated voltage at the CSP pin, whichever is less. Consider
the expected maximum current, power dissipation and
instant-on voltage drop when selecting this PMOS. The
PMOS suggestions in Table 1 are an appropriate starting
point depending on the application.
Float Voltage, Output Voltage and Instant-On Voltage
Dependencies
If ROFB1 and ROFB2 are set to be equal to RBFB1 and RBFB2
respectively, then the output voltage is set at 105% of
the float voltage and the instant-on voltage is set at 86%
of the float voltage. Figure 8 shows the range of possible
The formulas for setting the float voltage, output voltage
and instant-on voltage are repeated here:
TO SYSTEM
CSP
RCS
LTC4000-1
VISHAY CURVE 2
NTC RESISTOR
THERMALLY COUPLED
WITH CHARGING PMOS
RNTC2
CSN
BGATE
M2
R4 = RNTC2
AT 25°C
BAT
BIAS
R3
CBIAS
162k
2N7002L
NTC
Li-Ion
BATTERY PACK
RNTC1
LTC1540
–
+
RISING
TEMPERATURE
THRESHOLD
SET AT 90°C
20k
VOLTAGE HYSTERESIS CAN
BE PROGRAMMED FOR
TEMPERATURE HYSTERESIS
86mV ≈ 10°C
40001 F07
Figure 7. Charging PMOS Overtemperature Detection Circuit
Protecting PMOS from Overheating
40001f
20
LTC4000-1
Applications Information
POSSIBLE
OUTPUT
VOLTAGE RANGE
105%
NOMINAL OUTPUT VOLTAGE
NOMINAL FLOAT VOLTAGE
POSSIBLE
INSTANT-ON
VOLTAGE RANGE
100%
MINIMUM PRACTICAL
OUTPUT VOLTAGE
100%
100%
86%
NOMINAL INSTANT-ON VOLTAGE
MINIMUM PRACTICAL
INSTANT-ON VOLTAGE
81.6%
75%
40001 F08
Figure 8. Possible Voltage Ranges for VOUT and VOUT(INST_ON) in Ideal Scenario
output voltages that can be set for VOUT(INST_ON) and VOUT
with respect to VFLOAT to ensure the battery can be fully
charged in an ideal scenario.
Taking into account possible mismatches between the
resistor dividers as well as mismatches in the various
regulation loops, VOUT should not be programmed to
be less than 105% of VFLOAT to ensure that the battery
can be fully charged. This automatically means that the
instant-on voltage level should not be programmed to be
less than 86% of VFLOAT.
Battery Temperature Qualified Charging
To use the battery temperature qualified charging feature,
connect an NTC thermistor, RNTC, between the NTC pin
and the GND pin, and a bias resistor, R3, from the BIAS
pin to the NTC pin (Figure 9). Thermistor manufacturer
datasheets usually include either a temperature lookup
table or a formula relating temperature to the resistor
value at that corresponding temperature.
In a simple application, R3 is a 1% resistor with a value
equal to the value of the chosen NTC thermistor at 25°C
(R25). In this simple setup, the LTC4000-1 will pause
charging when the resistance of the NTC thermistor
drops to 0.54 times the value of R25. For a Vishay
Curve 2 thermistor, this corresponds to approximately
41.5°C. As the temperature drops, the resistance of the
NTC thermistor rises. The LTC4000-1 is also designed
to pause charging when the value of the NTC thermistor
increases to three times the value of R25. For a Vishay
Curve 2 thermistor, this corresponds to approximately
–1.5°C. With Vishay Curve 2 thermistor, the hot and cold
comparators each have approximately 5°C of hysteresis
to prevent oscillation about the trip point.
The hot and cold threshold can be adjusted by changing
the value of R3. Instead of simply setting R3 to be equal to
R25, R3 is set according to one of the following formulas:
R3 =
RNTC at cold_ threshold
3
or
BIAS
LTC4000-1
R3
CBIAS
NTC
BAT
NTC RESISTOR
THERMALLY COUPLED
WITH BATTERY PACK
RNTC
40001 F09
R3 = 1.857 • RNTC at hot _ threshold
Notice that with only one degree of freedom (i.e. adjusting
the value of R3), the user can only use one of the formulas
above to set either the cold or hot threshold but not both.
If the value of R3 is set to adjust the cold threshold, the
value of the NTC resistor at the hot threshold is then
Figure 9. NTC Thermistor Connection
40001f
21
LTC4000-1
Applications Information
equal to 0.179 • RNTC at cold_threshold. Similarly, if the
value of R3 is set to adjust the hot threshold, the value
of the NTC resistor at the cold threshold is then equal to
5.571 • RNTC at cold_threshold.
Note that changing the value of R3 to be larger than R25
will move both the hot and cold threshold lower and vice
versa. For example, using a Vishay Curve 2 thermistor
whose nominal value at 25°C is 100k, the user can set
the cold temperature to be at 5°C by setting the value of
R3 = 75k, which automatically then sets the hot threshold
at approximately 50°C.
It is possible to adjust the hot and cold threshold independently by introducing another resistor as a second degree
of freedom (Figure 10). The resistor RD in effect reduces
the sensitivity of the resistance between the NTC pin and
ground. Therefore, intuitively this resistor will move the hot
threshold to a hotter temperature and the cold threshold
to a colder temperature.
BIAS
LTC4000-1
R3
CBIAS
NTC
RD
For example, this method can be used to set the hot
and cold thresholds independently to 60°C and –5°C.
Using a Vishay Curve 2 thermistor whose nominal value
at 25°C is 100k, the formula results in R3 = 130k and
RD = 41.2k for the closest 1% resistors values.
To increase thermal sensitivity such that the valid charging
temperature band is much smaller than 40°C, it is possible to put a PTC (positive thermal coefficient) resistor
in series with R3 between the BIAS pin and the NTC pin.
This PTC resistor also needs to be thermally coupled with
the battery. Note that this method increases the number of
thermal sensing connections to the battery pack from one
wire to three wires. The exact value of the nominal PTC
resistor required can be calculated using a similar method
as described above, keeping in mind that the threshold at
the NTC pin is always 75% and 35% of VBIAS.
Leaving the NTC pin floating or connecting it to a capacitor
disables all NTC functionality.
Battery Voltage Temperature Compensation
BAT
NTC RESISTOR
THERMALLY COUPLED
WITH BATTERY PACK
if the user finds that a negative value is needed for RD,
the two temperature thresholds selected are too close to
each other and a higher sensitivity thermistor is needed.
RNTC
40001 F10
Figure 10. NTC Thermistor Connection with
Desensitizing Resistor RD
The value of R3 and RD can now be set according to the
following formula:
Some battery chemistries have charge voltage requirements that vary with temperature. Lead-acid batteries in
particular experience a significant change in charge voltage requirements as temperature changes. For example,
manufacturers of large lead-acid batteries recommend a
float charge of 2.25V/cell at 25°C. This battery float voltage,
however, has a temperature coefficient which is typically
specified at –3.3mV/°C per cell.
1.219 • RNTC at hot _ threshold
The LTC4000-1 employs a resistor feedback network to
program the battery float voltage. manipulation of this
network makes for an efficient implementation of various temperature compensation schemes of battery float
voltage.
Note the important caveat that this method can only be
used to desensitize the thermal effect on the thermistor
and hence push the hot and cold temperature thresholds
apart from each other. When using the formulas above,
A simple solution for tracking such a linear voltage dependence on temperature is to use the LM234 3-terminal
temperature sensor. This creates an easily programmable
linear temperature dependent characteristic.
RNTC at cold_ threshold – RNTC at hot _ threshold
2.461
RD = 0.219 • RNTC at cold_ threshold –
R3 =
40001f
22
LTC4000-1
Applications Information
(TC = –19.8mV/°C and VFLOAT(25°C) = 13.5V) and RSET =
2.43k into the equation, we obtained the following values:
RBFB1 = 210k and RBFB2 = 13.0k.
14.4
14.2
14.0
VFLOAT (V)
13.8
3-Step Charging for Lead-Acid Battery
13.6
13.4
13.2
13.0
12.8
12.6
–10
0
20
40
10
30
TEMPERATURE (°C)
60
50
40001 F11
Figure 11. Lead-Acid 6-Cell Float Charge Voltage vs
Temperature Using LM234 with the Feedback Network
TRICKLE
CHARGE
BAT
CONSTANT
CURRENT
RBFB1
210k
TERMINATION
V+
R
RSET
2.43k
BFB
RBFB2
13.0k
BATTERY VOLTAGE
V–
6-CELL
LEAD-ACID
BATTERY
CHARGE
CURRENT
40001 F12
Figure 12. Battery Voltage Temperature Compensation Circuit
RBFB1 = –RSET • (TC • 4405)
and
RBFB1 • 1.136V

 0.0677  
 VFLOAT(25°C) + RBFB1 •  R
  – 1.136V

SET  
40001 F13
CHARGE TIME
Figure 13. Li-Ion Typical Charging Cycle
In the circuit shown in Figure 12,
RBFB2 =
CONSTANT VOLTAGE
LM234
LTC4000-1
FBG
The LTC4000-1 naturally lends itself to charging applications requiring a constant current step followed by
constant voltage. Furthermore, the LTC4000-1 additional
features such as trickle charging, bad battery detection
and C/X or timer termination makes it an excellent fit for
Lithium based battery charging applications. Figure 13
and Table 2 show the normal steps involved in Lithium
battery charging.
Table 2. Lithium Based Battery Charging Steps
STEP
CHARGE METHOD
DURATION
Trickle Charge
Constant Current at a
Lower Current Value,
Usually 1/10th of Full
Charge Current
Until Battery Voltage Rises
Above Low Battery Threshold
Constant Current at
Full Charge Current
Until Battery Voltage Reaches
Float Voltage
Constant Current
Time Limit Set at TMR Pin
No Time Limit
Where: TC = temperature coefficient in V/°C and VFLOAT(25°C)
is the desired battery float voltage at 25°C in V.
Constant Voltage
Constant Voltage
For example, a 6-cell lead-acid battery has a float charge
voltage that is commonly specified at 2.25V/cell at 25°C
or 13.5V, and a –3.3mV/°C per cell temperature coefficient or –19.8mV/°C. Substituting these two parameters
Recharge
Initiate Constant
Current Again When
Battery Voltage Drops
Below Recharge
Threshold
Terminate Either When
Charge Current Falls to the
Programmed Level at the CX
Pin or after the Termination
Timer at TMR Pin Expires
40001f
23
LTC4000-1
Applications Information
On the other hand, the LTC4000-1 is also easily configurable to handle lead-acid based battery charging. One of
the common methods used in lead-acid battery charging
is called 3-step charging (Bulk, Absorption and Float).
Figure 14 and Table 3 summarize the normal steps involved
in a typical 3-step charging of a lead-acid battery.
FROM DC/DC
OUTPUT
LTC4000-1
CSP
RCS
CSN
BAT
FBG
RBFB2
BFB
RBFB1
RBFB3
CX
BATTERY VOLTAGE
BULK
CHARGE
ABSORPTION
FLOAT
(STORAGE)
RCX
CL CHRG
LEAD-ACID
BATTERY
RCL
40001 F15
Figure 15. 3-Step Lead-Acid Circuit Configuration
CHARGE
CURRENT
40001 F14
CHARGE TIME
When a charging cycle is initiated, the CHRG pin is pulled
low. The charger first enters the bulk charge step, charging the battery with a constant current programmed at
the CL pin:
Figure 14. Lead-Acid 3-Step Charging Cycle
Table 3. Lead-Acid Battery Charging Steps
STEP
CHARGE METHOD
DURATION
Bulk Charge
Constant Current
Until Battery Voltage Reaches
Absorption Voltage
Absorption
Constant Voltage
at the Absorption
Voltage Level
Terminate When Charge
Current Falls to the
Programmed Level at the CX
Pin
Float (Storage)
Constant Voltage
at the Lower Float
Voltage Level (Float
Voltage Is Lower
than the Absorption
Voltage)
Indefinite
No Time Limit
Recharge
Initiate Bulk Charge
Again When Battery
Voltage Drops Below
Recharge Threshold
Figure 15 shows the configuration needed to implement
this 3-step lead-acid battery charging with the LTC4000-1.
ICLIM =
MIN( 50mV, 2.5µA • RCL )
RCS
When the battery voltage rises to the Absorption voltage
level:
R
(R + RBFB3 ) + 1 • 1.136V
VABSRP =  BFB1 BFB2

RBFB2RBFB3

the charger enters the Absorption step, charging the battery at a constant voltage at this absorption voltage level.
As the charge current drops to the C/X level:
ICLIM =
(0.25µA • RCX ) – 0.5mV
RCS
the CHRG pin turns high impedance and now the charger
enters the Float (Storage) step, charging the battery voltage at the constant float voltage level:
R

VFLOAT =  BFB1 + 1 • 1.136V
 RBFB2 
40001f
24
LTC4000-1
Applications Information
Note that in this configuration, the recharge threshold is
97.6% of the float voltage level. When the battery voltage
drops below this level, the whole 3-step charging cycle is
reinitiated starting with the bulk charge.
Some systems require trickle charging of an over discharged lead-acid battery. This feature can be included
using the CL pin of the LTC4000-1. In the configuration
shown in Figure 15, when the battery voltage is lower
than 68% of the Absorption level, the pull-up current on
the CL pin is reduced to 10% of the normal pull-up current. Therefore, the trickle charge current can be set at
the following level:
ICLIM =
MIN( 50mV, 0.25µA • RCL )
RCS
If this feature is not desired, leave the CL pin open to set
the regulation voltage across the charge current sense
resistor (RCS) always at 50mV.
The FLT and CHRG Indicator Pins
The FLT and CHRG pins in the LTC4000-1 provide status
indicators. Table 4 summarizes the mapping of the pin
states to the part status.
Table 4. FLT and CHRG Status Indicator
FLT
CHRG
0
0
STATUS
NTC Over Ranged – Charging Paused
1
0
Charging Normally
0
1
Charging Terminated and Bad Battery Detected
1
1
VIBMON < (VC/X – 10mV)
where 1 indicates a high impedance state and 0 indicates
a low impedance pull-down state.
Note that VIBMON < (VCX – 10mV) corresponds to charge
termination only if the C/X termination is selected. If the
charger timer termination is selected, constant voltage
charging may continue for the remaining charger timer
period even after the indicator pins indicate that VIBMON
< (VCX – 10mV). This is also true when no termination is
selected, constant voltage charging will continue even after
the indicator pins indicate that VIBMON < (VCX – 10mV).
The BIAS Pin
For ease of use the LTC4000-1 provides a low dropout
voltage regulator output on the BIAS pin. Designed to
provide up to 0.5mA of current at 2.9V, this pin requires
at least 470nF of low ESR bypass capacitance for stability.
Use the BIAS pin as the pull-up source for the NTC resistor networks, since the internal reference for the NTC
circuitry is based on a ratio of the voltage on the BIAS
pin. Furthermore, various 100k pull-up resistors can be
conveniently connected to the BIAS pin.
Setting the Input Voltage Monitoring Resistor Divider
The falling threshold voltage level for this monitoring
function can be calculated as follows:
V

RVM1 =  VM _ RST – 1 • R VM2
 1.193V

where RVM1 and RVM2 form a resistor divider connected
between the monitored voltage and GND, with the center
tap point connected to the VM pin as shown in Figure 6. The
rising threshold voltage level can be calculated similarly.
Input Voltage Programming
Connecting a resistor divider from VIN to the IFB pin enables programming of a minimum input supply voltage.
This feature is typically used to program the peak power
voltage for a high impedance input source. Referring to
Figure 2, the input voltage regulation level is determined
using the following formula:
V

RIFB1 =  IN _ REG – 1 RIFB2
 1V

Where VIN_REG is the minimum regulation input voltage
level, below which the current draw from the input source
is reduced.
Combining the Input Voltage Programming and the
Input Voltage Monitoring Resistor Divider
When connected to the same input voltage node, the input
voltage monitoring and the input voltage regulation resistor
divider can be combined (see Figure 16).
40001f
25
LTC4000-1
Applications Information
RIS
IN
DC/DC INPUT
CCLN
(OPTIONAL)
CIN
RVM3
IN
CLN
VM
–
1.193V
+
TO DC/DC EN PIN
RST
CP1
CVM
CC
RVM4
IFB
RIFB2
1V
–
+
A4
LTC4000-1
CC
–
+
RC
ITH
TO DC/DC
COMPENSATION
PIN
40001 F16
Figure 16. Input Voltage Monitoring and Input Voltage
Regulation Resistor Divider Combined
In this configuration use the following formula to determine
the values of the three resistors:

1.193V   VIN _ REG 
RVM3 =  1–

 RIFB2
 VVM _ RST   1V 
MPPT Temperature Compensation – Solar Panel
Example
The input regulation loop of the LTC4000-1 allows a user to
program a minimum input supply voltage regulation level
allowing for high impedance source to provide maximum
available power. With typical high impedance source such
as a solar panel, this maximum power point varies with
temperature.
A typical solar panel is comprised of a number of seriesconnected cells, each cell being a forward-biased p-n
junction. As such, the open-circuit voltage (VOC) of a
solar cell has a temperature coefficient that is similar to
a common p-n junction diode, about –2mV/°C. The peak
power point voltage (VMP) for a crystalline solar panel
can be approximated as a fixed percentage of VOC, so the
temperature coefficient for the peak power point is similar
to that of VOC.
Panel manufacturers typically specify the 25°C values for
VOC, VMP and the temperature coefficient for VOC, making
determination of the temperature coefficient for VMP of a
typical panel straight forward.

 V
 
RVM4 =  1.193  IN _ REG  – 1 RIFB2
 VVM _ RST  

When the RST pin of the LTC4000-1 is connected to the
SHDN or RUN pin of the converter, it is recommended that
the value of VIN_REG is set higher than the VVM_RST pin by a
significant margin. This is to ensure that any voltage noise
or ripple on the input supply pin does not cause the RST
pin to shut down the converter prematurely, preventing
the input regulation loop from functioning as expected.
As discussed in the input current monitoring section,
noise issues on the input node can be reduced by placing
a large filter capacitor on the CLN node (CCLN). To further
reduce the effect of any noise on the monitoring function,
another filter capacitor placed on the VM pin (CVM) is
recommended.
PANEL VOLTAGE
Note that for the RVM4 value to be positive, the ratio of
VIN_REG to VVM_RST has to be greater than 0.838.
VOC TEMP CO.
VOC(25°C)
VOC
VMP(25°C)
VOC – VMP
VMP
5
15
25
35
TEMPERATURE (°C)
45
55
40001 F17
Figure 17. Temperature Characteristic of a Solar
Panel Open Circuit and Peak Power Point Voltages
In a manner similar to the battery float voltage temperature
compensation, implementation of the MPPT temperature
compensation can be accomplished by incorporating an
LM234 into the input voltage feedback network. Using the
40001f
26
LTC4000-1
Applications Information
feedback network in Figure 18, a similar set of equations
can be used to determine the resistor values:
RIFB1 = –RSET • (TC • 4405)
and
RIFB2 =
RIFB1 • 1V

 0.0677  
 VMP(25°C) + RIFB1 •  R
  – 1V

SET  
Where: TC = temperature coefficient in V/°C, and
VMP(25°C) = maximum power point voltage at 25°C in V.
VIN
IN
LM234
V+
R
V–
RSET
1k
LTC4000-1
RIFB1
348k
IFB
RIFB2
8.66k
40001 F18
Figure 18. Maximum Power Point Voltage Temperature
Compensation Feedback Network
For example, given a common 36-cell solar panel that has
the following specified characteristics:
Open circuit voltage (VOC) = 21.7V
Maximum power voltage (VMP) = 17.6V
Open-circuit voltage temperature coefficient
(VOC) = –78mV/°C
As the temperature coefficient for VMP is similar to that of
VOC, the specified temperature coefficient for VOC (TC) of
–78mV/°C and the specified peak power voltage (VMP(25°C))
of 17.6V can be inserted into the equations to calculate the
appropriate resistor values for the temperature compensation network in Figure 18. With RSET equal to 1kΩ, then:
RSET = 1kΩ, RIFB1 = 348kΩ, RIFB2 = 8.66kΩ.
typical sinking capability of the LTC4000-1 at the ITH pin
is 1mA at 0.4V with a maximum voltage range of 0V to 6V.
It is imperative that the local feedback of the DC/DC converter be set up such that during regulation of any of the
LTC4000-1 loops this local loop is out of regulation and
sources as much current as possible from its ITH/VC pin.
For example for a DC/DC converter regulating its output
voltage, it is recommended that the converter feedback
divider is programmed to be greater than 110% of the
output voltage regulation level programmed at the OFB pin.
There are four feedback loops to consider when setting
up the compensation for the LTC4000-1. As mentioned
before these loops are: the input voltage loop, the charge
current loop, the float voltage loop and the output voltage loop. All of these loops have an error amp (A4-A7)
followed by another amplifier (A10) with the intermediate
node driving the CC pin and the output of A10 driving the
ITH pin as shown in Figure 19. The most common compensation network of a series capacitor (CC) and resistor
(RC) between the CC pin and the ITH pin is shown here.
Each of the loops has slightly different dynamics due to
differences in the feedback signal path. The analytic description of the input voltage regulation loop is included
in the Appendix section. Please refer to the LTC4000 data
sheet for the analytic description of the other three loops.
In most situations, an alternative empirical approach to
compensation, as described here, is more practical.
A4-A7
gm4-7 = 0.2m
+
–
LTC4000-1
RO4-7
CC
A10
gm10 = 0.1m
–
+
ITH
CC
RC
RO10
40001 F11
Figure 19. Error Amplifier Followed by Output Amplifier Driving
CC and ITH Pins
Compensation
Empirical Loop Compensation
In order for the LTC4000-1 to control the external DC/DC
converter, it has to be able to overcome the sourcing bias
current of the ITH or VC pin of the DC/DC converter. The
Based on the analytical expressions and the transfer
function from the ITH pin to the input and output current
of the external DC/DC converter, the user can analytically
40001f
27
LTC4000-1
Applications Information
determine the complete loop transfer function of each of
the loops. Once these are obtained, it is a matter of analyzing the gain and phase bode plots to ensure that there is
enough phase and gain margin at unity crossover with the
selected values of RC and CC for all operating conditions.
may cause a blinking scope display and higher frequencies may not allow sufficient settling time for the output
transient. Amplitude of the generator output is typically
set at 5VP-P to generate a 100mAP-P load variation. For
lightly loaded outputs (IOUT < 100mA), this level may be
too high for small signal response. If the positive and
negative transition settling waveforms are significantly
different, amplitude should be reduced. Actual amplitude
is not particularly important because it is the shape of
the resulting regulator output waveform which indicates
loop stability.
Even though it is clear that an analytical compensation
method is possible, sometimes certain complications
render this method difficult to tackle. These complications include the lack of easy availability of the switching
converter transfer function from the ITH or VC control
node to its input or output current, and the variability of
parameter values of the components such as the ESR of
the output capacitor or the RDS(ON) of the external PFETs.
A 2-pole oscilloscope filter with f = 10kHz is used to
block switching frequencies. Regulators without added
LC output filters have switching frequency signals at their
outputs which may be much higher amplitude than the
low frequency settling waveform to be studied. The filter
frequency is high enough for most applications to pass
the settling waveform with no distortion.
Therefore a simpler and more practical way to compensate
the LTC4000-1 is provided here. This empirical method
involves injecting an AC signal into the loop, observing
the loop transient response and adjusting the CC and RC
values to quickly iterate towards the final values. Much
of the detail of this method is derived from Application
Note 19 which can be found at www.linear.com using
AN19 in the search box.
Oscilloscope and generator connections should be made
exactly as shown in Figure 20 to prevent ground loop errors. The oscilloscope is synced by connecting the channel B probe to the generator output, with the ground clip
of the second probe connected to exactly the same place
as channel A ground. The standard 50Ω BNC sync output
of the generator should not be used because of ground
loop errors. It may also be necessary to isolate either
the generator or oscilloscope from its third wire (earth
Figure 20 shows the recommended setup to inject an
AC-coupled output load variation into the loop. A function
generator with 50Ω output impedance is coupled through
a 50Ω/1000µF series RC network to the regulator output.
Generator frequency is set at 50Hz. Lower frequencies
SWITCHING
CONVERTER
GND
ITH
1k
0.015µF
RC
CC
CLN
ITH
CC
CSP
LTC4000-1
IN
IOUT
A
10k
B
1500pF
50Ω
1W
1000µF
(OBSERVE
POLARITY)
SCOPE
GROUND
CLIP
CSN
GND BAT BGATE
VIN
50Ω
GENERATOR
f = 50Hz
40001 F20
Figure 20. Empirical Loop Compensation Setup
40001f
28
LTC4000-1
Applications Information
ground) connection in the power plug to prevent ground
loop errors in the scope display. These ground loop errors
are checked by connecting channel A probe tip to exactly
the same point as the probe ground clip. Any reading on
channel A indicates a ground loop problem.
Once the proper setup is made, finding the optimum
values for the frequency compensation network is fairly
straightforward. Initially, CC is made large (≥1μF) and RC
is made small (≈10k). This nearly always ensures that the
regulator will be stable enough to start iteration. Now, if
the regulator output waveform is single-pole over damped
(see the waveforms in Figure 21), the value of CC is reduced in steps of about 2:1 until the response becomes
slightly under damped. Next, RC is increased in steps of
2:1 to introduce a loop zero. This will normally improve
damping and allow the value of CC to be further reduced.
Shifting back and forth between RC and CC variations will
allow one to quickly find optimum values.
If the regulator response is under damped with the initial
large value of CC, RC should be increased immediately before
larger values of CC are tried. This will normally bring about
the over damped starting condition for further iteration.
The optimum values for RC and CC normally means the
smallest value for CC and the largest value for RC which
still guarantee well damped response, and which result in
GENERATOR OUTPUT
REGULATOR OUTPUT
WITH LARGE CC, SMALL RC
WITH REDUCED CC, SMALL RC
EFFECT OF INCREASED RC
FURTHER REDUCTION IN CC
MAY BE POSSIBLE
IMPROPER VALUES WILL
CAUSE OSCILLATIONS
40001 F21
Figure 21. Typical Output Transient Response at Various
Stability Level
the largest loop bandwidth and hence loop settling that is
as rapid as possible. The reason for this approach is that
it minimizes the variations in output voltage caused by
input ripple voltage and output load transients.
A switching regulator which is grossly over damped will
never oscillate, but it may have unacceptably large output
transients following sudden changes in input voltage or
output loading. It may also suffer from excessive overshoot
problems on startup or short circuit recovery. To guarantee
acceptable loop stability under all conditions, the initial
values chosen for RC and CC should be checked under all
conditions of input voltage and load current. The simplest
way of accomplishing this is to apply load currents of
minimum, maximum and several points in between. At
each load current, input voltage is varied from minimum
to maximum while observing the settling waveform.
If large temperature variations are expected for the system,
stability checks should also be done at the temperature
extremes. There can be significant temperature variations in several key component parameters which affect
stability; in particular, input and output capacitor value
and their ESR, and inductor permeability. The external
converter parametric variations also need some consideration especially the transfer function from the ITH/VC
pin voltage to the output variable (voltage or current). The
LTC4000-1 parameters that vary with temperature include
the transconductance and the output resistance of the
error amplifiers (A4-A7). For modest temperature variations, conservative over damping under worst-case room
temperature conditions is usually sufficient to guarantee
adequate stability at all temperatures.
One measure of stability margin is to vary the selected
values of both RC and CC by 2:1 in all four possible combinations. If the regulator response remains reasonably
well damped under all conditions, the regulator can be
considered fairly tolerant of parametric variations. Any
tendency towards an under damped (ringing) response
indicates that a more conservative compensation may
be needed.
40001f
29
LTC4000-1
Applications Information
Design Example
• RCL is set at 24.9kΩ such that the voltage at the CL pin
is 1.25V. Similar to the IIMON pin, the regulation voltage
on the IBMON pin is clamped at 1V with an accurate
internal reference. Therefore, the charge current limit
is set at 10A according to the following formula:
In this design example, the LTC4000-1 is paired with the
LT3845A buck converter to create a 10A, 3-cell LiFePO4
battery charger. The circuit is shown on the front page
and is repeated here in Figure 22.
• With RIFB2 set at 20k, the input voltage monitoring falling
threshold is set at 15V and the input voltage regulation
level is set at 17.6V according to the following formulas:
ICLIM(MAX) =
0.050V 0.050V
=
= 10A
RCS
5mΩ
• The trickle charge current level is consequently set at
1.25A, according to the following formula:
 1.193V   17.6V 
RVM3 =  1−

 20kΩ = 324kΩ

15V   1V 
ICLIM(TRKL) = 0.25µA •

 17.6V  
RVM4 =  1.193V 
− 1 20kΩ = 8.06kΩ
 15V  

24.9kΩ
= 1.25A
5mΩ
• The battery float voltage is set at 10.8V according to
the following formula:
• The input current sense resistor is set at 5mΩ. Therefore, the voltage at the IIMON pin is related to the input
current according to the following formula:

 10.8
RBFB1 = 
− 1 • 133kΩ ≈ 1.13MΩ
 1.136 
VIIMON = (0.1Ω) • IRIS
SOLAR PANEL INPUT
<60V OPEN CIRCUIT VOLTAGE
17.6V PEAK POWER VOLTAGE
5mΩ
LT3845A
IN
BIAS
VC
SHDN
1M
324k
20k
1.15M
47nF
ITH
CC
IID IGATE CSP
5mΩ
Si7135DP
CSN
BGATE
BAT
1µF
OFB
VM
8.06k
VOUT
12V, 15A
100µF
14.7k
RST
CLN
IN
Si7135DP
OUT
127k
LTC4000-1
3.0V
FBG
133k
IFB
ENC
CHRG
FLT IIMON
BFB
1.13M
NTC
IBMON
TMR
10k
GND BIAS
BIAS
10nF
10nF
CX
CL
0.1µF
24.9k
22.1k
1µF
10k
NTHS0603
N02N1002J
VBAT
10.8V FLOAT
10A MAX CHARGE
CURRENT
3-CELL Li-Ion
BATTERY PACK
40001 F22
Figure 22. 10.8V at 10A Charger for Three LiFePO4 Cells with Solar Panel Input
40001f
30
LTC4000-1
Applications Information
• The bad battery detection time is set at 43 minutes
according to the following formula:
CTMR (nF) = tBADBAT (h) • 138.5 =
43
• 138.5 = 100nF
60
• The charge termination time is set at 2.9 hours according to the following formula:
CTMR (nF) = t TERMINATE (h) • 34.6 = 2.9 • 34.6 = 100nF
• The C/X current termination level is programmed at 1A
according to the following formula:
RCX =
(1A • 5mΩ) + 0.5mV ≈ 22.1kΩ
0.25µA
Note that in this particular solution, the timer termination is selected since a capacitor connects to the TMR
pin. Therefore, this C/X current termination level only
applies to the CHRG indicator pin.
• The output voltage regulation level is set at 12V according to the following formula:
 12

ROFB1 = 
− 1 • 127kΩ ≈ 1.15MΩ
 1.193 
• The instant-on voltage level is consequently set at 9.79V
according to the following formula:
VINST _ ON =
Therefore, depending on the layout and heat sink available to the charging PMOS, the suggested PMOS over
temperature detection circuit included in Figure 7 may
need to be included.
• The range of valid temperature for charging is set at
–1.5°C to 41.5°C by picking a 10k Vishay Curve 2 NTC
thermistor that is thermally coupled to the battery, and
connecting this in series with a regular 10k resistor to
the BIAS pin.
• For compensation, the procedure described in the
empirical loop compensation section is followed. As
recommended, first a 1µF CC and 10k RC is used, which
sets all the loops to be stable. For an example of typical
transient responses, the charge current regulation loop
when VOFB is regulated to VOUT(INST_ON) is used here.
Figure 23 shows the recommended setup to inject a
DC-coupled charge current variation into this particular
loop. The input to the CL pin is a square wave at 70Hz
with the low level set at 120mV and the high level set
at 130mV, corresponding to a 1.2A and 1.3A charge
current (100mA charge current step). Therefore, in this
particular example the trickle charge current regulation
stability is examined. Note that the nominal trickle
charge current in this example is programmed at 1.25A
(RCL = 24.9kΩ).
1150kΩ + 127kΩ
• 0.974V = 9.79V
127kΩ
The worst-case power dissipation during instant-on
operation can be calculated as follows:
B
A
10k
1500pF
1k
IBMON
0.015µF
LTC4000-1
• During trickle charging:
PTRKL = [0.86 • VFLOAT – VBAT ] • ICLIM _ TRKL
= [0.86 • 10.8] • 1A
= 9.3W
CL
SQUARE WAVE
GENERATOR
f = 60Hz
40001 F23
• And beyond trickle charging:
PINST _ ON = [0.86 • VFLOAT – VBAT ] • ICLIM
= [0.86 • 10.8 – 7.33] • 10A
Figure 23. Charge Current Regulation Loop Compensation Setup
= 19.3W
40001f
31
LTC4000-1
Applications Information
With CC = 1µF, RC = 10k at VIN = 20V, VBAT = 7V, VCSP
regulated at 9.8V and a 0.2A output load condition at
CSP, the transient response for a 100mA charge current
step observed at IBMON is shown in Figure 24.
10
15
5
10
0
5
VIBMON (mV)
5mV/DIV
VIBMON (mV)
5mV/DIV
15
The transient response now indicates an overall under
damped system. As noted in the empirical loop compensation section, the value of RC is now increased iteratively
until RC = 20k. The transient response of the same loop
with CC = 22nF and RC = 20k is shown in Figure 26.
–5
–10
–15
–20 –15 –10
5
0
5ms/DIV
–5
10
15
20
–15
–20 –15 –10
Figure 24. Transient Response of Charge Current Regulation Loop
Observed at IBMON When VOFB is Regulated to VOUT(INST_ON) with
CC = 1µF, RC = 10k for a 100mA Charge Current Step
The transient response shows a small overshoot with slow
settling indicating a fast minor loop within a well damped
overall loop. Therefore, the value of CC is reduced iteratively
until CC = 22nF. The transient response of the same loop
with CC = 22nF and RC = 10k is shown in Figure 25.
15
VIBMON (mV)
5mV/DIV
10
5
0
–5
–10
–5
5
0
5ms/DIV
10
15
20
–5
–10
25
40001 F24
–15
–20 –15 –10
0
25
40001 F25
Figure 25. Transient Response of Charge Current Regulation Loop
Observed at IBMON When VOFB is Regulated to VOUT(INST_ON) with
CC = 22nF, RC = 10k for a 100mA Charge Current Step
–5
5
0
5ms/DIV
10
15
20
25
40001 F26
Figure 26. Transient Response of Charge Current Regulation Loop
Observed at IBMON When VOFB is Regulated to VOUT(INST_ON) with
CC = 22nF, RC = 20k for a 100mA Charge Current Step
Note that the transient response is close to optimum
with some overshoot and fast settling. If after iteratively
increasing the value of RC, the transient response again
indicates an over damped system, the step of reducing
CC can be repeated. These steps of reducing CC followed
by increasing RC can be repeated continuously until one
arrives at a stable loop with the smallest value of CC and
the largest value of RC. In this particular example, these
values are found to be CC = 22nF and RC = 20kΩ.
After arriving at these final values of RC and CC, the stability
margin is checked by varying the values of both RC and
CC by 2:1 in all four possible combinations. After which
the setup condition is varied, including varying the input
voltage level and the output load level and the transient
response is checked at these different setup conditions.
Once the desired responses on all different conditions are
obtained, the values of RC and CC are noted.
40001f
32
LTC4000-1
Applications Information
This same procedure is then repeated for the other four
loops: the input voltage regulation, the output voltage
regulation, the battery float voltage regulation and finally
the charge current regulation when VOFB > VOUT(INST_ON).
Note that the resulting optimum values for each of the loops
may differ slightly. The final values of CC and RC are then
selected by combining the results and ensuring the most
conservative response for all the loops. This usually entails
picking the largest value of CC and the smallest value of
RC based on the results obtained for all the loops. In this
particular example, the value of CC is finally set to 47nF
and RC = 14.7kΩ.
Board Layout Considerations
In the majority of applications, the most important parameter of the system is the battery float voltage. Therefore,
the user needs to be extra careful when placing and routing the feedback resistor RBFB1 and RBFB2. In particular,
the battery sense line connected to RBFB1 and the ground
return line for the LTC4000-1 must be Kelvined back
to where the battery output and the battery ground are
located respectively. Figure 27 shows this Kelvin sense
configuration.
For accurate current sensing, the sense lines from RIS
and RCS (Figure 27) must be Kelvined back all the way
to the sense resistors terminals. The two sense lines of
each resistor must also be routed close together and away
from noise sources to minimize error. Furthermore, current filtering capacitors should be placed strategically to
ensure that very little AC current is flowing through these
sense resistors as mentioned in the applications section.
The decoupling capacitors CIN and CBIAS must be placed as
close to the LTC4000-1 as possible. This allows as short
a route as possible from CIN to the IN and GND pins, as
well as from CBIAS to the BIAS and GND pins.
In a typical application, the LTC4000-1 is paired with an
external DC/DC converter. The operation of this converter
often involves high dV/dt switching voltage as well as
high currents. Isolate these switching voltages and currents from the LTC4000-1 section of the board as much
as possible by using good board layout practices. These
include separating noisy power and signal grounds, having
a good low impedance ground plane, shielding whenever
necessary, and routing sensitive signals as short as possible and away from noisy sections of the board.
SWITCHING
CONVERTER
GND
ITH
SYSTEM LOAD
RC
CC
ITH
CC
CLN
RIS
IID IGATE
CSP
RCS
LTC4000-1
IN
CSN
BGATE
BAT
RBFB1
BFB
VIN
RBFB2
GND
FBG
40001 F27
Figure 27. Kelvin Sense Lines Configuration for LTC4000-1
40001f
33
LTC4000-1
Applications Information
Appendix—The Loop Transfer Functions
The Input Voltage Regulation Loop
When a series resistor (RC) and capacitor (CC) is used
as the compensation network as shown in Figure 19, the
transfer function from the input of A4-A7 to the ITH pin
is simply as follows:
The feedback signal for the input voltage regulation loop
is the voltage on the IFB pin, which is connected to the
center node of the resistor divider between the input
voltage (connected to the IN pin) and GND. This voltage
is compared to an internal reference (1.000V typical) by
the transconductance error amplifier A4. This amplifier
then drives the output transconductance amplifier (A10)
to appropriately adjust the voltage on the ITH pin driving
the external DC/DC converter to regulate the output voltage observed by the IFB pin. This loop is shown in detail
in Figure 28.


1 
C
s+1

  RC –
C
gm10 

VITH


(s) = gm4-7


RO4-7 •CCs
VFB




where gm4-7 is the transconductance of error amplifier A4A7, typically 0.5mA/V; gm10 is the output amplifier (A10)
transconductance, RO4-7 is the output impedance of the
error amplifier, typically 50MΩ; and RO10 is the effective
output impedance of the output amplifier, typically 10MΩ
with the ITH pin open circuit.
Note this simplification is valid when gm10 • RO10 • RO4-7
• CC = AV10 • RO4-7 • CC is much larger than any other
poles or zeroes in the system. Typically AV10 • RO4-7 = 5 •
1010 with the ITH pin open circuit. The exact value of gm10
and RO10 depends on the pull-up current and impedance
connected to the ITH pin respectively.
In most applications, compensation of the loops involves
picking the right values of RC and CC. Aside from picking
the values of RC and CC, the value of gm10 may also be
adjusted. The value of gm10 can be adjusted higher by
increasing the pull-up current into the ITH pin and its
value can be approximated as:
gm10
Assuming RIS << RIN << (RIFB1 + RIFB2), the simplified
loop transmission is as follows:


1 
CCs + 1
  RC –

gm10 

 • Gmi (s) •
LIV (s) = gm4 
p


CCs





  RIFB2 
RIN

•

R
C
+
C
s
+
1
(
)
IN
IN
CLN

  RIFB 
where Gmip(s) is the transfer function from VITH to the
input current of the external DC/DC converter, RIN is the
equivalent output impedance of the input source, and
RIFB = RIFB1 + RIFB2.
RIS
IN
CIN
I + 5µA
= ITH
50mV
The higher the value of gm10, the smaller the lower limit
of the value of RC would be. This lower limit is to prevent
the presence of the right half plane zero.
Even though all the loops share this transfer function from
the error amplifier input to the ITH pin, each of the loops
has a slightly different dynamic due to differences in the
feedback signal path.
DC/DC INPUT
CCLN
(OPTIONAL)
IN
RIFB1
RIFB2
CLN
A4
gm4 = 0.5m
IFB
1V
–
+
RO4
LTC4000-1
CC
A10
gm10 = 0.1m
–
+
CC
ITH
RC
TO DC/DC
RO10
40001 F28
Figure 28. Simplified Linear Model of the Input Voltage
Regulation Loop
40001f
34
V–
V+
8.66k
1k
R
LM234
348k
47µF
100k
1.10M
20mΩ
3.0V
1µF
BIAS
49.9k
1.5nF
CLN
IN
ENC
FLT
IFB
VM
BG
SW
TG
SENSE+
BURST_EN
VFB
VCC
BOOST
LT3845A
VIN
RST
10nF
IIMON
ITH
14.7k
–
SHDN VC SENSE
fSET
SGND
SYNC
CSS
2.2µF
182k
16.2k
10nF
IBMON
CC
47nF
1µF
BAS521
BSC123NO8NS3
0.1µF
BSC123NO8NS3
CL
24.9k
TMR
LTC4000-1
1N4148
B160
CX
20k
Si7135DP
NTC
40001 F29
CHRG
BFB
FBG
OFB
CSN
BGATE
BAT
IID IGATE CSP
BIAS
1µF
33µF
×3
GND BIAS
3mΩ
WÜRTH ELEKTRONIC
74435561100
10µH
442k
13.0k
R
V+
6-CELL
LEAD-ACID
BATTERY
V–
LM234
2.4k
210k
15mΩ
VOUT
13.5V
Figure 29. Solar Panel Input, 6-Cell Lead-Acid, 3-Step Battery Charger with 3.3A Bulk Charge Current, 14.1V at 25°C Absorption Voltage and 13.5V at
25°C Float Voltage. Temperature Compensation of Battery Float Voltage at –19.8mV/°C. Temperature Compensation of Solar Panel Input VMP at –78mV/°C
with VMP = 17.6V at 25°C
SOLAR PANEL INPUT
<40V OPEN CIRCUIT VOLTAGE
17.6V PEAK POWER VOLTAGE
LTC4000-1
Typical Applications
40001f
35
HIGH IMPEDANCE
INPUT SOURCE
8V TO 18V WITH
PEAK POWER
VOLTAGE AT 11.7V
36
1µF
100k
10nF
GND
CL
22.1k
CX
1µF
Si7135DP
10k
107k
107k
1.87M
NTHS0603
N02N1002J
BFB
NTC
FBG
BAT
OFB
IID IGATE CSP
CSN
BGATE
TMR
150µF
22µF
×5
GND BIAS
22.1k
232k
BSC027N04
10µF
LTC4000-1
CC
10k
22nF
BSC027N04
0.1µF
BAS140W
INTVCC
28.7k
10nF
IBMON
ITH
ITH
VFB
TG
VBIAS
BG
SW
BOOST
SENSE–
LTC3786
IIMON
FREQ
SS
RUN
PGOOD
INTVCC
PLLINMODE
1nF
100Ω
PA1494.362NL
3.3µH
SENSE+
100Ω
RST
ENC
CHRG
FLT
IFB
VM
IN
CLN
0.1µF
4.7µF
INTVCC
150µF
22µF
×4
2.5mΩ
Figure 30. 21V at 5A Boost Converter 5-Cell Li-Ion Battery Charger for High Impedance Input Sources
Such as Solar Cell, Fuel Cell or Wind Turbine Generator
10k
7.5k
100k
3.3mΩ
RNTC
1.87M
40001 F30
5-CELL
Li-Ion
BATTERY
PACK
TENERGY
SSIP PACK
30104
Si7135DP
10mΩ
VOUT
22V, 5A
LTC4000-1
Typical Applications
40001f
VIN
18V TO 72V
2.2µF
×2
0.1µF
15.8k
221k
FS
VCC
681Ω
SYNC GND FB OC
ITH
ISENSE
•
•
•
BAS516
1.5k
VOUT
PDS1040
VOUT
10nF
14.7k
100nF
VM
150k
10nF
IIMON IBMON
ENC
CHRG
FLT
RST
ITH
CC
100k
100µF
×3
CL
IN
22.1k
TMR
100nF
LTC4000-1
CLN
1µF
20mΩ
CX
IFB
NTC
BFB
FBG
OFB
BAT
BGATE
CSN
CSP
IGATE
GND BIAS
22.1k
IID
SiA923EDJ
Figure 31. 18V to 72VIN to 4.2V at 2.0A Isolated Flyback Single-Cell Li-Ion Battery Charger
with 2.9h Timer Termination and 0.22A Trickle Charge Current
13.6k
0.04Ω VCC
150pF
68Ω
BAS516
ISO1
PS2801-1-K
BAS516
3.01k
FDC2512
1µF
GATE
MMBTA42
VCC
LTC3805-5
75k
SSFLT
RUN
PDZ6.8B
6.8V
221k
TR1
PA1277NL
1µF
10k
115k
115k
309k
RNTC
309k
10nF
40001 F31
NTHS0603
N02N1002J
SINGLE-CELL
Li-Ion
BATTERY
PACK
SiA923EDJ
25mΩ
VSYS
4.4V, 2.5A
LTC4000-1
Typical Applications
40001f
37
LTC4000-1
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
40001f
38
LTC4000-1
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.033
(0.838)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ±.004
× 45°
(0.38 ±0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
9 10 11 12 13 14
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
40001f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC4000-1
Typical Application
5.6Ω
IHLP6767GZ
ER4R7M01
4.7µH
390pF
3.6Ω
B240A
SOLAR PANEL
INPUT <40V OPEN
CIRCUIT VOLTAGE
11.8V PEAK
POWER VOLTAGE
4mΩ
Q2
Q4
1800pF
B240A
Q5
0.01Ω
Q3
Si7135DP
LM234
V+
270µF
V–
0.22µF
0.01Ω
0.22µF
R
1.24k
3.3µF
×5
TG1
1k
SW1
1.24k
+
BG1 SENSE
–
SENSE
BG2
SW2
BOOST1
VOUT
15V, 5A
330µF
×2
22µF
×2
TG2
BOOST2
DFLS160
DFLS160
INTVCC
INTVCC
10µF
MODE/PLLIN
VIN
1µF
100k
LTC3789
VINSNS
PGOOD
309k
IOSENSE+
IOSENSE–
VOUTSNS
BZT52C5V6
121k
FREQ
EXTVCC
ILIM
RUN
154k
VFB
SS
ITH
SGND
10µF
PGND1
8.06k
0.01µF
10mΩ
14.7k
RST
CLN
IN
210k
ITH
100nF
CC
IID IGATE CSP
CSN
BGATE
Si7343DP
1µF
VM
BAT
OFB
LTC4000-1
16.2k
26.7k
IFB
8.66k
ENC
CHRG
FLT
Q2: SiR422DP
Q3: SiR496DP
Q4: SiR422DP
Q5: SiR496DP
FBG
118k
IIMON
IBMON
CL
TMR
10nF
10nF
CX
GND
BFB
NTC
BIAS
1.37M
0.1µF
18.2k
22.1k
1µF
4-CELL
LiFePO4
BATTERY
PACK
RNTC
10k
40001 F32
Figure 32. Solar Panel Input 6V to 36VIN to 14.4V at 4.5A Buck Boost Converter 4-Cell LiFePO4
Battery Charger with 2.9h Timer Termination and 0.22A Trickle Charge Current
NTHS0603
N02N1002J
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4000
High Voltage High Current Controller for Battery Charging and Power
Management
Similar to LTC4000-1 with Input Current Regulation
LTC3789
High Efficiency, Synchronous, 4 Switch Buck-Boost Controller
Improved LTC3780 with More Features
LT3845
High Voltage Synchronous Current Mode Step-Down Controller with
Adjustable Operating Frequency
For Medium/High Power, High Efficiency Supplies
LT3650
High Voltage 2A Monolithic Li-Ion Battery Charger
3mm × 3mm DFN-12 and MSOP-12 Packages
LT3651
High Voltage 4A Monolithic Li-Ion Battery Charger
4A Synchronous Version of LT3650 Family
LT3652/LT3652HV Power Tracking 2A Battery Chargers
Multi-Chemistry, Onboard Termination
LTC4009
High Efficiency, Multi-Chemistry Battery Charger
Low Cost Version of LTC4008, 4mm × 4mm QFN-20
LTC4012
High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control Similar to LTC4009 Adding PowerPath Control
LT3741
High Power, Constant Current, Constant Voltage, Step-Down Controller
Thermally Enhanced 4mm × 4mm QFN and 20-Pin TSSOP
40001f
40 Linear Technology Corporation
LT 0712 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012
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