Integrated, Step-Down Switching Regulator With Selectable Applications Configurations General Description The MAX38800 is a fully integrated, highly efficient switching regulator for applications operating from 6.5V to 14V input supplies that require up to 9A maximum load. This single-chip regulator provides compact high-efficiency power delivery for precision outputs that demand fast transient response. The device has different programmability options to enable a wide range of configurations. The programmable features include: internal/external reference voltage, output voltage set-point, switching frequency, overcurrent protection level (OCP), and soft-start timing. Discontinuous current mode (DCM) operation can be enabled using pinstrapping to improve light-load efficiency. The MAX38800 includes multiple protection and measurement features. Positive and negative cycle-bycycle OCP, short-circuit protection and overtemperature protection (OTP) ensure robust design. Input undervoltage and overvoltage lockout shut down the regulator to prevent damages when the input voltage is out of specification. Regulation is halted in case of an output overvoltage (OVP) event. A status pin indicates that the output voltage is within range and the output voltage is in regulation. The device has an analog output that can be configured to report output current or junction temperature. The device is available in a 19-bump (2.2mm x 2.8mm) WLCSP package that provides low thermal resistance and minimizes the printed circuit board area. Applications ●● ●● ●● ●● ●● Servers/µServers I/O and Chipset Supplies GPU Core Supply DDR Memory: VDDQ, VPP and VTT Point-of-Load (PoL) Applications Benefits and Features ●● High-Efficiency Solution • Up to 96% Peak • Up to 95.5% Full Load • Up to 94% Light-Load Efficiency at 1A with DCM Enabled ●● Flexible Design Allows Early PCB Definition • Footprint Compatible with MAX38801 (15A) and MAX38802/MAX38803 (25A) • Programmable Switching Frequency up to 1MHz • Programmable Soft-Start and STAT Delay Timings • Programmable Reference Voltage with External Input Option • Programmable Positive and Negative OCP Limit • Supports Current Sourcing and Sinking ●● Advanced Architecture, Protection and Reporting Guarantees Reliable Designs • Analog Current or Temperature Reporting • Differential Remote Sense with Open-Circuit Detection • Fast Transient Response with Quick-PWM™ Architecture • Percentage-Based Output Power Good and OVP • Open-Drain Status Indicator (STAT) Pin • Input Undervoltage and Overvoltage Lockout • Adaptive Dead-Time Control ●● Saves Board Space • Integrated Boost Switch • 19-Bump WLCSP (2.2mm x 2.8mm) Footprint • Operation Using Ceramic Input and Output Capacitors Basic Application Circuit VCC CVCC VDDH VDDH VCC MAX38800 CURRENT RATING (A) INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 9 6.5 to 14 0.6 to 5.5 Ordering Information appears at end of data sheet. Quick-PWM is a trademark of Maxim Integrated Products, Inc. 19-100047; Rev 0; 9/17 BST CIN CBST VOUT RSTAT LOUT VX Ramp Compensation RR ROE STAT SENSE+ OE SENSE- AGND C_SEL CR1 GND PGM RLAG R_SEL CR2 RFB1 CLAG CLEAD Lag Compensation MAX38800 RLEAD Lead Compensation RFB2 COUT MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Absolute Maximum Ratings VDDH to GND (Note 1)...........................................-0.3V to +23V VX to GND (DC).....................................................-0.3V to +23V VX to GND (AC) (Notes 1, 2)..................................-10V to +23V VDDH to VX (DC)....................................................-0.3V to +23V VDDH to VX (AC) (Notes 1, 2).................................-10V to +23V BST to GND (DC)................................................-0.3V to +25.5V BST to GND (AC) (Notes 1, 2)...............................-7V to +25.5V Operating Ratings Input Voltage (VDDH)................................................. 6.5V to 14V Bias Supply Voltage (VCC)................................... 1.71V to 1.89V Output Current (IOUT) .............................................................9A BST to VX Differential...........................................-0.3V to +2.5V VCC to AGND........................................................-0.3V to +2.5V OE, PGM, SENSE+, SENSE- to GND..................-0.3V to +2.5V STAT to AGND.........................................................-0.3V to +4V Junction Temperature (TJ)................................................+150°C Storage Temperature Range............................. -65°C to +150°C Peak Reflow Temperature Lead-Free.............................. +260°C Junction Temperature (TJ) ...................................0°C to +125°C Peak Output Current (IPK_MAX).............................................30A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information PACKAGE TYPE: 19 WLCSP PACKAGE CODE C192B2+1 Outline Number 21-0915 Land Pattern Number 90-0544 THERMAL RESISTANCE, FOUR-LAYER BOARD Junction to Ambient (θJA) 32°C/W (typ) (Note 3) Junction to Case (θJC) 1°C/W (max) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Note 1: Input HF capacitors placed not more than 60 mils away from the VDDH pin are required to keep inductive voltage spikes within Absolute Maximum Ratings limits. Note 2: AC is limited to 25ns. Note 3: Data taken using Maxim’s evaluation kit with no air flow and no heatsink. www.maximintegrated.com Maxim Integrated │ 2 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Electrical Characteristics (VCC = 1.8V ±5%, VDDH = 12V unless otherwise specified. Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 14 V 1.89 V SUPPLY VOLTAGES, SUPPLY CURRENT, TEMPERATURE RANGE 12V Supply Voltage Range VDDH Note 8 6.5 1.8V Supply Voltage Range VCC Note 8 1.71 VCC Supply Current ICC 1.8 CCM (Note 8) 35 DCM (Note 8) 25 Shutdown (Note 8) 32 196 mA µA VREF Programmable Reference Voltage VREF Tolerance (VREF_TOL) VREF Tolerance Temperature Coefficient (VREFT_COEFF) 0.6 See Table 3 (Note 9) T = 35°C (Note 4) VREF -0.5 0°C < TJ < 100°C (Note 4) External Reference Voltage (SENSE-) V 0.95 0.5 +0.5 % 0.0106 %/°C 1.1 V FEEDBACK LOOP RSENSE GAIN Gain 1.05 See Table 3 (Note 9) mV/A 2.1 SWITCHING FREQUENCY Low fSW Threshold Forced Minimum fSW fSW DCM enabled 30 kHz DCM enabled. The low fSW threshold has been crossed. 60 kHz INPUT PROTECTION Rising VDDH UVLO Threshold Falling VDDH UVLO Threshold Hysteresis Rising VDDH OVLO Threshold Falling VDDH OVLO Threshold Hysteresis VDDH UVLO (Note 8) VDDH OVLO (Note 8) Rising VCC UVLO Threshold Falling VCC UVLO Threshold VCC UVLO 5.8 6.2 6.5 V 5.2 5.5 5.9 V 700 14.2 14.8 15.4 13.8 14.3 14.8 500 (Note 8) Hysteresis www.maximintegrated.com mV 1.62 1.70 V 1.43 1.57 1.68 V 50 Rising VBST UVLO Threshold VBST UVLO (Note 8) V 1.46 Hysteresis Falling VBST UVLO Threshold mV mV 1.49 1.57 1.70 V 1.41 1.52 1.63 V 50 mV Maxim Integrated │ 3 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Electrical Characteristics (continued) (VCC = 1.8V ±5%, VDDH = 12V unless otherwise specified. Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 8.5 13 16 % 25 30 36 µs (Note 5) 5 9 12.5 % (Note 5) 3 6 9.5 % 25 30 36 µs OUTPUT VOLTAGE PROTECTION (OVP) Overvoltage-Protection Rising Threshold OVP (Note 5) OVP Deglitch Filter Time Power Good Protection Falling Power Good Protection Rising PWRGD Power Good Deglitch Filter OVERCURRENT PROTECTION (OCP) 6.6 Positive OCP Threshold (POCP) 8.5 10 Valley current (Note 9) Negative OCP Threshold (NOCP) A -6.9 -8.5 OCP A -10 POCP Threshold Tolerance Referenced to nominal value (Note 5) (Note 8) -20 +20 % NOCP Threshold Tolerance Referenced to nominal value (Note 5) (Note 8) -26 +26 % Hysteresis (Note 6) Referenced to inception value (Note 8) % 15 OVERTEMPERATURE PROTECTION (OTP) OTP Inception Threshold Hysteresis OTP Note 8 130 140 150 °C -25 -10 °C 0 125 °C -8 +8 °C 0 9 A -1.5 +1.5 A -5 +5 % TEMPERATURE REPORTING Temperature Reporting Range Temperature Reporting Tolerance TJ Note 8 CURRENT REPORTING Current Reporting Range Current Reporting Tolerance www.maximintegrated.com ILOAD From no load to full load (Note 8) Full load (Note 8) Maxim Integrated │ 4 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Electrical Characteristics (continued) (VCC = 1.8V ±5%, VDDH = 12V unless otherwise specified. Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OE PIN Input Range (Note 8) Rising Threshold VOE(H) Falling Threshold VOE(L) Hysteresis 1.89 V Full VCC supply range. Measured at OE Pin (Note 8) 0.98 0 1.09 1.3 V 0.44 0.66 0.80 V (Note 5) (Note 8) 0.35 0.44 0.61 V Deglitch Filter Time 375 UVLO < VCC < OVLO (Note 8) OE Pin Input Resistance ns 300 430 480 kΩ 185 300 500 µs STARTUP TIMING Enable Time from OE Rise to Start of Regulation tEN 1.5 Soft-Start Ramp Time tSS See Table 3 (Note 9) 3 ms 6 Dwell Time at VOUT (DCM Not Allowed) Timing to Charge Boost Capacitor tSETTLE 14 35 8 tBST µs µs STAT PIN Pullup Voltage Status Output Low VOLSTAT Time from VOUT Ramp Completion to STAT Pin Released Fault Clearing www.maximintegrated.com ISTAT = 4mA (Note 8) 0.4 ISTAT = 0.2mA, 0V < VCC < UVLO and 0V <VDDH < UVLO (Note 8) 0.67 ISTAT = 1.3mA, 0V < VCC < UVLO and 0V < VDDH < UVLO (Note 8) 0.76 VSTAT = 0.4V (Note 8) Current Sinking Capability Status Output High Leakage Current 3.6 VOHSTAT ISTAT tSTAT V 3 11 STAT pulled to 3.3V through 20kΩ (Note 8) STAT output low-to-high. See Table 3. (Note 9) Bad to good delay V mA 7 128 2000 2 µA µs ms Maxim Integrated │ 5 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Electrical Characteristics (continued) (VCC = 1.8V ±5%, VDDH = 12V unless otherwise specified. Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 820 pF -20 +20 % 20 pF -0.5 +0.5 % -1 +1 % 0.15 % -0.5 +0.5 % -3 +3 % PGM PIN Capacitor Range Three options C_SEL Capacitor Accuracy C_SEL External Capacitance Load and stray capacitance in addition to C_SEL SYSTEM SPECIFICATIONS (NOTE 7) Peak-to-Peak Output Ripple Voltage, DCM Disabled Peak-to-Peak Input Ripple Voltage VOUT-RIPL VIN-RIPL VDDH = 10.8V - 13.2V Line Regulation VDDH = 10.8V - 13.2V Load Regulation (Static) IOUT = 0 - IMAX VOUT Load Regulation (Dynamic) VDDH = 10.8V - 13.2V, IOUT Step 5.8A at 20A/µs, 1kHz to 1MHz repetition rate, 10% to 90% Duty Cycle Note 4: To calculate the total VREF tolerance over a temperature variation of ΔT: VREF(TOL_TOT) = VREF(TOL) + ∆T × VREF(T_COEFF) Note 5: Note 6: Note 7: Note 8: Note 9: Min/max limits are ≥ 4σ about the mean. The OCP hysteresis is for positive current OCP only, negative current OCP hysteresis is always 0. Tested using circuit of Reference Schematic with COUT = 15 x 22µF. VOUT = 1.05V. Not guaranteed; for reference only. Denotes specifications that apply over the temperature range of TJ = 0°C to 125°C. Otherwise, specifications are for TJ = 32°C. Denotes parameters that are programmable. www.maximintegrated.com Maxim Integrated │ 6 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Typical Operating Characteristics (VDDH = 12V, VCC = 1.8V, fSW Setting #6, 900kHz, COUT = 15 x 22µF, unless otherwise noted. LOUT = 680nH for VOUT ≥ 2.5V, LOUT = 200nH for VOUT ≤ 1.8V) Efficiency vs. Load Current (Light Load) 98% 96% 96% 94% 94% 92% 92% 90% 90% 88% 88% Efficiency (%) Efficiency Efficiency vs. Load Current (Full Scale) 98% 86% 84% 82% 80% 86% 84% 82% 80% 78% VOUT = 5V 76% VOUT = 2.5V 76% VOUT = 1.8V 74% VOUT = 3.3V 74% VOUT = 1.05V 72% 70% 1 2 VOUT = 3.3V VOUT = 3.3V VOUT = 2.5V VOUT = 2.5V VOUT = 1.8V VOUT = 1.8V VOUT = 1.05V VOUT = 1.05V VOUT = 0.6V VOUT = 0.6V 72% VOUT = 0.6V 0 VOUT = 5V VOUT = 5V 78% 3 4 5 6 7 8 70% 9 0.1 1 Load Current (A) Load Current (A) Power Dissipation vs. Load Current (Full Scale) Power Dissipation vs. Load Current (Light Load) 2.0 1.0 1.8 VOUT = 3.3V VOUT = 1.8V 1.4 VOUT = 1.05V VOUT = 0.6V 1.2 1.0 0.8 0.2 0.1 3 4 5 6 7 8 VOUT = 0.6V 0.4 0.2 2 VOUT = 1.05V 0.5 0.3 1 VOUT = 1.8V 0.6 0.4 0 VOUT = 2.5V 0.7 0.6 0.0 VOUT = 3.3V 0.8 VOUT = 2.5V Power Loss (W) Power Loss (W) 1.6 VOUT = 5V 0.9 VOUT = 5V 0.0 0.1 9 1 Load Current (A) Load Current (A) Load Regulation Safe Operating Area (SOA) 0.10% 9 0.08% 8 0.06% Load Regulation (%) 10 IOUT (9A) 7 6 5 = 25°C 25ºC //250LFM / No Heatsink TTA 250 LFM / No Heatsink A = TTA 250 LFM / No Heatsink = 25°C 25ºC //0LFM / No Heatsink A = TTA 250 LFM / No Heatsink A = = 25°C 55ºC //250LFM / No Heatsink TA = 25°C / 250 LFM / No Heatsink 4 3 TA = 55ºC / 0LFM / No Heatsink 2 VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.05V 0.04% VOUT = 0.6V 0.02% 0.00% -0.02% -0.04% -0.06% -0.08% 1 0 VOUT = 5V 0.5 1 1.5 2 2.5 3 VOUT (V) www.maximintegrated.com 3.5 4 4.5 5 5.5 -0.10% 0 1 2 3 4 5 6 7 8 9 Load Current (A) Maxim Integrated │ 7 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Typical Operating Characteristics (continued) (VDDH = 12V, VCC = 1.8V, Circuit of Basic Application Circuit, VOUT = 1.05V, R_SEL = 46.4kΩ, RFB1 = 2.1kΩ, RFB2 = 2.8kΩ. No heatsink, ILOAD = 12A, unless otherwise noted.) Startup with OE, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div 1ms/div C: STAT, 500mV/div D: OE, 500mV/div Startup with VDDH, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div 1ms/div C: STAT, 500mV/div D: VDDH, 2V/div Startup with VCC, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div www.maximintegrated.com 1ms/div C: STAT, 500mV/div D: VCC, 500mV/div Shutdown with OE, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div 10μs/div C: STAT, 500mV/div D: OE, 500mV/div Shutdown with VDDH, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div 10μs/div C: STAT, 500mV/div D: VDDH, 2V/div Shutdown with VCC, Internal VREF A: VOUT, 200mV/div B: Vx, 5V/div 10μs/div C: STAT, 500mV/div D: VCC, 500mV/div Maxim Integrated │ 8 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Typical Operating Characteristics (continued) (VDDH = 12V, VCC = 1.8V, Circuit of Figure 6, VOUT = 2.5V, R_SEL = 9.09kΩ, RFB1 = 2.1kΩ, RFB2 = 2.8kΩ, External VREF = 0.6V. No heatsink, unless otherwise noted.) Startup with OE, External VREF A: VOUT, 200mV/div B: STAT, 500mV/div 1ms/div C: SENSE-, 200mV/div D: OE, 500mV/div Startup with VDDH, External VREF A: VOUT, 200mV/div B: STAT, 500mV/div 1ms/div C: SENSE-, 200mV/div D: VDDH, 2V/div Transient Response CCM A: VOUT, 50mV/div B: Vx, 10V/div www.maximintegrated.com 100μs/div C: ILOAD, 3.3A/div External VREF Tracking A: VOUT, 50mV/div B: STAT, 500mV/div 2ms/div C: SENSE-, 50mV/div Startup with VCC, External VREF A: VOUT, 200mV/div B: STAT, 500mV/div 1ms/div C: SENSE-, 200mV/div D: VCC, 500mV/div Load-Transient Response CCM – Zoom In A: VOUT, 20mV/div B: Vx, 10V/div 10μs/div C: ILOAD, 3.3A/div Maxim Integrated │ 9 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Typical Operating Characteristics (continued) (VDDH = 12V, Circuit of Basic Application Circuit, VOUT = 1.05V, COUT = 15 x 22µF, L = 200nH, fSW Setting #6, Load Step = 6A, SR = 20A/µs.) Unload-Transient Response CCM – Zoom In A: VOUT, 20mV/div B: Vx, 10V/div 10μs/div C: ILOAD, 3.3A/div Load-Transient Response DCM – Zoom In A: VOUT, 20mV/div B: Vx, 10V/div 10μs/div C: ILOAD, 3.3A/div Positive Overcurrent Protection A: VOUT, 500mV/div B: STAT, 1V/div www.maximintegrated.com 10μs/div C: Vx, 10V/div D: IL, 5A/div Transient Response DCM A: VOUT, 50mV/div B: Vx, 10V/div 100μs/div C: ILOAD, 3.3A/div Unload-Transient Response DCM – Zoom In A: VOUT, 20mV/div B: Vx, 10V/div 10μs/div C: ILOAD, 3.3A/div Negative Overcurrent Protection A: VOUT, 500mV/div B: STAT, 1V/div 10μs/div C: Vx, 10V/div D: IL, 10A/div Maxim Integrated │ 10 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Pin Configurations 4 3 2 1 1 2 3 4 E E GND GND GND GND GND GND GND GND D D VX VX VX VX VX VX VX VX C C BST VDDH VDDH VDDH VDDH VDDH VDDH BST B B VCC SENSE+ OE PGM PGM SENSE+ OE VCC A A STAT AGND SENSE- SENSE- (Top View) AGND STAT (Bottom View) 19 WLCSP www.maximintegrated.com Maxim Integrated │ 11 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Pin Description PIN NAME A1 SENSE- Negative Remote Sense/External Reference Input. Connect the SENSE- pin to ground at the load with a Kelvin connection to use the internal voltage reference, or connect the pin to an external reference voltage, as shown in Figure 6. A2 AGND Analog/signal ground. Connect to ground plane following the recommendations mentioned in the Printed Circuit Board Layout section. A4 STAT Open-Drain Status Output. This pin is pulled low to indicate a fault or output Undervoltage/ Overvoltage events. B1 PGM Programming Input/Telemetry Output. Connect PGM to analog ground using a programming resistor and capacitor. The resistance and capacitance values are measured at startup to determine the desired regulator settings (see Table 3). See the Current/Temperature Reporting and Programming Options sections for more information. B2 SENSE+ B3 OE Output Enable Input. Connect to enable signal through a 20kΩ resistor. When OE is low the VX node is high impedance. Toggle OE to clear the fault-protection latch. B4 VCC Supply Voltage Input for the Regulator’s Analog, Digital and Gate Drive Circuits. Connect VCC to 1.8V and closely bypass the pin to power ground with a 1µF or greater ceramic capacitor. C1–C3 VDDH C4 BST Bootstrap supply input. Connect a 0.47µF ceramic capacitor in close proximity to the IC between BST and VX, as specified in Table 4 and the Printed Circuit Board Layout section. D1–D4 VX Switching Node. Connect to the switching node of the power inductor. E1–E4 GND www.maximintegrated.com FUNCTION Positive Remote Sense Input. Connect SENSE+ to VOUT at the load using a Kelvin connection. A resistive voltage-divider can be inserted between the output and SENSE+ to regulate the output above the reference voltage. Power Input Voltage. Connect VDDH to the input power supply source. High-frequency ceramic decoupling capacitors must be placed in close proximity to the pin. See Table 4 for decoupling recommendations. Power ground. Connect to the return path of the output load. Maxim Integrated │ 12 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Functional (or Block) Diagram PGM ILIM (SOURCE) OE DCM tOFF(MIN) VDDH ON-TIME COMPUTE VCC BST ILIM (SINK) OPERATION PROGRAM VX 1-SHOT S tON TRIG VDDH TRIG Q Q R Q 1-SHOT REF/ SOFT-START VX VALLEY CURRENT SENSE REF/ EXT GAIN ERROR COMP CCV VCC 1X S SENSE- Q R SENSE+ GND Zero Crossing (SENSE+) + 13% AGND STAT AND FAULT PROTECTION (SENSE+) - 9% STAT UVLO Detection 150C FLAG www.maximintegrated.com VDDH VX BST DCM ILIM (SINK) ILIM (SOURCE) Maxim Integrated │ 13 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Detailed Description Control Architecture The MAX38800 step-down regulator is ideal for low duty cycle. Maxim’s proprietary Quick-PWM pulse-width modulator in the MAX38800 is a pseudo-fixed frequency, constant on-time, current-mode regulator with voltage feed-forward (Block Diagram). The architecture is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. This approach circumvents the poor load-transient timing problems of fixed frequency, current mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time PFM control schemes regardless of input voltage. Traditional constant on-time architectures require an output capacitor with a specified minimum ESR to ensure stable operation. This restriction does not apply to the MAX38800, because the inductor valley current is added to the feedback signal using a proprietary current sense method, which improves stability. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage (Equation 1). Another oneshot sets a minimum off-time (100ns, typ). Under normal operating conditions, the on-time one-shot is triggered if the sum of the feedback voltage and the valley current sense signal falls below the control voltage, and the minimum off-time one-shot has timed out. The tON pulse width is clamped to a maximum of 2.5µs. Equation 1 t ON = VX AVE f SW × VDDH Voltage Regulator Enable and Turn-On Sequencing The startup sequence is shown in Figure 1. Once the OE pin rises above the VOE(H) threshold, the control circuits wait for a 300µs tEN time to allow the bias circuits, analog blocks and other circuits to settle to their proper states before beginning the regulation. The OE pin has a voltage rating of 1.8V. For control signal voltages higher than 1.8V, a resistor-divider network must be used to drive the OE pin. In addition, the impedance of the OE pin is reduced when the VCC is below UVLO. To prevent any damage to the part due to lowering the impedance, a resistor is used to limit the current. For 1.8V control signals, this resistor has a value of 20kΩ and it is placed in series with OE pin. For higher drive voltages to OE that require a resistive voltage divider, choose 20kΩ for the bottom resistor to ground. The top resistor is given by Equation 2. Use closest higher resistor value available. Equation 2 V = 20kΩ × SIG − 1 R TOP 1.8V Output enable delay timing can be added using an RC network connected between control signal and OE pin. R-C delay networks are designed based on desired turn on/off timings and the VOE(H)/VOE(L) thresholds. The OE pin has nominal input impedance, which should be included in calculations for the divider network (see the Electrical Characteristics table for nominal impedance). When the system pulls OE low, the MAX38800 enters low-power shutdown mode. STAT is pulled low immediately. The device discharges the inductor by keeping the low-side FET enabled until the current reaches zero. Under these conditions, both power FETs are in highimpedance and the regulator enters shutdown. Soft-Start Control Once the OE reaches its threshold and the tEN has elapsed, the regulator performs the bootstrap capacitor charging sequence. After bootstrap capacitor is fully charged, the internal reference voltage starts ramping to the target voltage with the appropriate soft-start time (tSS). Both soft-start timing, and target voltage can be programmed (see the Programming Options section and Table 3). OE VOUT Prebias VOUT Internal VDES STAT tEN tBST tSTAT tSS Figure 1. Startup Timing www.maximintegrated.com Maxim Integrated │ 14 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations If the regulator is enabled with a prebiased output voltage, the system cannot regulate until the reference voltage ramps above the SENSE+ node voltage. Upon reaching the SENSE+ voltage, the regulator performs the CBST charging sequence and starts normal operation. If, at the end of tSS, the SENSE+ pin voltage is still higher than the internal reference, continuous conduction mode (CCM) operation is forced for a short period of time (tSETTLE) to discharge the output to the desired voltage. After this period, discontinuous conduction mode (DCM) is allowed, if selected, and the OVP/UVP circuitry becomes active. Remote Output-Voltage Sensing Remote output-voltage sensing is implemented to improve output-voltage regulation accuracy at the load. This technique reduces errors due to voltage drops in the plane impedance between the load and the MAX38800, particularly in cases where the load is placed away from the MAX38800. Remote output voltage sensing is implemented by using the SENSE- node as a reference for the internal voltage reference VREF. Switching Operation Modes The MAX38800 supports both CCM and DCM. The mode of operation can be programmed as indicated in the Programming Options section and Table 3. If DCM is enabled, the MAX38800 transitions seamlessly to DCM at light loads to improve efficiency. Once in DCM, the switching frequency decreases as load decreases until a minimum frequency of 30kHz is reached. The purpose of this minimum switching frequency limitation is to prevent operation in the audible frequency range to reduce audible noise. If the load is such that no tON pulse is generated for ~33µs (1/30kHz) since the last pulse was issued, the low-side FET is turned on until the error comparator commutates, and a tON pulse is issued. Once this minimum frequency mode is entered, the IC operates with a minimum switching frequency of 60kHz, to provide proper hysteresis and prevent the IC from moving in and out of this mode. Protection and Status Features Output-Voltage Protection The SENSE+ pin is continuously monitored for both undervoltage and overvoltage conditions. If the output voltage falls below the PWRGD threshold (9% of programmed output voltage) for more than 30µs (typ), the STAT pin is driven low while the MAX38800 continues to operate, attempting to maintain regulation. If the output voltage rises above the overvoltage protection (OVP) threshold (13% of programmed output voltage) for more than 30µs (typ), the STAT pin is driven low and the MAX38800 latches off (high-side and low-side FETs turn off). Toggle OE or cycling VCC supply is required to clear fault conditions. Current Limiting The MAX38800 has a current limit that can be programmed using the appropriate R_SEL value (see Table 3). The overcurrent protection (OCP) monitors and limits the low-side FET current on a cycle-by-cycle basis. If the minimum instantaneous “valley” low-side switch current level exceeds the OCP (source) level, the IC delays the next on-time pulse until the current falls below the threshold level (Figure 2). Since the regulator responds to the inductor valley current, the DC current delivered during positive (source) current limit is the programmed valley current (IOCP - Hysteresis) plus half of the inductor ripple. During the current limit event (source), the output voltage drops and if the voltage reaches the PWRGD threshold, the STAT pin is driven low. The MAX38800 also has a negative OCP limit (Sink). When this threshold is reached, the IC issues an ontime pulse to limit the negative current. This on-time pulse is issued regardless of the error comparator state. Therefore, it is possible to cause an OVP event if the negative load exceeds the negative current limit. IOCP(AVG) IOCP IOCP2 IOCP(AVG) = IOCP2 + I tON 1 (VIN - VOUT) x 2 LOUT where, IOCP2 = IOCP - Hysteresis Figure 2. Inductor Current During Current Limit Event www.maximintegrated.com Maxim Integrated │ 15 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations UVLO and OVLO Protection The regulator monitors VDDH with both undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits. UVLO protection is also present on BST and VCC supplies. When any of the supply voltages is below the UVLO threshold or VDDH is above the OVLO threshold, the regulator stops switching, and the STAT pin is driven low (refer to Electrical Characteristics table for UVLO and OVLO levels). Overtemperature Protection If the die temperature exceeds the overtemperature threshold during operation, the MAX38800 stops regulation and the STAT pin is driven low. Regulation starts again once the die temperature falls below the new overtemperature threshold (overtemperature threshold–hysteresis) value. The STAT pin eventually goes high again once the output voltage reaches the expected value. Regulator Status The regulator status (STAT) signal provides an opendrain output (4V ABS MAX) that indicates whether the MAX38800 is functioning properly. An external pullup resistor is required. After the startup ramp is completed (tSTAT), if the output voltage is within the PWRGD/OVP regulation window the STAT pin goes high impedance. The STAT pin is driven low when one or more of the following conditions exist: ●● OE is low ●● VDDH or VCC are not present or below/above the respective UVLO/OVLO thresholds. ●● A PWRGD fault is present (see the Output-Voltage Protection section). ●● The SENSE- or SENSE+ pin is left unconnected at startup. ●● The die temperature is above the maximum allowed temperature. ●● The OVP circuit has detected that the output voltage is above the tolerance limit. ●● UVLO is detected on bootstrap supply (BST-VX), indicating a possible short or open bootstrap capacitor. Current/Temperature Reporting During regulation, an analog voltage is produced on the PGM pin that represents either average output current or chip temperature (see Table 3 for proper setting). The PGM pin has an output-voltage range of 0.5V to 1V. The PGM output is designed to drive the R_SEL/C_SEL network with an additional 20pF external load (including parasitics), which allows this node to be connected to external circuitry such as voltage buffer or ADC. The conversion equations for temperature and current reporting are shown in Equation 3 and Equation 4. Equation 3 TREPORTED = (VPGM − TrOFFSET ) × TrSLOPE TrOFFSET = 0.579V TrSLOPE = 500 °C V Equation 4 IREPORTED = (VPGM − IrOFFSET ) × IrSLOPE IrOFFSET = 0.496V IrSLOPE = 67.4 A V Table 1. Summary of Fault Actions REGULATOR RESPONSE STAT Continue Operation LOW VOUT < (1 - 9%) VOUTNOM Shutdown and Latchoff LOW VOUT > (1 + 13%) VOUTNOM Overtemperature Protection (OTP) Shutdown LOW TJ > 140°C Overcurrent Protection (OCP) Clamping VOUT DROP, LOW Boost Undervoltage Shutdown LOW (BST - VX) < 1.52V VDDH Supply Shutdown LOW VDDH < 5.5V or VDDH > 14.8V VCC Supply Shutdown LOW VCC < 1.57V Do Not Start LOW Open Sense Lines FAULT TYPE Power Good (PWRGD) Overvoltage Protection (OVP) SENSE-/SENSE+ Disconnected www.maximintegrated.com DESCRIPTION Valley current higher than selected limit Maxim Integrated │ 16 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Programming Options By selecting the appropriate values of resistor and capacitor, the desired set of parameters (scenario) can be programmed as shown in Table 3. The MAX38800 allows programming of several key parameters to allow optimization for specific applications. The parameters that are programmable are shown in Table 2. A resistor and capacitor connected from the programming pin to ground select a set of parameters. C_SEL selects the fSW setting. There are six options available (from #1 to #6), indicating six different nominal switching frequencies, from lowest to highest. Since the actual value of fSW also depends on VOUT, refer to Figure 4 to select the proper fSW setting for a specific application. Table 2. Programmable Options PARAMETER DESCRIPTION VREF Selects internal or external voltage reference. For internal VREF two values are available. Soft-Start Time The time required to ramp the reference voltage to its final value. OCP Inception The valley current at which the overcurrent protection is tripped (see the Current Limiting section). Operation Modes Selects whether DCM is allowed. If allowed the IC transitions to DCM mode for light loads Reporting Selects the parameter reported using the analog output voltage on the PGM pin during regulation. RSENSE Gain Selects the sense-loop gain. By changing this value, the operation and components selection can be optimized. fSW Switching frequency setting. tSTAT Time delay between the completion of the soft-start ramp and the STAT pin output is valid. VDDH VCC CVCC CIN VDDH VCC CBST MAX38800 VOUT BST RSTAT LOUT VX Ramp Compensation RR SENSE+ OE SENSE- AGND C_SEL CR1 GND PGM RLAG R_SEL CR2 RFB1 CLAG Lag Compensation ROE STAT CLEAD RLEAD Lead Compensation RFB2 COUT Figure 3. Typical Application Circuit www.maximintegrated.com Maxim Integrated │ 17 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Table 3. Configuration Table R_SEL (kΩ) VREF (V) SOFTSTART TIME (tSS) (ms) 1.78 VALLEY OCP OPERATION REPORTING INCEPTION MODES (CURRENT/TEMP) (A) 6 2.67 0.95 4.02 6.04 3 9.09 Ext. 13.3 1.5 20 6.6 CCM 8.5 CCM/DCM 6.6 CCM 8.5 CCM/DCM 6.6 CCM 46.4 0.6 6.6 200pF 820pF fSW #4 fSW #5 fSW #6 2000 1.5 fSW #1 fSW #2 fSW #3 128 Temp CCM/DCM 107 Ext. 0pF CCM 6 71.5 162 2.1 tSTAT (µs) C_SEL CCM/DCM 10 30.9 Current fSW SETTING RSENSE (GAIN) (mΩ) 8.5 CCM Current 1.05 Temp 2.1 900 NOMINAL fsw (kHz) 800 700 600 500 400 300 0.5 1 1.5 2 fsw #1#1 fSWSETTING = SETTING fsw #2#2 fSWSETTING = SETTING fsw fSWSETTING = SETTING#3#3 fSWSETTING = SETTING fsw #4#4 fSWSETTING = SETTING fsw #5#5 fSWSETTING = SETTING#6#6 fsw 2.5 3 3.5 4 4.5 5 VOUT (V) Figure 4. Nominal Switching Frequency vs. VOUT and fSW Setting www.maximintegrated.com Maxim Integrated │ 18 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Setting the Output Voltage RFB2 = Bottom divider resistor The output voltage of MAX38800 is set by selecting a reference voltage and using an appropriate resistive voltage-divider, as shown in Equation 5. RPAR = Desired parallel resistance of RFB1 and RFB2 VOUT = Output voltage VREF = Reference voltage The reference voltage is selected using R_SEL (see Table 3) and can be either internal or external (refer to Operation with External VREF section for more details). To improve the DC output-voltage accuracy, use the highest VREF value available and suitable for the application. For instance, use VREF = 0.6V for 0.6V ≤ VOUT < 0.95V and VREF = 0.95V for 0.95V ≤ VOUT < 5.5V. The Effect of Resistor Selection on DC Output Voltage Accuracy RFB1 and RFB2 set the output voltage as described in Equation 5. The tolerance of these resistors affects the accuracy of the programmed output voltage. Equation 7 To optimize the common mode rejection of the error amplifier, choose the resistive voltage-dividers so that their parallel resistance is as close as possible to 2kΩ (Equation 6). Equation 5 Equation 6 ε RVOUT = 2ε R VOUT − VREF 1 − εR VOUT Figure 5 shows the effect of 1% tolerance resistors over a range of output voltages. To ensure accuracy over temperature, the temperature coefficients must also be included in the error calculation (i.e., for 25ppm/°C resistors over a 50°C excursion, add 0.125% to the 25°C tolerance). R VOUT = VREF × 1 + FB1 R FB2 R PAR R = FB1 VOUT × VREF R PAR R= FB2 R FB1 × − R R PAR FB1 The error due to the voltage-feedback resistors’ tolerance, RFB1 and RFB2 should be added to the output voltage tolerance due to the IC’s VREF tolerance listed in the Electrical Characteristics table. Equation 8 where: R VOUT = VREF × 1 + FB1 R FB2 RFB1 = Top divider resistor 1.8% 1.6% 1.4% ERROR (%) 1.2% 1.0% 0.8% VREF = 0.6V 0.6% VREF = 0.95V 0.4% 0.2% 0% 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOUT (V) Figure 5. Contribution of 1% Tolerance Resistors on VOUT Error www.maximintegrated.com Maxim Integrated │ 19 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Voltage Margining Typical values for the filter components are: Voltage margining can be implemented by changing the effective feedback-divider ratio. FET switches can be used to introduce or remove parallel resistors to RFB2, to increase or decrease the output voltage respectively. To avoid triggering OVP or UVP faults, the circuits used to introduce resistive-divider changes should have switching time constants greater than the response time of the MAX38800. ●● RF = 2.2kΩ ●● CF = 0.22µF When changing the external reference voltage during normal operation (after the part has powered up, and reached regulation level), the regulator must be able to follow the reference-voltage change fast enough as to avoid OVP and PWRGD faults. Please make sure that reference-voltage change timing from the initial to the final value does not exceed 1/(2×BW), where BW is the bandwidth of the regulator in Hertz (Hz). Operation with External VREF When using an external reference, adopt the configuration shown in Figure 6. The MAX38800 employs a specialized soft-start sequence. Once OE is asserted, the regulator briefly discharges the SENSE- node and releases it as regulation begins. The resulting soft-start ramp timing is determined by the external low-pass filter time constant. The external filter time constant needs to be lower than tSS/3 to avoid premature assertion of STAT pin while the output voltage is still ramping. Control Loop The MAX38800 uses quick PWM architecture with the current-sense signal added to feedback. Hence, without additional compensation, the voltage-loop gain consists of the following terms: The external reference voltage can be applied prior to enabling the regulator, or ramped up right after enable is asserted. In both cases, the low-pass filtered reference voltage at SENSE- pin must reach its final value within tSS. VCC ●● The IC’s current-mode control scheme has an effective transconductance gain of 1/RSENSE(GAIN). See Table 3 for correct RSENSE(GAIN) values. ●● The output capacitors contribute an impedance gain of 1/(2 × π × COUT × f). ●● The feedback divider contributes an attenuation of KDIV = RFB2/(RFB1 + RFB2). VDDH CVCC CIN VDDH VCC MAX38800 CBST VOUT BST RSTAT LOUT VX ROE STAT SENSE+ OE SENSE- AGND GND PGM RFB1 RF CF VREF RFB2 COUT Kelvin Connection to Load C_SEL R_SEL Figure 6. Electrical Connections to Use the External Voltage Reference Feature www.maximintegrated.com Maxim Integrated │ 20 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Thus, when the ramp injection components (RR, CR1, CR2), lead compensation components (CLEAD, RLEAD) and lag compensation components (RLAG, CLAG) are not used, the approximate loop gain and bandwidth (BW) are given by the following equations. Equation 9 Loop_Gain(f ) = BW = K DIV 2 × π × R SENSE(GAIN) × C OUT × f The actual voltage deviation (VOUT_ERROR) is given by the largest of the values calculated using Equation 10a and Equation 10b. Equation 10 K DIV a) = I STEP × R GAIN_EFF VOUT_ERROR 1 b) VOUT_ERROR ≈ 2 × π × R SENSE(GAIN) × C OUT or BW = Equation 10a). If the load step applied exceeds the slew rate capability of the inductor current, the voltage deviation (VOUT_ERROR) is solely determined by output filter values (See Equation 10a). 2 × π × R GAIN_EFF × C OUT where RGAIN_EFF = RSENSE(GAIN)/KDIV For stability, COUT should be chosen so that BW < fSW/3. Designing with no loop compensation can result in fairly large COUT; compensation schemes such as lead, lag and ramp injection can be used to allow COUT reduction. These compensations impact the transient performance as they change the BW of the system. This should be included in design analysis. Integrator (I2 × L) 2 × VOUT × C OUT After a transient event, VOUT returns to the nominal value with a 20µs time constant, due to the integrator circuit. A first order average small-signal model of the regulator is shown in Figure 7. VEQ is an ideal voltage source equal to VOUT, REQ (RGAIN_EFF) is an emulated lossless resistance created by the control loop action and LEQ (tREC × RGAIN_EFF) is an emulated inductance. Note that LEQ is not the same as the actual LOUT inductor which has been absorbed into the model. COUT is the actual output capacitance. The IC has an integrator included in its error amplifier to improve load regulation. The integrator only adds gain at low frequencies, so it does not affect the loop BW; therefore, it was not considered in previous equations. With integrator, the loop gain from Equation 9 is multiplied by a factor of (1/tREC + s)/s LEQ REQ where tREC is 20µs. Step Response RGAIN_EFF determines the small-signal transient response of the regulator. When a load step is applied that does not exceed the slew rate capability of the inductor current, the regulator responds linearly and VOUT temporarily changes by the amount of VOUT_ERROR (see www.maximintegrated.com VEQ COUT Figure 7. Averaged Small-Signal Equivalent Circuit of Regulator Maxim Integrated │ 21 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Lag Compensation In cases where the response is faster than desired, the lag compensation network (RLAG, CLAG) can be used to decrease the BW. This has the effect of lowering the gain contribution of the feedback network at higher frequencies, by effectively placing RLAG in parallel with RFB2. For the lag network to be effective and to achieve optimal phase margin, the zero at 1/ (2 × π × RLAG × CLAG) should be placed at least a decade below the crossover frequency (BW/10). With lag, KDIV near the crossover frequency becomes Equation 11. Equation 11 K DIV _LAG = For the lead network to be effective and to achieve optimal phase margin, the zero at 1/(2 × π × RLEAD × CLEAD) should be placed below the crossover frequency (BW/10 < fZ < BW). With lead compensation, KDIV near the crossover frequency becomes Equation 13. Equation 13 K DIV _LEAD = (R FB2 R LAG ) (R FB1 + R FB2 R LAG ) R GAIN_EFF = R FB2 R R ( FB1 LEAD + R FB2 ) R GAIN_EFF = R GAIN K DIV _LAG Lag compensation increases RGAIN_EFF and VOUT_ ERROR while decreasing BW. An increase in VOUT_ ERROR can also result in higher overshoot at startup especially when the system recovers after hitting OCP. To avoid this, make sure that Equation 12 is satisfied. Equation 12 C LAG < be used to increase the bandwidth. This has the effect of increasing the gain contribution of the feedback network at higher frequencies by effectively placing RLEAD in parallel with RFB1. VOUT × C OUT I OCP × (R LAG + R FB1 R FB2 ) × 3 Lead Compensation In cases where the response is slower than desired, the lead compensation network (RLEAD, CLEAD) can R GAIN K DIV _LEAD Lead compensation decreases RGAIN_EFF and VOUT_ ERROR while increasing BW accordingly. External Ramp The ramp compensation stabilizes the converter if the ESR of the output capacitor bank is low. The ramp is added to the internal current-sense signal at the error comparator inputs, which improves the signal-to-noise ratio and reduces the off-time jitter. The amplitude of the external ramp is determined by RR and CR2 (see Figure 8). A voltage signal, which approximates the inductor current, appears across CR2 and it is injected to the feedback node through CR1. VOUT LOUT VX RR GAIN VALLEY CURRENT CONSTRUCTION VREF CR2 RFB1 1X CCV CR1 SENSE+ ON-TIME GENERATOR COUT ERROR COMP CONTROL LOOP RFB2 RAMP COMPENSATION NETWORK Figure 8. Ramp Compensation Diagram www.maximintegrated.com Maxim Integrated │ 22 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Values of ramp compensation network are selected as follows: 1) 2) 3) CR1 is chosen to maximize the coupling of the ramp signal on the feedback node: CR1 × RFB1||RFB2||RLEAD||RLAG ≈ 10 × tSW CR2 is chosen such that the ramp signal is unaffected by the value of CR1: CR2 ≈ 10 × CR1. Like lag compensation, ramp injection increases RGAIN_ EFF and VOUT_ERR. Inductor Selection The inductor value is selected based on the switching frequency and the percentage ratio of the inductor ripple to the peak load current. Equation 18 RR is chosen to achieve the desired ramp injection V (VIN − VOUT ) signal. Use Equation 14 to calculate proper = L × OUT f I LIR VIN × × RR value. SW LOAD(MAX) The approximate amplitude of the external ramp at the SENSE+ pin is given by Equation 14. Equation 14 VRAMP_EXT = VOUT × (VIN − VOUT ) (VIN × R R × C R2 × f SW ) The sensed inductor current ramp at the comparator input is given in Equation 15. Equation 15 VRAMP_IND = R GAIN × VOUT × (VIN − VOUT ) (VIN × L OUT × f SW ) where RGAIN is the internal current-sense gain (see the Electrical Characteristics table). The high-frequency gain from SENSE+ to the comparator input is unity. Therefore, with external ramp, the comparator sees an effective ramp given in Equation 16. where: LIR = Inductor current ratio ILOAD(MAX) = Peak load current A lower LIR results in lower RMS losses in passive and active components, which improves the regulator efficiency. A higher LIR results in faster inductor current slew rate, better transient performance and lower inductor value/ size. Optimal inductor selection is performed by evaluating these trade-offs according to design requirements. The inductor must have a saturation current higher than the peak current during an OCP event. The highest peak current is reached when a hard VOUT short circuit is applied during operation (See Equation 19). In addition, the application circuit design must ensure that the peak current never exceeds the maximum operating current (IPK) listed in the Operating Ratings section. Equation 19 Equation 16 I SAT > IPK _MAX = I OCP + V= RAMP_EFF VRAMP_IND + VRAMP_EXT =VOUT × (VIN − VOUT ) L OUT × R GAIN + (R R × C R2 ) (VIN × L OUT × f SW ) For best results, it is recommended that VRAMP_EFF be at least 15mV. The effective RGAIN with external ramp is given in Equation 17. Equation 17 R GAIN_EFF = R GAIN + L OUT (R R × C R2 ) The ramp injection capacitors effectively bypass the divider near the cross-over frequency, so in this case KDIV is approximately 1 and drops out of the loop gain equation. www.maximintegrated.com VOUT L × f SW where: ISAT = Inductor saturation current IOCP = Overcurrent protection threshold (see Table 3). Output Capacitor Selection Output capacitor selection is based on output ripple and load transient requirements. Low ESR capacitors (MLCCs) are recommended to minimize ripple. The output ripple is affected by three components: a resistive component due to effective ESR of the output capacitor bank, an inductive component due to the parasitic inductance of the capacitor package (ESL) and capacitive component based on the total COUT. See Equation 20 for an approximate expression of the output-voltage ripple. Maxim Integrated │ 23 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Input Capacitor Selection Equation 20 V I OUTRIPL = ESR(I OUTRIPL ) + ESL IN + VPP L 8 f C × × SW OUT OUT where: ESR = Equivalent series resistance at the output IOUTRIPL = Peak-to-peak inductor current ripple ESL = High-frequency equivalent series inductance at output VIN = Input voltage LOUT = Output inductance fSW = Switching frequency COUT = Output capacitance Low ESR MLCC capacitors minimize the voltage drop due to fast load transients. Follow Equation 9 and the description in the Control Loop section to properly size the output capacitor bank. In addition to output-voltage ripple and transient requirements for determining the output capacitance, ripple-current rating and power dissipation of the output capacitors should also be considered (see Equation 21 and Equation 22). Equation 21 Input capacitors are designed to filter the pulsed current drawn by the switching regulator when the high-side FET is conducting. Filtering is primarily accomplished by the bulk input capacitors, while the high-frequency capacitors are used to minimize the parasitic inductance between the input supply and the voltage regulator. This arrangement minimizes the voltage transients during the commutations of high-side and low-side MOSFETs. For effective input decoupling, it is critical that the high frequency decoupling is placed in close proximity to the MAX38800 VDDH and GND pins, and on the same side of the PCB board as the MAX38800. Refer to Table 4 for minimum input decoupling recommendations. It is also recommended to keep the input ripple below 3% of the DC voltage. To meet this target, additional capacitance can be required other than the minimum recommendations listed in Table 4. Use Equation 23 to calculate total input capacitance based on desired peak-to-peak input-voltage ripple. Equation 23 I × VOUT × (VIN − VOUT ) C IN = MAX f SW × VIN 2 × VINPP ) ( where: CIN = Input capacitance (MLCC) I IRMS_COUT = OUTRIPL 12 IMAX = Maximum load current where IOUTRIPL is the peak-to peak ripple current value. Equation 22 VIN = Input voltage VOUT = Output voltage fSW = Switching frequency (CCM) = PCOUT IRMS_COUT 2 × ESR where ESR is the equivalent series resistance of the entire output capacitor bank. VINPP = Target peak-to-peak input voltage ripple Table 4. Typical Boost, Filtering and Decoupling Capacitor Requirements DESCRIPTION VALUE TYPE PACKAGE QTY 1µF/6.3V X7R/125°C 0402/0603 1 0.47 µF/6.3V X7R/125°C 0402 1 VDDH HF Capacitor (Note 1) 1µF/16V X7R/125°C 0603 1 VDDH HF Capacitor (Note 1) 0.1µF/16V X7R/125°C 0402 1 VDDH Bulk Capacitor (Note 2) 10µF/16V X5R 0805/1206 2 VCC Capacitor Boost Capacitor Note 1: All VDDH high-frequency capacitors must be placed in close proximity to the slave IC and on the same side of the PCB as the slave IC. Refer to Maxim’s layout guideline for component placement requirements and recommendations. Note 2: For operation below 10.8V, two 22µF bulk capacitors are recommended instead of two 10µF capacitors. www.maximintegrated.com Maxim Integrated │ 24 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Because of discontinuous current drawn from the input supply, the power dissipation and ripple-current rating of input capacitors are more important than those of the output capacitors. Use Equation 24 to calculate the RMS current that the input capacitors must withstand. Multiple input caps can be placed in parallel to achieve the required total input RMS current rating. 3) The input capacitors should be placed as close as possible to the input supply pins (VDDH and GND). High-frequency filter capacitors (see Table 4) must be placed within 60 mils of VDDH/GND pins. VCC and BST decoupling capacitors (see Table 4) must be placed on the same side of the PCB board as the IC. There should be an uninterrupted ground plane located immediately underneath these high-frequency current paths, with the ground plane located no more than 8 mils below the top layer. By keeping the flow of this high frequency AC current localized to a tight loop at the regulator, electromagnetic interference (EMI) can be minimized. 4) Keep the sensitive analog signals away from highspeed switching nodes. The ground plane can be used to shield these sensitive signals and protect them from coupling of high-frequency noise. Voltagesense lines should be routed differentially with Kelvin connections to the load points. For remote-sense applications where the load and regulator IC are separated by a significant distance or impedance, it is important to place the majority of the output capacitors directly at the load for system stability. In remotesense applications, common-mode filtering is necessary to filter high-frequency noise in the sense lines. Equation 24 IRMS_CIN = ILOAD VOUT (VIN − VOUT ) VIN where ILOAD is the output DC load current. With an equivalent series resistance of the bulk input capacitor bank (ESRCIN), the total power dissipation in the input capacitors is given by Equation 25. Equation 25 = PCIN IRMS_CIN 2 × ESR CIN Printed Circuit Board Layout Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The high current path requires particular attention. If possible, place all the power components on the top side of the board with their ground terminals flushed against one another. Follow these guidelines for good PCB layout: 1) 2) Keep the power traces and load connections short. This is essential for high efficiency and stable operation. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Pay close attention to correct routing and PCB trace length reduction even by fraction of inches, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. For maximum efficiency place the regulator, output inductor, and output capacitors as close as possible to the load. If this is not possible, keep the output capacitors close the load and output inductor close to the regulator. Keep the high-current traces (VX, VDDH, VCC and BST) short and wide to minimize trace resistance and inductance. Traces connecting the input capacitors and VDDH (power input node) on the IC require particular attention since they carry currents with the largest RMS values and fastest slew rates. www.maximintegrated.com The following layout recommendations should be used for optimal performance: ●● It is essential to have a low-impedance and uninterrupted ground plane under the IC and extended out underneath the inductor and output capacitor bank. ●● Multiple vias are recommended for all paths that carry high currents (i.e., GND, VDDH, VX). Vias should be placed close to the IC to create the shortest possible current loops. Via placement must not obstruct the flow of currents or mirror currents in the ground plane. ●● A single via in close proximity to the chip should be used to tie the top layer AGND trace to the secondlayer ground plane, it must not be connected to the top power-ground area. ●● The feedback divider and compensation network should be close to the IC. Gerber files with layout information and complete reference designs can be obtained by contacting a Maxim account representative. Maxim Integrated │ 25 R1 46.4K 0402 C4 820pF 0402 1V8 STAT OE R18 20.0K 0402 C36 1.0uF VCC OE STAT PGM VDDH MAX38800 AGND www.maximintegrated.com GND VSN VSP Vx BST U6 C8 0.47uF 0603 SENSE- SENSE+ C3 0.1uF X7R 0402 C7 1uF X7R 0603 R12 20.0K 0402 C5 10uF X7R 1206 C37 6.8nF 0402 C38 15nF 0402 R13 2.10K C39 2200pF 0402 0.20uH L1 C6 10uF X7R 1206 R9 2.8K R6 2.10K 0402 C10 10uF X7R 1206 C11 10uF X7R 1206 VDDH C24 0.01uF 0402 12V supply 1 C12 22uF 0805 C13 22uF 0805 C14 22uF 0805 C15 22uF 0805 C16 22uF 0805 C17 22uF 0805 VOUT C18 22uF 0805 1 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Reference Schematic Maxim Integrated │ 26 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Ordering Information PART TEMP RANGE CURRENT LEVEL PIN-PACKAGE SHIPPING METHOD PACKAGE MARKING MAX38800HCS+T 0°C to +125°C 9A 19 WLCSP 2.5ku Tape and Reel MAX38800 www.maximintegrated.com Maxim Integrated │ 27 MAX38800 Integrated, Step-Down Switching Regulator With Selectable Applications Configurations Revision History REVISION NUMBER REVISION DATE 0 9/17 PAGES CHANGED DESCRIPTION Initial release — For information on other Maxim Integrated products, visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc. │ 28