ISSI IS62WV10248BLL-55BLI 1m x 8 low voltage, ultra low power cmos static ram Datasheet

ISSI
IS62WV10248BLL
1M x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
®
MARCH 2006
FEATURES
DESCRIPTION
• High-speed access time: 55ns, 70ns
The ISSI IS62WV10248BLL is a high-speed, 8M bit static
RAMs organized as 1M words by 8 bits. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
• CMOS low power operation:
36 mW (typical) operating
12 µW (typical) CMOS standby
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at which
the power dissipation can be reduced down with CMOS input
levels.
• TTL compatible interface levels
• Single power supply:
2.5V--3.6V VDD (IS62WV10248BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV10248BLL is packaged in the JEDEC standard
48-pin mini BGA (7.2mm x 8.7mm).
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1M x 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
1
ISSI
IS62WV10248BLL
®
PIN DESCRIPTIONS
A0-A19
Address Inputs
CS1
Chip Enable 1 Input
CS2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
NC
No Connection
VDD
Power
GND
Ground
PIN CONFIGURATION
48-pin mini BGA (B) (7.2mm x 8.7mm)
1
2
2
3
4
5
6
A
NC
OE
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1
NC
C
I/O0
NC
A5
A6
NC
I/O4
D
GND
I/O1
A17
A7
I/O5
VDD
E
VDD
I/O2
NC
A16
I/O6
GND
F
I/O3
NC
A14
A15
NC
I/O7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
ISSI
IS62WV10248BLL
®
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CS1
CS2
OE
I/O Operation
VDD Current
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High-Z
High-Z
High-Z
DOUT
DIN
ISB1, ISB2
ISB1, ISB2
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
VDD Related to GND
Storage Temperature
Power Dissipation
Value
–0.2 to VDD+0.3
–0.2 to +3.8
–65 to +150
1.0
Unit
V
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (VDD)
Range
Ambient Temperature
IS62WV10248BLL
0°C to +70°C
–40°C to +85°C
2.5V - 3.6V
2.5V - 3.6V
Commercial
Industrial
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
VDD
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -1 mA
2.5-3.6V
2.2
—
V
VOL
Output LOW Voltage
IOL = 2.1 mA
2.5-3.6V
—
0.4
V
VIH
VIL(1)
Input HIGH Voltage
2.5-3.6V
2.2
VDD + 0.3
V
Input LOW Voltage
2.5-3.6V
–0.2
0.6
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
3
ISSI
IS62WV10248BLL
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
8
pF
VOUT = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
IS62WV10248BLL
(Unit)
0.4 to VDD-0.3V
5 ns
VREF
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
See Figures 1 and 2
IS62WV10248BLL
2.5V - 3.6V
R1(Ω)
1029
R2(Ω)
1728
VREF
1.5V
VTM
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
4
R2
5 pF
Including
jig and
scope
R2
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
ISSI
IS62WV10248BLL
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS62WV10248BLL
Symbol Parameter
Test Conditions
ICC
VDD = Max.,
IOUT = 0 mA, f = fMAX
VDD = Max., CS1 = 0.2V
WE = VDD -0.2V
CS2 = VDD -0.2V, f = 1MHz
VDD = Max.,
VIN = VIH or VIL
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
ICC1
VDD Dynamic Operating
Supply Current
Operating Supply
Current
ISB1
TTL Standby Current
(TTL Inputs)
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CS1 ≥ VDD – 0.2V,
CS2 ≤ 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Max.
70
25
30
5
5
Unit
Com.
Ind.
Com.
Ind.
Max.
55
30
35
5
5
Com.
Ind.
0.3
0.3
0.3
0.3
mA
Com.
Ind.
typ.(1)
20
25
3
20
25
3
µA
mA
mA
Note:
1. Typical Values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
5
ISSI
IS62WV10248BLL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
55 ns
Min.
Max.
70 ns
Min.
Max.
Unit
tRC
Read Cycle Time
55
—
70
—
ns
tAA
Address Access Time
—
55
—
70
ns
tOHA
Output Hold Time
10
—
10
—
ns
tACS1/tACS2
CS1/CS2 Access Time
—
55
—
70
ns
tDOE
OE Access Time
—
25
—
35
ns
OE to High-Z Output
—
20
—
25
ns
tHZOE
(2)
OE to Low-Z Output
5
—
5
—
ns
(2)
tHZCS1/tHZCS2
CS1/CS2 to High-Z Output
0
20
0
25
ns
(2)
tLZCS1/tLZCS2
CS1/CS2 to Low-Z Output
10
—
10
—
ns
tLZOE(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse
levels of 0.4V to VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
tRC
ADDRESS
tAA
tOHA
DOUT
6
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
ISSI
IS62WV10248BLL
®
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
7
ISSI
IS62WV10248BLL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
tWC
55 ns
Min.
Max.
Parameter
Write Cycle Time
70 ns
Min. Max.
Unit
55
—
70
—
ns
45
—
60
—
ns
45
—
60
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
tSD
WE Pulse Width
40
—
50
—
ns
Data Setup to Write End
25
—
30
—
ns
tHD
tHZWE(3)
Data Hold from Write End
0
—
0
—
ns
WE LOW to High-Z Output
—
25
—
25
ns
tLZWE
WE HIGH to Low-Z Output
5
—
5
—
ns
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
Address Setup Time to Write End
tHA
tSA
(4)
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to VDD0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHZWE + tSD when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
8
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
ISSI
IS62WV10248BLL
®
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
tHD
9
ISSI
IS62WV10248BLL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
1.2
3.6
V
IDR
Data Retention Current
VDD = 1.2V, CS1 ≥ VDD – 0.2V
—
20
µA
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
DATA RETENTION WAVEFORM (CS1
CS1 Controlled)
Data Retention Mode
tSDR
tRDR
VDD
3.0V
2.2V
VDR
CS1 ≥ VDD
CS1
GND
- 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
VDD
3.0
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
ISSI
IS62WV10248BLL
®
ORDERING INFORMATION: IS62WV10248BLL (2.5V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV10248BLL-55BI
IS62WV10248BLL-55BLI
mini BGA (7.2mm x 8.7mm)
mini BGA (7.2mm x 8.7mm), Lead-free
70
IS62WV10248BLL-70BI
mini BGA (7.2mm x 8.7mm)
70
IS62WV10248BLL-70XI
DIE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
11
ISSI
IS62WV10248BLL
®
Mini Ball Grid Array
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
D
5
4
3
2
1
A
e
B
B
C
C
D
D
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
A
A1
SEATING PLANE
mBGA - 7.2mm x 8.7mm
MILLIMETERS
Sym.
Min. Typ. Max.
N0.
Leads
48
Min. Typ.
Max.
A
—
—
1.20
—
—
0.047
A1
0 .24
—
0.30
0.009
—
0.012
A2
0.60
—
—
0.024
—
—
D
8.60
8.70
8.80
D1
E
5.25BSC
7.10
7.20
0.339 0.343 0.346
0.207BSC
7.30
0.280 0.283 0.287
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
b
12
Notes:
1. Controlling dimensions are in millimeters.
INCHES
0.30
0.35
0.40
0.012 0.014 0.016
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/17/06
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