Mitsubishi M66222SP 128 x 8-bit x 2 mail-box Datasheet

MITSUBISHI
MITSUBISHI
〈DIGITAL
〈DIGITAL
ASSP〉
ASSP〉
M66222SP/FP
M66222SP/FP
× 8-BIT
2 MAIL-BOX
128128
× 8-BIT
× 2 ×MAIL-BOX
DESCRIPTION
The M66222 is a mail box that incorporates two complete CMOS
shared memory cells of 128 × 8-bit configuration using highperformance silicon gate CMOS process technology, and are
equipped with two access ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations individually. This product
exclusively performs a write operation from A port and a read operation
from B port for one memory, and a read operation from A port and a
write operation from B port for the other memory.
Memory configuration of 128 × 8 bits × 2 memory areas
High-speed access, address access time 40ns (typ.)
Complete asynchronous accessibility from ports A and B
Fixed read/write access ports for memory
Completely static operation
Low power dissipation CMOS design
5V single power supply
TTL direct-coupled I/O
3-state output for I/O pins
 I/O0A ↔

 I/O1A ↔

 I/O2A ↔

↔
A PORT  I/O3A
DATA I/O 
↔
4
A
I/O


 I/O5A ↔

 I/O6A ↔

 I/O7A ↔
APPLICATION
Inter-MCU data transfer memory, communication buffer memory
GND
42
1
2
3
4
5
6
7
8
9
10
11
12
13
VCC
CHIP SELECT
41 ← CSB INPUT
40 ← WEB WRITE ENABLE
INPUT
NC
39
OUTPUT ENABLE
38 ← OEB INPUT
37 ← A0B 

36 ← A1B 

35 ← A2B 

34 ← A3B  B PORT
 ADDRESS
33 ← A4B  INPUT

32 ← A5B 

31 ← A6B 

30 ← A7B 
29 ↔ I/O7B 

28 ↔ I/O6B 

27 ↔ I/O5B 

26 ↔ I/O4B  B PORT
 DATA I/O
25 ↔ I/O3B 

24 ↔ I/O2B 

23 ↔ I/O1B 

22 ↔ I/O0B 
14
15
16
17
18
19
20
21
Outline 42P4B
42P2R-A
NC: No Connection
BLOCK DIAGRAM
41 CSB CHIP
OUTPUT BUFFER
13
14
15
16
17
18
19
20
SENSE AMPLIFIER
I/O0A
I/O1A
I/O2A
I/O3A
I/O4A
I/O5A
I/O6A
I/O7A
MEMORY AREA(1)
Write 128-WORD × 8-BIT Read
CONFIGURATION
0-127
ADDRESSES
VCC
READ/
WRITE
CONTROL
CIRCUIT
ROW/COLUMN
DECODER
A0A~A6A
7
A0B~A6B
7
ROW/COLUMN
DECODER
SENSE AMPLIFIER
12
5
6
7
8
9
10
11











A PORT
DATA I/O











A PORT
ADDRESS
INPUT
A7A
A0A
A 1A
A 2A
A 3A
A 4A
A5A
A6A
READ/
WRITE
CONTROL
CIRCUIT
OUTPUT BUFFER
CHIP SELECT CSA 1
INPUT
WRITE
WEA 2
ENABLE INPUT
OUTPUT
OEA 4
ENABLE INPUT
INPUT DATA CONTROL
CIRCUIT
42
MEMORY AREA(2)
Read 128-WORD × 8-BIT Write
CONFIGURATION
128-255
ADDRESSES
INPUT DATA CONTROL
CIRCUIT
•
•
•
•
•
•
•
•
•
CHIP SELECT
CSA →
INPUT
WRITE ENABLE
WEA →
INPUT
NC
OUTPUT ENABLE
OEA →
INPUT
 A 0A →

 A 1A →

 A 2A →

A PORT  A3A →
ADDRESS 
INPUT
 A 4A →

 A 5A →

 A 6A →

 A 7A →
M66222SP/FP
FEATURES
PIN CONFIGURATION (Top view)
21
SELECT INPUT
WRITE
40 WEB
ENABLE INPUT
38 OEB OUTPUT
ENABLE INPUT
30
37
36
35
34
33
32
31
A7B
A0B
A1B
A2B
A3B
A4B
A5B
A6B



 B PORT

 ADDRESS
 INPUT




22
23
24
25
26
27
28
29
I/O0B
I/O1B
I/O2B
I/O3B
I/O4B
I/O5B
I/O6B
I/O7B




 B PORT

 DATA I/O




GND
1
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
FUNCTION
The M66222 is a mail box most suitable for inter-MCU data
communication interface. Provision of two pairs of addresses and
data buses in its shared memory cell of 128 × 8-bit configuration
allows independent and asynchronous read/write operations from/to
two access ports of A and B individually.
Two memory areas of 128 × 8-bit configuration are incorporated in
the chip. Memory area (1) is used only to perform a write operation
from A port and a read operation from B port, and memory area (2)
only to perform a read operation from A port and a write operation
from B port.
In this case, address A7A should be set to “L” when writing data from
A port in memory area (1), and address A7B should be set to “L”
when reading data from B port in memory area (1). Also, address
A7B should be set to “H” when writing data from B port in memory
area (2), and address A7A should be set to “H” when reading data
from A port in memory area (2).
Therefore, an attempt to set addresses A7A and A7B from each port
in a mode other than the above setting invalidates any read/write
operation from the corresponding port (See Table 1 and Fig 1).
As a basic write operation to memory, one of addresses A0 to A7 is
specified. The CS signal is set to “L” to place one of I/O pins in the
input mode. Also, the WE signal is set to “L”. Data at the I/O pin is
written into memory.
As a read operation, the WE signal is set to “H”. Both CS signal and
OE signal are set to “L” to place one of I/O pins in the output mode.
One of addresses A0 to A7 is specified. Data at the specified address
is thus output to the I/O pin.
When the CS signal is set to “H”, the chip enters a non-select state
which inhibits a read and write operation. At this time, the output is
placed in the floating state (high impedance state), thus allowing OR
tie with another chip. When the OE signal is set to “H”, the output
enters the floating state. In the I/O bus mode, setting the OE signal
to "H" at a write time avoids contention of I/O bus data. When the CS
signal is set to Vcc, the output enters the full stand-by state to minimize
supply current (See Tables 2 and 3).
Table 1 Port Operations and Address A7 Setting Conditions
Access
port
Operation
Write
Read
B port
A7A = “L”
A7A = “H”
A7B = “H”
A7B = “L”
Note 1: No input data is written into any port having address A7 set under
any condition other than Table 1. Undefined data is read to an
output pin during a read operation.
Write A7A = “L”
A7B = “L” Read
Memory area (1)
of 128-word × 8-bit
configuration
0-127 addresses
A port
A port
Memory area (2)
of 128-word × 8-bit
configuration
128-255 addresses
Read A7A = “H”
B port
A7B = “H” Write
Fig 1 Access from Ports
Table 2 A Port Function Table
CSA WEA OEA A7A
L
L
L
×
H
L
L
H
L
H
L
H
H
×
H
×
×
×
Mode
Write
Invalid
Invalid
Read
—
Non-select
Note 2: × indicates “L” or “H”. (Irrelevant)
“H” = High level, “L” = Low level
2
Table 3 B Port Function Table
I/O pin
DIN
DIN
DOUT
DOUT
High impedance
High impedance
ICC
Operation
Operation
Operation
Operation
Operation
Stand-by
CSB WEB OEB A7B
L
L
L
×
H
L
L
H
L
H
L
H
H
×
H
×
×
×
Mode
Invalid
Write
Read
Invalid
—
Non-select
I/O pin
DIN
DIN
DOUT
DOUT
High impedance
High impedance
ICC
Operation
Operation
Operation
Operation
Operation
Stand-by
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
FUNCTIONAL DESCRIPTION
(4). There is no concern about uncertainty of read/write data at an
active address. If one port operates in the write mode and the other
does in the read mode as given in (2) and (3), however, the same
address may be selected. In this case, data of the port operating in
the write mode is written. If the port in the read mode comes first,
read data of the first-in port becomes uncertain until write data of the
last-in port is determined (If the same address is selected, data of
the port operating in the write mode is written into memory. Therefore,
data of the port in the read mode may change from previously written
data to newly written ones during the same cycle) (See Fig 2).
The M66222 with independent and asynchronous accessibility from
two ports has the following four basic operations depending on an
address and mode set from both ports:
(1) A port .......... Write
B port .......... Write
(2) A port .......... Write
B port .......... Read
(3) A port .......... Read
B port .......... Write
(4) A port .......... Read
B port .......... Read
In this case, the same address is not selected when the same read/
write instruction is being executed at both ports as given in (1) and
Ex.) A port - address setting first-in read operation
B port - address setting last-in write operation
: When selecting the same address
A port address
B port address
WEB
B port I/O
(DIN)
Data B
(Data written from B port)
A port I/O
(DOUT)
Data A
Data B
(Data read to A port)
Fig 2 Example of Read Data Transition at Selection of Same Address
3
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol
VCC
VI
VO
Pd
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Maximum power dissipation
Storage temperature range
Conditions
When defining GND pin as a
reference.
Ta = 25°C
Ratings
–0.3 ~ +7.0
–0.3 ~ VCC + 0.3
0 ~ VCC
700
–65 ~ 150
Unit
V
V
V
mW
°C
Limits
Typ.
Unit
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
GND
VI
Topr
Parameter
Supply voltage
Ground
Input voltage
Operating temperature range
Limits
Typ.
5.0
0
Min.
4.5
0
0
Max.
5.5
VCC
70
Unit
V
V
V
°C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
VIH
VIL
VOH
VOL
IIH
IIL
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
“H” input current
“L” input current
IOZH
Off state “H” output current
IOZL
ICC
Test conditions
Min.
2.2
–0.3
2.4
Max.
VCC+0.3
0.8
0.5
10.0
–10.0
V
V
V
V
µA
µA
CS = VIH or OE = VIH
VO = VCC
10.0
µA
Off state “L” output current
CS = VIH or OE = VIH
VO = GND
–10.0
µA
Static current dissipation (active)
CS < 0.2V,
Another input VIN > VCC – 0.2V
or VIN < 0.2V, Output pin open
60
mA
5
mA
IOH = –2mA
IOL = 4mA
VI = VCC
VI = GND
Two-port stand-by
CSA, CSB = VIH
ISB2
One-port stand-by
CSA or CSB = VIH
IOUT = 0mA
(Active port output pin open)
60
mA
Two-port full stand-by
CSA, CSB > VCC – 0.2V
Another input VIN > VCC – 0.2V
or VIN < 0.2V
0.1
mA
ISB4
One-port full stand-by
CSA or CSB > VCC – 0.2V
Another input VIN > VCC – 0.2V
or VIN < 0.2V, IOUT = 0mA
(Active port output pin open)
30
mA
CI
CO
Input capacitance
Output capacitance in off state
10
15
pF
pF
ISB3
Stand-by current
ISB1
Notes 3: The direction in which current flows into the IC is defined as positive (no sign).
4: The above typical values are standard values for VCC=5V and Ta=25°C.
4
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V±10%, unless otherwise noted)
Read cycle
Symbol
tCR
ta(A)
ta(CS)
ta(OE)
tdis(CS)
tdis(OE)
ten(CS)
ten(OE)
tv(A)
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after CS (Note 5)
Output disable time after OE (Note 5)
Output enable time after CS (Note 5)
Output enable time after OE (Note 5)
Data effective time after Address
Min.
70
Limits
Typ.
Max.
70
70
35
35
35
5
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING REQUIREMENTS (Ta = 0 ~ 70°C, VCC = 5V±10%, unless otherwise noted)
Write cycle
Symbol
tCW
tw(WE)
tsu(A)1
tsu(A)2
tsu(A-WEH)
tsu(CS)
tsu(D)
th(D)
trec(WE)
tdis(WE)
tdis(OE)
ten(WE)
ten(OE)
Parameter
Write cycle time
Write pulse width
Address setup time (for WE)
Address setup time (for CS)
Address setup time for rise of WE
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after WE (Note 5)
Output disable time after OE (Note 5)
Output enable time after WE (Note 5)
Output enable time after OE (Note 5)
Min.
70
45
0
0
65
65
40
0
0
Limits
Typ.
Max.
35
35
0
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5: The time required for the output to change from a steady state to ±500mV under the load conditions shown in Figure 4.
This parameter is guaranteed but is not tested at shipment.
5
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
TIMING DIAGRAM
Read Cycle (WE = VIH)
Read cycle No. 1 (Address control) (CS = OE = VIL)
tCR
A0~A7
ta(A)
tv(A)
tv(A)
I/O0~I/O7
(DOUT)
Data output determined
Previous cycle data
Read cycle No. 2 (CS control)
tCR
A0~A7
ta(A)
CS
ta(CS)
tdis(CS)
ten(CS)
OE
ta(OE)
tdis(OE)
ten(OE)
I/O0~I/O7
(DOUT)
6
Data output determined
High impedance
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
Write Cycle
Write cycle No.1 (WE control) See Notes 6, 7 and 8.
tCW
A0~A7
tsu(CS)
CS
tsu(A-WEH)
OE
tw(WE)
tsu(A)1
trec(WE)
WE
tsu(D)
I/O0~I/O7
(DIN)
th(D)
Data input determined
tdis(WE)
ten(OE)
tdis(OE)
ten(WE)
I/O0~I/O7
(DOUT)
Write cycle No.2 (CS control) See Notes 7 and 8.
tCW
A0~A7
tsu(A)2
tsu(CS)
trec(WE)
CS
WE
tsu(D)
I/O0~I/O7
(DIN)
th(D)
Data input determined
Notes 6:
7:
8:
9:
The WE of the port must be set to “H” when an address input changes.
A write operation is performed during the overlap period when both CS and WE are “L”.
Do not apply any negative-phase signal from outside when an I/O pin is in output state.
The shaded part means a state in which a signal can be “H” or “L”.
7
MITSUBISHI 〈DIGITAL ASSP〉
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
Input pulse level
Input pulse rise/fall time
Input timing reference voltage
Output timing decision voltage
Output load
: VIH = 3.0V, VIL = 0V
: tr/tf = 5ns
: 1.5V
: 1.5V
: Figure 3 ~ 4 (The capacitance includes stray wiring capacitance and the probe input capacitance.)
+ 5V
+ 5V
1250Ω
1250Ω
I/O
I/O
775Ω
100pF
Fig 3. Output Load
8
775Ω
5pF
Fig 4. Output Load (to ten, tdis)
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