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H7N0608LD, H7N0608LS, H7N0608LM Silicon N Channel MOS FET High Speed Power Switching REJ03G0144-0100Z Rev.1.00 Oct.30.2003 Features • Low on-resistance RDS(on) = 6.0 mΩ typ. • Low drive current • Available for 4.5 V gate drive Outline LDPAK D 4 G 1 1 S Rev.1.00, Oct.30.2003, page 1 of 11 2 4 4 2 1 3 2 3 H7N0608LS H7N0608LM 3 H7N0608LD 1. Gate 2. Drain 3. Source 4. Drain H7N0608LD, H7N0608LS, H7N0608LM Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage VDSS 60 V Gate to source voltage VGSS ±20 V Drain current ID 70 A Note1 Drain peak current ID (pulse) 280 A Body-drain diode reverse drain current IDR 70 A 40 A Note3 Avalanche current IAP Avalanche energy EARNote3 Channel dissipation Pch Channel temperature Storage temperature 137 mJ 80 W Tch 150 °C Tstg –55 to +150 °C Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Rev.1.00, Oct.30.2003, page 2 of 11 Note2 H7N0608LD, H7N0608LS, H7N0608LM Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS — — V ID = 10 mA, VGS = 0 Gate to source breakdown Voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0 Gate to source leak current IGSS — — ±10 µA VGS = ±16 V, VDS = 0 Zero gate voltage drain current IDSS — — 10 µA VDS = 60 V, VGS = 0 Gate to source cutoff voltage VGS(off) 1.5 — 2.5 V ID = 1 mA, VDS = 10 VNote1 Static drain to source on state RDS(on) — 6.0 8.0 mΩ ID = 35 A, VGS = 10 VNote1 — 8.0 12 mΩ ID = 35 A, VGS = 4.5 VNote1 resistance 60 Forward transfer admittance |yfs| 45 75 — S ID = 35 A, VGS = 10 VNote1 Input capacitance Ciss — 6200 — pF VDS = 10 V Output capacitance Coss — 680 — pF VGS = 0 Reverse transfer capacitance Crss — 350 — pF f = 1 MHz Total gate charge Qg — 100 — nC VDD = 25 V Gate to source charge Qgs — 20 — nC VGS = 10 V Gate to drain charge Qgd — 20 — nC ID = 70 A Turn-on delay time td(on) — 45 — ns VGS = 10 V, ID = 35 A Rise time tr — 220 — ns RL = 0.86 Ω Turn-off delay time td(off) — 125 — ns Rg = 4.7 Ω Fall time tf — 35 — ns Body–drain diode forward voltage VDF — 0.94 — V IF = 70 A, VGS = 0 Body–drain diode reverse recovery time — 40 — ns IF = 70 A, VGS = 0 diF/dt = 100 A/µs trr Notes: 1. Pulse test Rev.1.00, Oct.30.2003, page 3 of 11 H7N0608LD, H7N0608LS, H7N0608LM Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area 1000 300 (A) Drain Current 40 0 50 100 150 Case Temperature 0.3 0.1 Operation in this area is limited by RDS(on) 0.03 Ta = 25°C 0.01 0.1 0.3 1 200 3 10 Drain to Source Voltage Tc (°C) 30 VDS 100 (V) Typical Transfer Characteristics 100 40 VGS = 3.2 V 20 (A) 3.6 V 80 ID Pulse Test 10 V 4.5 V 4.0 V 60 Drain Current (A) ID Drain Current PW = 10 ms (1 shot) 1 Typical Output Characteristics 60 DC Operation (Tc = 25°C) 3 100 80 s 30 10 µs s m 80 0µ 100 ID 120 10 10 1 Channel Dissipation Pch (W) 160 VDS = 10 V Pulse Test 40 Tc = 150°C 20 25°C –40°C 0 2 4 6 Drain to Source Voltage Rev.1.00, Oct.30.2003, page 4 of 11 8 VDS 10 (V) 0 2 4 6 Gate to Source Voltage 8 VGS 10 (V) H7N0608LD, H7N0608LS, H7N0608LM Static Drain to Source on State Resistance vs. Drain Current Pulse Test 400 ID = 50 A 300 200 20 A 100 10 A 0 4 12 8 Drain to Source on State Resistance RDS(on) (mΩ) Gate to Source Voltage 16 50 A 10, 20 A 4 4.5 V VGS = 10 V 0 –50 –25 0 25 10, 20, 50 A 50 75 100 125 150 Case Temperature Tc Rev.1.00, Oct.30.2003, page 5 of 11 Pulse Test 30 VGS = 4.5 V 10 10 V 3 1 1 3 VGS (V) 16 8 100 20 Static Drain to Source on State Resistance vs. Temperature 20 Pulse Test 12 Drain to Source on State Resistance RDS(on) (mΩ) 500 (°C) 30 100 300 1000 10 Drain Current ID (A) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source Saturation Voltage VDS(on) (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage 1000 300 VDS = 10 V Pulse Test Tc = –40°C 100 30 25°C 10 150°C 3 1 0.3 0.1 0.1 0.3 1 3 Drain Current ID 10 30 (A) 100 H7N0608LD, H7N0608LS, H7N0608LM Body-Drain Diode Reverse Recovery Time 10000 di / dt = 100 A / µs VGS = 0, Ta = 25°C 300 100 30 10 1000 Coss 300 30 0.3 1 3 10 Reverse Drain Current 30 Crss 100 3 1 0.1 Ciss 3000 Capacitance C (pF) Reverse Recovery Time trr (ns) 1000 Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz 10 0 100 IDR (A) 10 VDS 40 20 0 (V) 12 8 VDD = 50 V 25 V 10 V 40 80 120 160 Gate Charge Qg (nc) Rev.1.00, Oct.30.2003, page 6 of 11 4 0 200 VGS VDD = 50 V 25 V 10 V 300 Switching Time t (ns) 60 16 Gate to Source Voltage VDS (V) Drain to Source Voltage VGS 80 40 50 (V) Switching Characteristics 1000 20 ID = 85 A 30 Drain to Source Voltage VDS Dynamic Input Characteristics 100 20 tf tr td(off) 100 td(on) tf 30 tr 10 VGS = 10 V, VDD = 30 V 3 PW = 5 µs, duty < 1 % Rg = 4.7 Ω 1 0.1 0.3 3 10 1 Drain Current ID 30 (A) 100 H7N0608LD, H7N0608LS, H7N0608LM Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current IDR (A) 100 80 10 V 60 40 5V VGS = 0, –5 V 20 Pulse Test 0 0.4 0.8 1.2 Source to Drain Voltage 1.6 2.0 VSD 200 IAP = 40 A VDD = 25 V duty < 0.1 % Rg > 50 Ω 160 120 80 40 0 25 (V) 50 75 100 125 Channel Temperature Tch (°C) Avalanche Test Circuit V DS Monitor Avalanche Waveform EAR = L 1 2 • L • I AP • 2 I AP Monitor VDSS VDSS – V DD V (BR)DSS I AP Rg D. U. T V DS VDD ID Vin 15 V 50Ω 0 Rev.1.00, Oct.30.2003, page 7 of 11 150 VDD H7N0608LD, H7N0608LS, H7N0608LM Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 1 Tc = 25°C D=1 0.5 0.3 0.2 0.1 0.1 0.03 θch - c(t) = γs (t) • θch - c θch - c = 1.56°C/ W, Tc = 25°C 0.05 2 0.0 PDM e 1 0.0 t ho ls pu D= PW 1s 0.01 10 µ PW T T 100 µ 1m 10 m 100 m 1 10 100 Pulse Width PW (S) Switching Time Test Circuit Vout Monitor Vin Monitor Rg Waveform 90% D.U.T. RL Vin Vout Vin 10 V V DS = 30 V 10% 90% td(on) Rev.1.00, Oct.30.2003, page 8 of 11 10% tr 10% 90% td(off) tf H7N0608LD, H7N0608LS, H7N0608LM Package Dimensions • H7N0608LD As of January, 2003 4.44 ± 0.2 10.2 ± 0.3 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.2 0.86 +– 0.1 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 11.0 ± 0.5 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 (1.4) Unit: mm 2.49 ± 0.2 0.4 ± 0.1 Package Code JEDEC JEITA Mass (reference value) Rev.1.00, Oct.30.2003, page 9 of 11 LDPAK (L) — — 1.40 g H7N0608LD, H7N0608LS, H7N0608LM • H7N0608LS As of January, 2003 Unit: mm (1.5) 10.0 7.8 7.0 2.49 ± 0.2 0.2 0.1 +– 0.1 1.7 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 1.3 ± 0.2 Package Code JEDEC JEITA Mass (reference value) Rev.1.00, Oct.30.2003, page 10 of 11 LDPAK (S)-(1) — — 1.30 g H7N0608LD, H7N0608LS, H7N0608LM • H7N0608LM As of January, 2003 Unit: mm (2.3) 10.0 7.8 7.0 2.49 ± 0.2 1.7 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 0.2 0.1 +– 0.1 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 5.0 +– 0.5 1.3 ± 0.2 Package Code JEDEC JEITA Mass (reference value) Rev.1.00, Oct.30.2003, page 11 of 11 LDPAK (S)-(2) — — 1.35 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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