Allegro A3968SLB-T Dual full-bridge pwm motor driver with brake Datasheet

Data Sheet
29319.29E
3968
DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
The A3968SA and A3968SLB are designed to bidirectionally control two
dc motors. Each device includes two H-bridges capable of continuous output
currents of ±650 mA and operating voltages to 30 V. Motor winding current
can be controlled by the internal fixed-frequency, pulse-width modulated
(PWM), current-control circuitry. The peak load current limit is set by the
user’s selection of a reference voltage and current-sensing resistors. Except
for package style and pinout, the two devices are identical.
The fixed-frequency pulse duration is set by a user-selected external RC
timing network. The capacitor in the RC timing network also determines a
user-selectable blanking window that prevents false triggering of the PWM
current-control circuitry during switching transitions.
To reduce on-chip power dissipation, the H-bridge power outputs have
been optimized for low saturation voltages. The sink drivers feature the
Allegro® patented Satlington® output structure. The Satlington outputs
combine the low voltage drop of a saturated transistor and the high peak
current capability of a Darlington.
For each bridge, the INPUTA and INPUTB terminals determine the load
current polarity by enabling the appropriate source and sink driver pair. When
a logic low is applied to both INPUTs of a bridge, the braking function is
enabled. In brake mode, both source drivers are turned OFF and both sink
drivers are turned ON, thereby dynamically braking the motor. When a logic
high is applied to both INPUTs of a bridge, all output drivers are disabled.
Special power-up sequencing is not required. Internal circuit protection
includes thermal shutdown with hysteresis, ground-clamp and flyback diodes,
and crossover-current protection.
The A3968SA is supplied in a 16-pin dual in-line plastic package. The
A3968SLB is supplied in a 16-pin plastic SOIC with copper heat sink tabs.
The power tab is at ground potential and needs no electrical isolation. The LB
package is available in a lead (Pb) free version (100% matte tin leadframe).
A3968SLB (SOIC)
OUT1A
1
INPUT1A
2
INPUT1B
3
GROUND
4
SENSE 1
5
OUT 1B
6
LOAD
SUPPLY
7
REFERENCE
8
16
OUT 2A
15
INPUT2A
14
INPUT2B
13
GROUND
12
SENSE 2
11
OUT 2B
V CC
10
LOGIC
SUPPLY
RC
9
VBB
LOGIC
VBB
V REF
LOGIC
RC
Dwg. PP-066
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ................... 30 V
Output Current, IOUT (peak) .......... ±750 mA
(continuous) .............................. ±650 mA
Logic Supply Voltage, VCC ................. 7.0 V
Input Voltage, Vin ..... -0.3 V to VCC + 0.3 V
Sense Voltage, VS ................................ 1.0 V
Package Power Dissipation (TA = 25°C), PD
A3968SA ..................................... 1.8 W*
A3968SLB ................................... 1.4 W*
Operating Temperature Range,
TA ................................... -20°C to +85°C
Junction Temperature,
TJ ................................................. +150°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
* Per SEMI G42-88 Specification, Thermal Test
Board Standardization for Measuring Junctionto-Ambient Thermal Resistance of Semiconductor
Packages.
FEATURES
■
■
■
■
■
■
■
■
■
*
±650 mA Continuous Output Current
30 V Output Voltage Rating
Internal Fixed-Frequency PWM Current Control
Satlington Sink Drivers
Brake Mode
User-Selectable Blanking Window
Internal Ground-Clamp & Flyback Diodes
Internal Thermal-Shutdown Circuitry
Crossover-Current Protection and UVLO Protection
Part Number
Pb-free*
RθJA
(°C/W)
RθJT
(°C/W)
Package
Packing
A3968SLB-T
A3968SLBTR-T
Yes
Yes
90
90
6
6
16-Lead SOIC
16-Lead SOIC
47 per tube
1000 per reel
Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be LAST TIME BUY. This
classification indicates that sale of this device is currently restricted to existing customer
applications. The variants should not be purchased for new design applications because
obsolescence in the near future is probable. Samples are no longer available. Status
change: October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007.
These variants include: A3968SA, A3968SLB, and A3968SLBTR.
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL BLOCK DIAGRAM
LOAD
SUPPLY
OUTB
OUTA
LOGIC
SUPPLY
(one-half of circuit shown)
V CC
INPUTA
+
CONTROL LOGIC
V BB
UVLO
& TSD
SOURCE
ENABLE
INPUTB
PWM LATCH
BLANKING
GATE
CURRENT-SENSE
COMPARATOR
SENSE
+
–
R
Q
TO OTHER
BRIDGE
TO OTHER
BRIDGE
S
÷4
GROUND
RS
OSC
RC
REFERENCE
TO OTHER
BRIDGE
CT
RT
Dwg. FP-036-4
A3968SA (DIP)
1
16
INPUT1B
OUT 1B
2
15
INPUT1A
LOAD
SUPPLY
3
14
OUT 1A
REFERENCE
4
V REF
13
GROUND
RC
5
RC
12
GROUND
LOGIC
SUPPLY
6
V
11
OUT 2A
OUT 2B
7
10
INPUT 2A
SENSE 2
8
9
INPUT 2B
LOGIC
SENSE 1
TRUTH TABLE
V BB
LOGIC
CC
INPUTA
L
L
H
H
INPUTB
L
H
L
H
OUTA
L
L
H
Z
Z = High impedance
Dwg. PP-066-3
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1997, 2003 Allegro MicroSystems, Inc.
OUTB
L
H
L
Z
Description
Brake mode
“Forward”
“Reverse”
Disable
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,
VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VCC
—
30
V
Output Drivers
Load Supply Voltage Range
VBB
Operating, IOUT = ±650 mA, L = 3 mH
Output Leakage Current
ICEX
VOUT = 30 V
—
<1.0
50
µA
VOUT = 0 V
—
<-1.0
-50
µA
Source Driver, IOUT = -400 mA
—
1.7
2.0
V
Source Driver, IOUT = -650 mA
—
1.8
2.1
V
Sink Driver, IOUT = +400 mA, VS = 0.5 V
—
0.3
0.5
V
Sink Driver, IOUT = +650 mA, VS = 0.5 V
—
0.7
1.3
V
IF = 400 mA
—
1.1
1.4
V
IF = 650 mA
—
1.4
1.6
V
IBB(ON)
Both bridges ON (forward or reverse)
—
3.0
5.0
mA
IBB(OFF)
All INPUTs = 2.4 V
—
<1.0
200
µA
4.75
—
5.50
V
Output Saturation Voltage
Clamp Diode Forward Voltage
Motor Supply Current
(No Load)
VCE(SAT)
VF
Control Logic
Logic Supply Voltage Range
VCC
Operating
Logic Input Voltage
VIN(1)
2.4
—
—
V
VIN(0)
—
—
0.8
V
IIN(1)
VIN = 2.4 V
—
<1.0
20
µA
IIN(0)
VIN = 0.8 V
—
<-20
-200
µA
Reference Input Volt. Range
VREF
Operating
0.1
–
2.0
V
Reference Input Current
IREF
-2.5
0
1.0
µA
Reference Divider Ratio
VREF/VTRIP
3.8
4.0
4.2
—
Logic Input Current
Current-Sense Comparator
Input Offset Voltage
VIO
VREF = 0.1 V
-6.0
0
6.0
mV
Current-Sense Comparator
Input Voltage Range
VS
Operating
-0.3
—
1.0
V
Sense-Current Offset
ISO
IS – IOUT, 50 mA ≤ IOUT ≤ 650 mA
12
18
24
mA
NOTES:1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
www.allegromicro.com
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,
VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise) (cont.)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
22.9
25.4
27.9
kHz
Comparator Trip to Source OFF
—
1.0
1.4
µs
Cycle Reset to Source ON
—
0.8
1.2
µs
Control Logic (continued)
PWM RC Frequency
PWM Propagation Delay Time
fosc
tPWM
CT = 680 pF, RT = 56 kΩ
Cross-Over Dead Time
tcodt
1 kΩ Load to 25 V
0.2
1.8
3.0
µs
Propagation Delay Times
tpd
IOUT = ±650 mA, 50% to 90%:
Disable OFF to Source ON
Disable ON to Source OFF
Disable OFF to Sink ON
Disable ON to Sink OFF
Brake Enable to Sink ON
Brake Enable to Source OFF
—
—
—
—
—
—
100
500
200
200
2200
200
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
TJ
—
165
—
°C
∆TJ
—
15
—
°C
—
4.1
4.6
V
0.1
0.6
—
V
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
VT(UVLO)+
Increasing VCC
VT(UVLO)hys
ICC(ON)
Both bridges ON (forward or reverse)
—
—
50
mA
ICC(OFF)
All INPUTs = 2.4 V
—
—
9.0
mA
ICC(BRAKE)
All INPUTs = 0.8 V
—
—
95
mA
NOTES:1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968SA and
A3968SLB dual H-bridges are designed to bidirectionally
control two dc motors. An internal fixed-frequency PWM
current-control circuit controls the load current in each
motor. The current-control circuitry works as follows:
when the outputs of the H-bridge are turned on, current
increases in the motor winding. The load current is sensed
by the current-control comparator via an external sense
resistor (RS). Load current continues to increase until it
reaches the predetermined value, set by the selection of
external current-sensing resistors and reference input
voltage (VREF) according to the equation:
ITRIP = IOUT + ISO = VREF/(4RS)
where ISO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the sourceenable latch, turning off the source driver of that H-bridge.
The source turn off of one H-bridge is independent of the
other H-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp
diode. The current decreases until the internal clock
oscillator sets the source-enable latches of both H-bridges,
turning on the source drivers of both bridges. Load current
increases again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components RTCT. The frequency
can be approximately calculated as:
fosc = 1/(RT CT + tblank)
where tblank is defined below.
The range of recommended values for RT and CT are
20 kΩ to 100 kΩ and 470 pF to 1000 pF respectively.
Nominal values of 56 kΩ and 680 pF result in a clock
frequency of 25.4 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to
the reverse-recovery currents of the clamp diodes and
switching transients related to distributed capacitance in
the load. To prevent this current spike from erroneously
resetting the source enable latch, the current-control
comparator output is blanked for a short period of time
when the source driver is turned on. The blanking time is
set by the timing component CT according to the equation:
tblank = 1900 CT (µs).
A nominal CT value of 680 pF will give a blanking
time of 1.3 µs.
The current-control comparator is also blanked when
the load current changes polarity (direction or phase
change). This internally generated blank time is approximately 1.8 µs.
V
BB
V PHASE
See Enlargement A
BRIDGE
ON
+
I OUT
BRIDGE ON
ALL
OFF
0
SOURCE OFF
–
ALL OFF
BRIDGE
ON
I TRIP
Enlargement A
SOURCE
OFF
td
RS
t blank
INTERNAL
OSCILLATOR
R TC T
www.allegromicro.com
Dwg. WM-003-2
Dwg. EP-006-16
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL DESCRIPTION (continued)
Load Current Regulation. Due to internal logic and
switching delays (td), the actual load current peak may be
slightly higher than the ITRIP value. These delays, plus the
blanking time, limit the minimum value the current control
circuitry can regulate. To produce zero current in a
winding, the INPUTA and INPUTB terminals should be
held high, turning off all output drivers for that H-bridge.
Output Drivers. To minimize on-chip power dissipation, the sink drivers incorporate a Satlington structure.
The Satlington output combines the low VCE(sat) features
of a saturated transistor and the high peak-current capability of a Darlington (connected) transistor. A graph
showing typical output saturation voltages as a function
of output current is on the next page.
Logic Inputs. The direction of current in the motor
winding is determined by the state of the INPUTA and
INPUTB terminals of each bridge (see Truth Table). An
internally generated dead time (tcodt) of approximately
1.8 µs prevents cross-over current spikes that can occur
when switching the motor direction.
Miscellaneous Information. Thermal protection
circuitry turns off all output drivers should the junction
temperature reach +165°C (typical). This is intended
only to protect the device from failures due to excessive
junction temperatures and should not imply that output
short circuits are permitted. Normal operation is resumed
when the junction temperature has decreased about 15°C.
A logic high on both INPUTs turns off all four output
drivers of that H-bridge. This results in a fast current
decay through the internal ground clamp and flyback
diodes.
The appropriate INPUTA or INPUTB can be pulsewidth modulated for applications that require a fast current-decay PWM. The internal current-control logic can
be disabled by connecting the RTCT terminal to ground.
A logic low on the INPUTA and the INPUTB terminals
will place that H-Bridge in the brake mode. Both source
drivers are turned OFF and both sink drivers are turned
ON. This has the effect of shorting the dc motor’s backEMF voltage, resulting in a current flow that dynamically
brakes the motor.
Note that during braking the internal current-control
circuitry is disabled. Therefore, care should be taken to
ensure that the motor’s current does not exceed the absolute maximum rating of the A3968.
The REFERENCE input voltage is typically set with a
resistor divider from VCC. This reference voltage is
internally divided down by 4 to set up the current-comparator trip-voltage threshold. The reference input voltage
range is 0 to 2 V.
The A3968 current control employs a fixed-frequency, variable duty cycle PWM technique. If the duty
cycle exceeds 50%, the current-control-regulation frequency may change.
To minimize current-sensing inaccuracies caused by
ground trace IR drops, each current-sensing resistor
should have a separate return to the ground terminal of
the device. For low-value sense resistors, the I x R drops
in the printed-wiring board can be significant and should
be taken into account. The use of sockets should be
avoided as their contact resistance can cause variations in
the effective value of RS.
The LOAD SUPPLY terminal, VBB, should be
decoupled with an electrolytic capacitor (47 µF recommended) placed as close to the device as physically
practical. To minimize the effect of system ground I x R
drops on the logic and reference input signals, the system
ground should have a low-resistance return to the load
supply voltage.
The frequency of the clock oscillator will determine
the amount of ripple current. A lower frequency will
result in higher current ripple, but reduced heating in the
motor and driver IC due to a corresponding decrease in
hysteretic core losses and switching losses respectively.
A higher frequency will reduce ripple current, but will
increase switching losses and EMI.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
OUTPUT SATURATION VOLTAGE IN VOLTS
2.5
Typical output saturation
voltages showing Satlington
sink-driver operation.
TA = +25°C
2.0
SOURCE DRIVER
1.5
1.0
0.5
SINK DRIVER
0
200
300
400
500
600
700
OUTPUT CURRENT IN MILLIAMPERES
Dwg. GP-064-1A
TYPICAL APPLICATION
MOTOR 1
MOTOR 2
16
1
INPUT1A
2
INPUT1B
3
V
LOGIC
4
0.5 Ω
BB
LOGIC
15
INPUT2A
14
INPUT2B
13
5
12
6
11
0.5 Ω
V
7
47 μF
V
REF
+
10 kΩ
8
BB
Dwg. EP-047-6
www.allegromicro.com
VCC
10
RC
9
+5 V
680 pF
+24 V
56 kΩ
39 kΩ
+5 V
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
A3968SA (DIP)
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
0.775
0.735
8
0.005
BSC
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
19.68
18.67
BSC
8
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
NOTES:1.
2.
3.
4.
Dwg. MA-001-16A mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 25 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
A3968SLB (SOIC)
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
16
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
10.50
10.10
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
NOTES:1.
2.
3.
4.
Dwg. MA-008-16A mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Webbed lead frame. Leads 4 and 13 are internally one piece.
Supplied in standard sticks/tubes of 47 devices, or add “TR” to part number for tape and reel.
www.allegromicro.com
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending. Satlington® is a registered
trademark of Allegro MicroSystems, Inc. (Allegro), and Satlington
devices are manufactured under U. S. Patent No. 5,684,427.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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