Microchip MCP6G04-E/OT 110 î¼a selectable gain amplifier Datasheet

MCP6G01/1R/1U/2/3/4
110 µA Selectable Gain Amplifier
Features
Description
• 3 Gain Selections:
- +1, +10, +50 V/V
• One Gain Select Input per Amplifier
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max.)
• High Bandwidth: 250 kHz to 900 kHz (typ.)
• Low Supply Current: 110 µA (typ.)
• Single Supply: 1.8V to 5.5V
• Extended Temperature Range: -40°C to +125°C
The Microchip Technology Inc. MCP6G01/1R/1U/2/3/4
are analog Selectable Gain Amplifiers (SGA). They can
be configured for gains of +1 V/V, +10 V/V, and
+50 V/V through the Gain Select input pin(s). The Chip
Select pin on the MCP6G03 can put it into shutdown to
conserve power. These SGAs are optimized for single
supply applications requiring reasonable quiescent
current and speed.
Typical Applications
•
•
•
•
•
A/D Converter Driver
Industrial Instrumentation
Bar Code Readers
Metering
Digital Cameras
Package Types
MCP6G01
SOIC, MSOP
Block Diagram
NC 1
VDD
GSEL 2
VIN
VOUT
3
RF
RG
Gain Select
Logic
5 MΩ
Resistor Ladder
(RLAD)
Gain
Switches
GSEL
CS
VSS
Gain
(V/V)
VIN 3
VSS 4
8 NC
7 VDD
6 VOUT
5 NC
MCP6G01
SOT-23-5
VOUT 1
VSS 2
VIN 3
GSEL Voltage (Typ.)
(V)
1
VDD/2 (or open)
10
0
50
VDD
VSS is assumed to be 0V
© 2006 Microchip Technology Inc.
VOUT 1
VDD 2
VIN 3
4 GSEL
5 VSS
GSEL 2
VIN 3
VSS 4
VINA 3
VSS 4
8 CS
7 VDD
6 VOUT
5 NC
8 VDD
7 VOUTB
6 GSELB
5 VINB
MCP6G04
SOIC, TSSOP
VOUTA 1
GSELA 2
4 GSEL
VINA 3
14 VOUTD
13 GSELD
12 VIND
VDD 4
11 VSS
VINB 5
10 VINC
5 VDD GSELB 6
VOUTB 7
VSS 2
GSEL 3
NC 1
5 VDD VOUTA 1
GSELA 2
MCP6G01U
SOT-23-5
VIN 1
MCP6G03
SOIC, MSOP
MCP6G02
SOIC, MSOP
MCP6G01R
SOT-23-5
(MCP6G03
only)
Note:
The single amplifiers MCP6G01, MCP6G01R,
MCP6G01U, and MCP6G03, are available in 5-pin
SOT-23 package and the dual amplifier MCP6G02, are
available in 8-pin SOIC and MSOP packages. The
quad amplifier MCP6G04 is available in 14-pin SOIC
and TSSOP packages. All parts are fully specified from
-40°C to +125°C.
9 GSELC
8 VOUTC
4 VOUT
DS22004B-page 1
MCP6G01/1R/1U/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Analog Input Pin (VIN) ......................................±2 mA
Analog Input (VIN) †† ..................... VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS – 0.3V to VDD + 0.3V
Output Short Circuit Current...................................continuous
Current at Output and Supply Pins ................................ ±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature.................................................. +150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.4 “Input Voltage and Current Limits”.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL = 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
VOS
Units
Conditions
–4.5
±1.0
+4.5
mV
G = +1
—
±1.0
—
mV
G = +10, +50
ΔVOS/ΔTA
—
±2
—
µV/°C
PSRR
65
80
—
dB
Input Bias Current
IB
—
1
—
pA
Input Bias Current at
IB
—
30
—
pA
TA = +85°C
TA = +125°C
Amplifier Inputs (VIN)
Input Offset Voltage
Input Offset Voltage Drift
Power Supply Rejection Ratio
G = +1, TA = -40°C to +125°C
G = +1 (Note 1)
IB
—
1000
5000
pA
ZIN
—
1013||6
—
Ω||pF
G
—
1 to 50
—
V/V
gE
–0.3
—
+0.3
%
VOUT ≈ 0.3V to VDD − 0.3V
gE
–1.0
—
+1.0
%
VOUT ≈ 0.3V to VDD − 0.3V
G = +1
ΔG/ΔTA
—
±1
—
ppm/°C
TA = -40°C to +125°C
G ≥ +10
ΔG/ΔTA
—
±4
—
ppm/°C
TA = -40°C to +125°C
Temperature
Input Impedance
Amplifier Gain
Nominal Gains
DC Gain Error G = +1
G ≥ +10
DC Gain Drift
+1, +10 or +50
Ladder Resistance (Note 1)
Ladder Resistance
Ladder Resistance
across Temperature
RLAD
200
350
500
kΩ
ΔRLAD/ΔTA
—
–1800
—
ppm/°C
VONL
–0.2
—
+0.2
% of FSR VOUT = 0.3V to VDD – 0.3V,
VDD = 1.8V
VONL
–0.1
—
+0.1
% of FSR VOUT = 0.3V to VDD – 0.3V,
VDD = 5.5V
% of FSR VOUT = 0.3V to VDD – 0.3V
TA = -40°C to +125°C
Amplifier Output
DC Output Non-linearity
G = +1
DC Output Non-linearity, G = +10, +50
Maximum Output Voltage Swing
Short Circuit Current
Note 1:
2:
VONL
–0.05
—
+0.05
VOH, VOL
VSS+10
—
VDD–10
mV
VOH, VOL
VSS+10
—
VDD–10
mV
G ≥ +10; 0.5V output overdrive
ISC
—
±7
—
mA
VDD = 1.8V
ISC
—
±20
—
mA
VDD = 5.5V
G = +1; 0.3V output overdrive
RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
DS22004B-page 2
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL = 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
VDD
1.8
—
5.5
V
IQ
60
110
170
µA
Conditions
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
IO = 0 (Note 2)
RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Frequency Response
-3dB Bandwidth
Gain Peaking
BW
—
900
—
kHz
G = +1, VOUT < 100 mVP-P (Note 1)
BW
—
350
—
kHz
G = +10, VOUT < 100 mVP-P (Note 1)
BW
—
250
—
kHz
G = +50, VOUT < 100 mVP-P (Note 1)
GPK
—
0.3
—
dB
G = +1; VOUT < 100 mVP-P
GPK
—
0
—
dB
G = +10, VOUT < 100 mVP-P
GPK
—
0.7
—
dB
G = +50; VOUT < 100 mVP-P
f = 1 kHz, G = +1 V/V
THD+N
—
0.0029
—
%
VOUT = 1.75V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
f = 1 kHz, G = +10 V/V
THD+N
—
0.18
—
%
VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
f = 1 kHz, G = +50 V/V
THD+N
—
1.3
—
%
VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
Total Harmonic Distortion plus Noise
Step Response
Slew Rate
SR
—
0.50
—
V/µs
G=1
SR
—
2.3
—
V/µs
G = 10
SR
—
4.5
—
V/µs
G = 50
Eni
—
9
—
µVP-P
f = 0.1 Hz to 10 Hz (Note 2)
Eni
—
50
—
µVP-P
f = 0.1 Hz to 30 kHz (Note 2)
eni
—
38
—
nV/√Hz G = +1 V/V, f = 10 kHz (Note 2)
eni
—
46
—
nV/√Hz G = +10 V/V, f = 10 kHz (Note 2)
eni
—
41
—
nV/√Hz G = +50 V/V, f = 10 kHz (Note 2)
ini
—
4
—
fA/√Hz f = 10 kHz
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Note 1:
2:
See Table 4-1 for a list of typical numbers and Figure 2-31 for the frequency response versus gain.
Eni and eni include ladder resistance thermal noise.
© 2006 Microchip Technology Inc.
DS22004B-page 3
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VCSL
0
—
0.2VDD
V
CS = 0V
CS Input Current, Low
ICSL
—
30
—
pA
CS = 0V
CS Logic Threshold, High
VCSH
0.8VDD
—
VDD
V
CS = VDD
CS Input Current, High
ICSH
—
0.8
—
µA
CS = VDD = 5.5V
Quiescent Current per Amplifier,
Shutdown Mode (IDD)
IDD_SHDN
—
120
—
pA
CS = VDD, MCP6G03
Quiescent Current per Amplifier,
Shutdown Mode (ISS) (Note 3)
ISS_SHDN
—
–2.4
—
µA
CS = VDD = 1.8V, MCP6G03
ISS_SHDN
—
–7.2
—
µA
CS = VDD = 5.5V, MCP6G03
CCS
—
10
—
pF
Input Rise/Fall Times
tCSRF
—
—
2
µs
(Note 2)
CS Low to Amplifier Output High
Turn-on Time
tCSON
—
40
—
µs
G = +1 V/V, VDD = 1.8V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
tCSON
—
7
—
µs
G = +1 V/V, VDD = 5.5V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
CS High to Amplifier Output High-Z
Turn-off Time
tCSOFF
—
30
—
µs
G = +1 V/V, VIN = VDD/2,
CS = 0.8VDD to VOUT = 0.1VDD/2
Hysteresis
VCSHY
—
0.40
—
V
VDD = 1.8V
VCSHY
—
0.55
—
V
VDD = 5.5V
GSEL Logic Threshold, Low
VGSL
0.15VDD
—
0.35VDD
V
Gain changes between 1 and 10,
IGSEL = 0
GSEL Logic Threshold, High
VGSH
0.65VDD
—
0.85VDD
V
Gain changes between 1 and 50,
IGSEL = 0
GSEL Input Current, Low
IGSL
–10
—
–1.5
µA
GSEL voltage = 0.3VDD
GSEL Input Current, High
IGSH
+1.5
—
+10
µA
GSEL voltage = 0.7VDD
—
8
—
pF
CS Low Specifications
CS High Specifications
CS Dynamic Specifications
Input Capacitance
GSEL Specifications (Note 1)
GSEL Dynamic Specifications (Note 1)
Input Capacitance
CGSEL
Input Rise/Fall Times
tGSRF
—
—
10
µs
(Note 2)
Hysteresis
VGSHY
—
45
—
mV
VDD = 1.8V
VGSHY
—
95
—
mV
VDD = 5.5V
tGSL1
—
10
—
µs
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 1.37V
GSEL Middle to Valid Output Time,
G = +10 to +1 Select
tGSM10
—
12
—
µs
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 0.28V
GSEL High to Valid Output Time,
G = +1 to +50 Select
tGSH1
—
9
—
µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.35V
GSEL Middle to Valid Output Time,
G = +50 to +1 Select
tGSM50
—
8
—
µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 0.18V
GSEL Low to Valid Output Time,
G = +1 to +10 Select
Note 1:
2:
3:
GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
Not tested in production. Set by design and characterization.
ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block diagram on the from page shows these current paths (through VSS).
DS22004B-page 4
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
GSEL High to Valid Output Time,
G = +10 to +50 Select
tGSH10
—
12
—
µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.38V
GSEL Low to Valid Output Time,
G = +50 to +10 Select
tGSL50
—
9
—
µs
VIN = 30 mV,
GSEL = 0.25VDD to VOUT = 0.42V
Note 1:
2:
3:
Conditions
GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
Not tested in production. Set by design and characterization.
ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block diagram on the from page shows these current paths (through VSS).
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
–40
—
+125
°C
Operating Temperature Range
TA
–40
—
+125
°C
Storage Temperature Range
TA
–65
—
+150
°C
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1:
VIN
The MCP6G01/1R/1U/2/3/4 family of SGAs operates over this temperature range, but operation must not cause TJ to
exceed Maximum Junction Temperature (+150°C).
0.150V
0.030V
GSEL
tGSL1
tGSM10
tGSH1
1.50V
VOUT
FIGURE 1-1:
tGSH10
1.50V
0.15V
0.15V
tGSM50
1.50V
0.30V
0.03V
tGSL50
0.30V
0.03V
Gain Select Timing Diagram.
© 2006 Microchip Technology Inc.
DS22004B-page 5
MCP6G01/1R/1U/2/3/4
CS
tCSON
VOUT
IDD
ISS
ICS
FIGURE 1-2:
DS22004B-page 6
tCSOFF
0.9VDD
High-Z
High-Z
110 µA (typ.)
120 pA (typ.)
–VDD / 7 MΩ (typ.)
–110 µA (typ.)
VDD / 7 MΩ (typ.)
30 pA (typ.)
SGA Chip Select Timing Diagram.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
1.1
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
The ideal SGA output voltage (VOUT) is (see Figure 1-3):
The DC Gain Drift (ΔG/ΔTA) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
EQUATION 1-4:
EQUATION 1-1:
Δg E
ΔG ⁄ ΔT A = G ⋅ ---------- ,
ΔT A
V O_ID = GV IN
in units of V/V/°C
Δg E
ΔG ⁄ ΔT A = 100% ⋅ ---------- ,
ΔT A
Where:
G is the nominal gain
in units of %/°C
V REF = V SS = 0V
VOUT (V)
This equation holds when there are no gain or offset
errors.
1.1.2
LINEAR MODEL
The SGA’s linear region of operation is modeled by the
line VO_LIN shown in Figure 1-3. VO_LIN includes offset
and gain errors, but does not include non-linear effects.
VDD
V2
VDD-0.3
V
T
OU
VO
IN
_L
D
_I
VO
V1
EQUATION 1-2:
0.3
V O_LIN = G ( 1 + g E ) ⎛ V IN – 0.3V
------------ + V OS⎞ + 0.3V
⎝
⎠
G
0
VIN (V)
0.3
G
0
Where:
G is the nominal gain
FIGURE 1-3:
gE is the gain error
VDD-0.3 VDD
G
G
Output Voltage Model.
VOS is the input offset voltage
1.1.3
V REF = V SS = 0V
Figure 1-4 shows the Integral Non-Linearity (INL) of the
output voltage. INL is the output non-linearity error not
explained by VO_LIN:
This line’s endpoints are 0.3V from the supply rails
(VO_ID = 0.3V and VDD – 0.3V). The gain error and
input offset voltage specifications (in the electrical
specifications) relate to Figure 1-3 as follows:
EQUATION 1-3:
V2 – V1
g E = 100% ⋅ ----------------------------V DD – 0.6V
V1
V OS = ------------------------- ,
G ( 1 + gE )
OUTPUT NON-LINEARITY
EQUATION 1-5:
INL = V OUT – V O_LIN
The output non-linearity specification (in the Electrical
Specifications, with units of % of FSR) is related to
Figure 1-4 by:
EQUATION 1-6:
G = +1
Where:
V 1 = V OUT – V O_ID ,
V O_ID = 0.3V
V 2 = V OUT – V O_ID ,
V O_ID = V DD – 0.3V
The input offset specification describes VOS at
G = +1 V/V.
© 2006 Microchip Technology Inc.
max ( V 3, V 4 )
V ONL = 100% ⋅ ------------------------------V DD – 0.6V
Where:
V 3 = max ( – INL )
V 4 = max ( INL )
Note that the Full Scale Range (FSR) is VDD – 0.6V
(0.3V to VDD – 0.3V).
DS22004B-page 7
MCP6G01/1R/1U/2/3/4
INL (V)
V4
0
V3
0
0.3
G
FIGURE 1-4:
DS22004B-page 8
VDD-0.3 VDD
G
G
VIN (V)
Output Voltage INL.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
6%
4%
2%
FIGURE 2-4:
© 2006 Microchip Technology Inc.
5
4
14
12
10
8
6
12
10
8
6
4
2
0
-2
-4
-6
-8
1612 Samples
G = +1, +10, +50
TA = -40 to +125°C
-12
Percentage of Occurrences
4.5
3.5
2.5
1.5
0.5
-0.5
-1.5
-2.5
-3.5
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Input Offset Voltage (mV)
Input Offset Voltage.
DC Gain Drift, G ≥ +10.
FIGURE 2-5:
-10
DC Gain Error, G ≥ +10.
G = +50
G = +10
G = +1
FIGURE 2-3:
4
DC Gain Drift (ppm/°C)
2460 Samples
-4.5
Percentage of Occurrences
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
2
0%
DC Gain Error (%)
FIGURE 2-2:
3
2%
-14
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0%
4%
0
2%
6%
-2
4%
8%
-6
6%
10%
-8
8%
4912 Samples
G ≥ +10
TA = -40 to +125°C
12%
-10
10%
14%
-12
4916 Samples
G ≥ +10
DC Gain Drift, G = +1.
-4
DC Gain Error, G = +1.
Percentage of Occurrences
12%
-0.7
Percentage of Occurrences
14%
2
DC Gain Drift (ppm/°C)
DC Gain Error (%)
FIGURE 2-1:
1
0%
0
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0.00
-0.04
-0.08
-0.12
-0.16
-0.20
-0.24
0%
8%
-1
5%
10%
-2
10%
12%
2459 Samples
G = +1
TA = -40 to +125°C
-3
15%
14%
-4
20%
16%
-5
25%
18%
2460 Samples
G = +1
Percentage of Occurrences
30%
-0.28
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Input Offset Voltage Drift (µV/°C)
FIGURE 2-6:
Input Offset Voltage Drift.
DS22004B-page 9
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
VIN
5
VDD = 5.0V
G = +1 V/V
VOUT
4
3
2
1
0
-10.0E+00
1.0E-03
2.0E-03
3.0E-03
4.0E-03
5.0E-03
6.0E-03
7.0E-03
8.0E-03
9.0E-03
0
-10
RS = 1 MΩ
-20 R = 100 kΩ
S
-30
RS = 10 kΩ
-40
-50
-60
-70
-80
-90
-100
-110
-120
1k
1.E+03
1.0E-02
Time (1 ms/div)
FIGURE 2-7:
The MCP6G01/1R/1U/2/3/4
family shows no phase reversal under overdrive.
PSRR (dB)
110
100
90
80
70
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-8:
100
125
PSRR vs. Temperature.
FIGURE 2-9:
vs. Frequency.
DS22004B-page 10
Quiescent Current (mA)
Input Noise Voltage Density
(nV/—Hz)
G = +1
= +10
= +50
10k
1.E+04
Frequency (Hz)
Input Referred
80
100k
1.E+05
VDD = 5.5V
G = 50
70
60
50
G = 10
40
VDD = 1.8V
30
G=1
20
100
100
160
100
10
0.1
0.1
90
1k
10k
1000
10000
Frequency (Hz)
FIGURE 2-11:
10000
1000
RS = 0 Ω
FIGURE 2-10:
Crosstalk vs. Frequency,
with G = 50 (circuit in Figure 4-7).
Power Supply Rejection Ratio
(dB)
120
VDD = 5.0V
G = 50 V/V
Crosstalk, Input Referred
(dB)
Input, Output Voltage (V)
6
140
100k
100000
PSRR vs. Frequency.
TA = +125°C
TA = +85°C
120
100
80
60
TA = +25°C
TA = –40°C
40
20
0
1
1
10
100
1k
10k 100k
10
100 1000 10000 10000
Frequency (Hz)
0
Input Noise Voltage Density
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-12:
Supply Voltage.
Quiescent Current vs.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
In Shutdown Mode
VIN = VDD/2
CS = VDD
-2
-3
ISS_SHDN
-4
-5
-6
-7
0
-8
-2
-3
VDD = 1.8V
-4
-5
-6
VDD = 5.5V
-7
-8
-9
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-13:
Quiescent Current (ISS) in
Shutdown Mode vs. Supply Voltage.
1,000
VDD = 5.5V
VIN = VDD
100
10
1
55
65
75
85
95
105
115
125
-25
1.E-02
10m
1.E-03
1m
1.E-04
100µ
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
VDD = 5.5V
1,000
TA = +125°C
100
TA = +85°C
10
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
FIGURE 2-15:
Voltage.
Input Bias Current vs. Input
© 2006 Microchip Technology Inc.
125
+125°C
+85°C
+25°C
-40°C
Input Voltage (V)
FIGURE 2-17:
Voltage.
Output Short Circuit Current
Magnitude (mA)
Input Bias Current (pA)
10,000
Input Bias Current vs.
100
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Ambient Temperature (°C)
FIGURE 2-14:
Temperature.
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-16:
Quiescent Current (ISS) in
Shutdown Mode vs. Temperature.
Input Current Magnitude (A)
Input Bias Current (pA)
In Shutdown Mode
VIN = VDD/2
-1
Quiescent Current in
Shutdown (µA)
Quiescent Current in
Shutdown (µA)
0
-1
30
25
20
Input Bias Current vs. Input
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-18:
Output Short Circuit Current
vs. Supply Voltage.
DS22004B-page 11
MCP6G01/1R/1U/2/3/4
VDD = +1.8V
Representative Part
1
0
G = +1
-1
G = +10
G = +50
-2
-3
0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6
Ideal Output Voltage; GVIN (V)
G = +10
G = +50
-1
-2
-3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ideal Output Voltage; GVIN (V)
FIGURE 2-22:
Output Voltage Error vs.
Ideal Output Voltage, with VDD = 5.5V.
4.0
1000
Output Voltage Headroom;
VDD–V OH and V OL–V SS (mV)
VDD = +1.8V
VDD – VOH
VDD = +5.5V
VOL – VSS
1
0.01
0.1
1
Output Current Magnitude (mA)
10k
1.E+04
1k
1.E+03
DS22004B-page 12
1.0
VDD = 1.8V: VOL–VSS
VDD–VOH
0.5
0.0
-50
-25
FIGURE 2-23:
vs. Temperature.
Percentage of Occurrences
G = 50
= 10
= 1
FIGURE 2-21:
Frequency.
1.5
0
25
50
75
100
125
Ambient Temperature (°C)
100k
1.E+05
100k
1M
1.E+05
1.E+06
Frequency (Hz)
2.0
10
FIGURE 2-20:
Output Voltage Headroom
vs. Output plus Ladder Current (circuit in
Figure 4-4).
100
1.E+02
10k
1.E+04
2.5
10M
1.E+07
Output Impedance vs.
Output Voltage Headroom
14%
1228 Samples
TA = -40 to +125°C
12%
10%
8%
6%
4%
2%
0%
-1500
10
3.0
-1600
100
VDD = 5.5V: VDD–VOH
VOL–VSS
3.5
-1700
Output Voltage Headroom;
VDD – V OH and V OL – V SS (mV)
G = +1
0
1.8
FIGURE 2-19:
Output Voltage Error vs.
Ideal Output Voltage, with VDD = 1.8V.
Output Impedance Magnitude
(ȍ)
1
-1800
0.0
VDD = +5.5V
Representative Part
2
-1900
2
3
-2000
3
Output Error, Input Referred;
VOUT /G – V IN (mV)
Output Error, Input Referred;
VOUT /G – V IN (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Ladder Resistance Drift (ppm/°C)
FIGURE 2-24:
Ladder Resistance Drift.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Slew Rate (V/µs)
0.6
G = +1 V/V
0.5
VDD = 5.5V
Output Voltage Swing (V
0.7
P-P )
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Falling Edge
0.4
0.3
VDD = 1.8V
0.2
Rising Edge
0.1
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-25:
with G = +1.
0.1 1.E+03
1k
1.E+04
10k
1.E+05
1.E+06
100k
1M
Falling Edge
Rising Edge
0.5
Output Voltage Swing vs.
G = +50 V/V
3.5
1.5
VDD = 5.5V
3.0
Falling Edge
2.5
2.0
Rising Edge
1.5
1.0
0.5
0.0
0.0
-50
-25
FIGURE 2-26:
with G = +10.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Temperature,
-50
-25
FIGURE 2-29:
with G = +50.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Temperature,
1.E+06
1M
1M
1.E+06
G = +1
G = +1
G = +10
G = +50
Bandwidth (Hz)
Bandwidth (Hz)
G = +1
G = +10
G = +50
4.0
VDD = 5.5V
1.0
VDD = 1.8V
1
FIGURE 2-28:
Frequency.
G = +10 V/V
2.0
VDD = 5.5V
Frequency (Hz)
Slew Rate vs. Temperature,
2.5
Slew Rate (V/µs)
125
Slew Rate (V/µs)
3.0
100
10
100k
1.E+05
10k
1.E+04
100
1.E+02
FIGURE 2-27:
Load.
10k
1k
1.E+03
1.E+04
Resistive Load (ȍ)
100k
1.E+05
Bandwidth vs. Resistive
© 2006 Microchip Technology Inc.
100k
1.E+05
10
FIGURE 2-30:
Load.
G = +10
G = +50
100
Capacitive Load (pF)
1000
Bandwidth vs. Capacitive
DS22004B-page 13
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
40
7
30
G = +50
6
Gain Peaking (dB)
Gain (dB)
20
G = +10
10
0
G = +1
-10
-20
4
3
2
1
-30
0
100k
1M
1.E+05
1.E+06
Frequency (Hz)
FIGURE 2-31:
10M
1.E+07
1
Normalized Input
Voltage (100 mV/div)
1
Output Voltage
(20 mV/div)
1
1
VOUT
G = +50
G = +10
G = +1
1
0
0
GVIN
5.00
10.00
15.00
FIGURE 2-32:
Response.
20.00
25.00
30.00
Time (5 µs/div)
35.00
40.00
45.00
50.00
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
Gain Peaking vs. Capacitive
VDD = +5.0V
GVI
VOUT
G = +1
G = +10
G = +50
0.00
5.00
10.00
FIGURE 2-35:
Response.
Small Signal Pulse
15.00
20.00
25.00
30.00
Time (5 µs/div)
35.00
40.00
45.00
50.00
Large Signal Pulse
10
10
1
G = +10
0.1
0.01
G = +1
VOUT = 2.8VP-P
VDD = 5.0V
THD + Noise (%)
G = +50
THD + Noise (%)
100
Capacitive Load (pF)
FIGURE 2-34:
Load.
Gain vs. Frequency.
VDD = +5.0V
0.00
10
Normalized Input Voltage,
Output Voltage (V)
-40
10k
1.E+04
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G = +1
G = +10
G = +50
5
1
G = +50
G = +10
0.1
G = +1
0.01
Measurement BW = 80 kHz
0.001
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
FIGURE 2-33:
THD plus Noise vs.
Frequency, VOUT = 2.8 VP-P.
DS22004B-page 14
100k
1.E+05
0.001
100
1.E+02
VOUT = 4 VP-P
VDD = 5.0V
Measurement BW = 80 kHz
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
FIGURE 2-36:
THD plus Noise vs.
Frequency, VOUT = 4.0 VP-P.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
10
G = +50
G = +1
VOUT = 0.8VDD
f = 1 kHz
Measurement BW = 80 kHz
0.01
0.001
1.5
2.0
2.5 3.0 3.5 4.0 4.5
Power Supply Voltage (V)
FIGURE 2-37:
Voltage.
5.0
THD plus Noise vs. Load
10
G = +10
0.1
G = +1
VDD = 5.0V
f = 1 kHz
0.01
Measurement BW = 80 kHz
Output Voltage (V)
1
4.0
GSEL
VDD = 5.0V
VIN = 0.030V
3.5
3.0
1
10
55
00
4.0
GSEL
3.5
-5
VDD = 5.0V
VIN = 0.15V
3.0
2.5
2.0
(G = +10)
-10
-15
VOUT
1.5
-20
(G = +10)
-25
-30
1.0
(G = +1)
0.5
0
10
20
FIGURE 2-39:
Gain = 1 and 10.
30
40
50
60
70
Time (10 µs/div)
80
90
100
© 2006 Microchip Technology Inc.
-25
(G = +50)
1.0
-30
(G = +1)
0
10
20
-35
(G = +1)
30
FIGURE 2-41:
Gain = 1 and 50.
40
50
60
70
80
Time (10 µs/div)
90
100
10
4.5
55
00
GSEL
4.0
3.5
-5
VDD = 5.0V
VIN = 0.030V
3.0
-10
-15
2.5
VOUT
2.0
1.5
-40
0.0
-20
-25
(G = +50)
1.0
0.5
-40
Gain Select Timing, with
5.0
-35
Gain Select Timing, with
-20
VOUT
1.5
0.0
Output Voltage (V)
10
4.5
Gain Select Voltage (V)
5.0
-10
-15
2.0
Output Swing (VP-P)
THD plus Noise vs. Output
-5
2.5
0.5
FIGURE 2-38:
Swing.
55
00
4.5
0.001
Output Voltage (V)
1M
1.E+06
5.0
G = +50
0.0
10k
100k
1.E+04
1.E+05
Load Resistance (Ω)
FIGURE 2-40:
Resistance.
10
THD + Noise (%)
G = +1
f = 1 kHz
VDD = 5.0V
Measurement BW = 80 kHz
0.01
0.001
1k
1.E+03
5.5
THD plus Noise vs. Supply
G = +10
0.1
Gain Select Voltage (V)
G = +10
0.1
G = +50
1
Gain Select Voltage (V)
1
THD + Noise (%)
THD + Noise (%)
10
(G = +10)
0
10
20
FIGURE 2-42:
Gain = 1 and 10.
-30
-35
(G = +10)
30
40
50
60
70
Time (10 µs/div)
80
90
100
-40
Gain Select Timing, with
DS22004B-page 15
MCP6G01/1R/1U/2/3/4
Shutdown
G=1
G = 10
G = 50
CS
1.8
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VOUT is "ON"
Shutdown
G=1
G = 10
G = 50
CS
Time (20 µs/div)
FIGURE 2-46:
Output Voltage vs. Chip
Select, with VDD = 5.0V.
1.8
GSEL Current (µA)
FIGURE 2-45:
GSEL Current, with GSEL
Voltage of 0.3VDD.
DS22004B-page 16
1228 Samples
GSEL = 0.7VDD
7.0
VDD = 5.5V
6.6
VDD = 1.8V
6.2
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
5.8
-3.0
-3.4
-3.8
-4.2
-4.6
-5.0
VDD = 1.8V
-5.4
-5.8
-6.2
VDD = 5.5V
FIGURE 2-47:
GSEL Pin Current vs. GSEL
Voltage, with VDD = 5.5V.
Percentage of Occurrences
1228 Samples
GSEL = 0.3VDD
-6.6
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-7.0
Percentage of Occurrences
FIGURE 2-44:
GSEL Pin Current vs. GSEL
Voltage, with VDD = 1.8V.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
GSEL Voltage (V)
5.4
1.6
5.0
1.4
TA = +125°C
= +85°C
= +25°C
4.6
0.6 0.8 1.0 1.2
GSEL Voltage (V)
TA = +25°C
= +85°C
= +125°C
3.8
0.4
VDD = 5.5V
3.4
0.2
TA = +125°C
= +85°C
= +25°C
10
8
6
4
2
0
-2
-4
-6
-8
-10
3.0
0.0
GSEL Current (µA)
GSEL Current (µA)
VDD = 1.8V
TA = +25°C
= +85°C
= +125°C
5
0
Time (20 µs/div)
FIGURE 2-43:
Output Voltage vs. Chip
Select, with VDD = 1.8V.
10
8
6
4
2
0
-2
-4
-6
-8
-10
VDD = 5.0V
VIN = 0.9VDD
Chip Select Voltage (V)
VDD = 1.8V
VIN = 0.9VDD
4.2
VOUT is "ON"
Output Voltage (mV)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
Chip Select Voltage (V)
Output Voltage (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
GSEL Current (µA)
FIGURE 2-48:
GSEL Current, with GSEL
Voltage of 0.7VDD.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Normalized GSEL Trip Point; VGSEL/VDD
FIGURE 2-49:
GSEL Trip Point between
G = +1 and G = +10.
© 2006 Microchip Technology Inc.
1228 Samples
G = +1 to +50
0.773
0.768
0.764
0.759
VDD = 1.8V
0.755
0.750
0.745
VDD = 5.5V
0.741
0.259
0.255
0.250
0.245
0.241
VDD = 5.5V
0.236
0.231
0.227
0.222
VDD = 1.8V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.736
Percentage of Occurrences
1227 Samples
G = +1 to +10
0.218
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.213
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Normalized GSEL Trip Point; VGSEL/VDD
FIGURE 2-50:
GSEL Trip Point between
G = +1 and G = +50.
DS22004B-page 17
MCP6G01/1R/1U/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6G01
(SOIC,
MSOP)
MCP6G01
(SOT-23-5)
MCP6G01R
(SOT-23-5)
MCP6G01U
(SOT-23-5)
MCP6G03
Symbol
6
1
1
4
6
VOUT
Analog Output
2
4
4
3
2
GSEL
Gain Select Input
3
3
3
1
3
VIN
Analog Input
7
5
2
5
7
VDD
Positive Power Supply
4
2
5
2
4
VSS
Negative Power Supply
—
—
—
—
8
CS
Chip Select
1,5,8
—
—
—
1,5
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6G02
MCP6G04
Symbol
1
1
VOUTA
Analog Output A
2
2
GSELA
Gain Select Input (SGA A)
3
3
VINA
Analog Input A
8
4
VDD
Positive Power Supply
5
5
VINB
Analog Input B
6
6
GSELB
Gain Select Input (SGA B)
7
7
VOUTB
Analog Output B
—
8
VOUTC
Analog Output C
—
9
GSELC
Gain Select Input (SGA C)
—
10
VINC
Analog Input C
4
11
VSS
Negative Power Supply
—
12
VIND
Analog Input D
—
13
GSELD
Gain Select Input (SGA D)
—
14
VOUTD
Analog Output D
3.1
Description
Analog Output
The output pin (VOUT) is a low impedance voltage
source. The selected gain (G) and input voltage (VIN)
determine its value.
3.2
Analog Input
The analog inputs (VIN) are high impedance CMOS
inputs with low bias currents. Only three fixed, noninverting gains are available through these inputs.
3.3
Power Supply (VSS and VDD)
The Positive Power Supply Pin (VDD) is 1.8V to 5.5V
higher than the Negative Power Supply Pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
DS22004B-page 18
Description
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground, and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (typically 1.0 µF to 10 µF) within
100 mm of the VDD pin; it can be shared with nearby
analog parts.
3.4
Digital Inputs
The Chip Select (CS) input is a Schmitt-triggered,
CMOS logic input.
The Gain Select (GSEL) inputs are tri-level digital
inputs. They function similar to normal logic inputs at
low (G = +10) and high voltages (G = +50). The pin can
also be set to mid-supply (G = +1) by a low impedance
source, or by leaving this pin open.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
4.0
APPLICATIONS INFORMATION
The MCP6G01/1R/1U/2/3/4 family of Selectable Gain
Amplifiers (SGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
VDD
VIN
VOUT
3
RG
Gain Select
Logic
GSEL
RF
5 MΩ
Resistor Ladder
(RLAD)
Gain
Switches
TABLE 4-1:
Gain
(V/V)
Gain
(V/V)
GSEL Voltage (Typ.)
(V)
1
VDD/2 (or open)
10
0
50
VDD
Note:
VSS is assumed to be 0V
FIGURE 4-1:
4.1
SGA Block Diagram.
4.1.1
COMPENSATION CAPACITORS
The internal op amp has three compensation
capacitors (comp. caps.) connected to a switching
network. They are selected to give good small signal
bandwidth at high gains, and good slew rate (full power
bandwidth) at low gains. The change in bandwidth as
gain changes is between 250 and 900 kHz. Refer to
Table 4-1 for more information.
© 2006 Microchip Technology Inc.
BW
(kHz)
Typ.
Large
0.90
0.50
29
900
Medium
3.5
2.3
133
350
50
Small
12.5
4.5
260
250
Note 1:
2:
3:
4:
Changing the compensation capacitor does not
change the DC performance (e.g., VOS).
G x BW is approximately the Gain Bandwidth
Product of the internal op amp.
FPBW is the Full Power Bandwidth at
VDD = 5.5V, which is based on slew rate (SR).
BW is the closed-loop, small signal –3 dB
bandwidth.
RAIL-TO-RAIL INPUTS
The input stage of the internal op amp uses two
differential input stages in parallel; one operates at low
VIN (input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail, although the output will clip
the signal before that happens.
The inputs need to be kept within a smaller range to
prevent output clipping. The input offset voltage also
reduces the range; most designs will need the following
for normal operation:
EQUATION 4-1:
V OL
V OH
---------- + V OS < V IN < ---------- – V OS
G
G
Internal Op Amp
The internal op amp gives the right combination of
bandwidth, accuracy, and flexibility.
FPBW
(kHz)
Typ.
1
4.1.2
VSS
Internal G x BW
SR
Comp.
(MHz) (V/µs)
Cap.
Typ.
Typ.
10
CS
(MCP6G03
only)
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
The transition between the two input stage occurs
when VIN ≈ VDD – 1.1V (see Figure 2-19 and Figure 222). For the best distortion and gain linearity, avoid this
region of operation.
4.1.3
PHASE REVERSAL
The MCP6G01/1R/1U/2/3/4 amplifier family is
designed with CMOS input devices. It is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages. Figure 2-7 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
DS22004B-page 19
MCP6G01/1R/1U/2/3/4
4.1.4
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
VDD Bond
Pad
current into the input pin (VIN) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-17. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.5
RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (IOUT) and the current through the ladder
resistance (ILAD); see Figure 4-4.
EQUATION 4-2:
VIN Bond
Pad
Input
Stage
Amplifier Load Current = I OUT + I LAD
to the rest of
the amplifier
Where:
( V OUT – V SS )
I LAD = -------------------------------R LAD
VSS Bond
Pad
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
VIN
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN pins (see Section
“Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN) from going too far below ground, and the resistor
R1 limits the possible current drawn out of the input pin.
Diode D1 prevents the input pin (VIN) from going too far
above VDD. When implemented as shown, resistor R1
also limits the current through D1.
VDD
V1
R1
VIN
MCP6G0X
VOUT
VSS – (minimum expected V1)
2 mA
FIGURE 4-3:
Inputs.
Protecting the Analog
It is also possible to connect the diode to the left of the
resistor R1. In this case, the current through the diode
D1 needs to be limited by some other mechanism. The
resistor then serves as in-rush current limiter; the DC
DS22004B-page 20
VOUT
MCP6G0X
ILAD
RLAD
VSS
FIGURE 4-4:
Amplifier Load Current.
See Figure 2-20 for the typical output headroom
(VDD – VOH or VOL – VSS) as a function of amplifier
load current.The specification table states the output
can reach within 10 mV of either supply rail when
RL = 100 kΩ.
4.2
D1
R1 ≥
IOUT
Resistor Ladder
The
resistor
ladder
shown
in
Figure 4-1
(RLAD = RF + RG) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion, and gain mismatch.
RLAD is an additional load on the output of the SGA and
causes additional current draw from the supplies.
When CS is high, the SGA is shut down (low power).
RLAD is still attached to the VOUT and VSS pins. Thus,
these pins and the internal amplifier’s inverting input
are all connected through RLAD and the output is not
high-Z (unlike the internal op amp).
RLAD contributes to the output noise; see Figure 2-9.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
RLAD is intended to be driven at the VSS pin by a low
impedance voltage source. The power supply driving
the VSS pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy.
4.3
TABLE 4-3:
Selected Gain
Figure 1-2 and Figure 2-43 show how the output
voltage and supply current response to a CS pulse.
4.4
Gain Select (GSEL)
The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see
Table 4-1). Table 4-2 shows how to change the gain
using a GPIO pin on a microcontroller and Table 4-3
shows how to hard wire the gain (i.e., using PCB
wiring).
TABLE 4-2:
Gain
+1 V/V
MCU DRIVEN GAIN
SELECTION
Open Circuit (Note 1)
+10 V/V
Tied to GND (0V)
+50 V/V
Tied to VDD
Low impedance source at VDD/2
Note 1:
4.5
The GSEL pin floats to mid-supply
(VDD/2); a bypass capacitor may be
needed.
Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/1R/1U/2/3/4
family of SGAs (Figure 2-30 and Figure 2-34). As the
load capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(RISO in Figure 4-5) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
RISO
VIN
MCP6G0X
VOUT
CL
MCU Pin’s State
Output PIC’s VREF at VDD/2
Digital Output High-Z (Notes 1)
Output VDD/2 PWM signal (Notes 2)
+10 V/V
Digital Output driven Low
+50 V/V
Digital Output driven High
Note 1:
See Section 4.8.1 “Driving the Gain
Select Pin with a Microcontroller GPIO
Pin”.
See Section 4.8.2 “Driving the Gain
Select Pin with a PWM Signal”
2:
Possible GSEL Drivers
+1 V/V
MCP6G03 Chip Select (CS)
The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between VSS and
VOUT; even in shutdown. This means that the output
resistance will be 350 kΩ (typ.), with a path for output
signals to appear at the input. The supply current at
VSS includes the current through the load resistor and
ladder resistors; it also includes current from the CS pin
to VSS. When CS is low, the amplifier is enabled. If CS
is left floating, the amplifier may not operate properly.
HARD WIRED GAIN
SELECTION
© 2006 Microchip Technology Inc.
FIGURE 4-5:
Capacitive Loads.
SGA Circuit for Large
Figure 4-6 gives recommended RISO values for
different capacitive loads. After selecting RISO for your
circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify RISO’s value until the response is reasonable at
all gains.
DS22004B-page 21
MCP6G01/1R/1U/2/3/4
4.6.3
Recommended RISO (:)
1,000
INPUT SOURCE IMPEDANCE
The sources driving the inputs of the SGAs need to
have reasonably low source impedance at higher
frequencies. Figure 4-7 shows how the external source
resistance (RS), SGA package pin capacitance (CP1),
and SGA package pin-to-pin capacitance (CP2) form a
positive feedback voltage divider network. Feedback
may cause frequency response peaking and step
response overshoot and ringing.
100
For all gains
10
10p
10
FIGURE 4-6:
4.6
100p
1n
10n
100
1,000
10,000
Load Capacitance (F)
Recommended RISO.
Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in Section 1.0 “Electrical
Characteristics”
and
Section 2.0
“Typical
Performance Curves”. It will also help minimize
Electromagnetic Compatibility (EMC) issues.
Because the MCP6G01/1R/1U/2/3/4 SGAs’ frequency
response reaches unity gain at 10 MHz when G = 50, it
is important to use good PCB layout techniques. Any
parasitic coupling at high frequency might cause
undesired peaking. Filtering high frequency signals
(i.e., fast edge rates) can help.
4.6.1
COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low speed from high speed, and low power from high
power. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
4.6.2
SUPPLY BYPASS
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the VDD pin for good, high frequency
performance. It must connect directly to ground.
Use a bulk bypass capacitor (i.e., 1.0 µF to 10 µF)
within 100 mm of the VDD pin. It needs to connect to
ground, and provides large, slow currents. This
capacitor may be shared with other nearby analog
parts.
Ground plane is important, and power plane(s) can
also be of great help. High frequency (e.g., multi-layer
ceramic capacitors), surface mount components
improve the supply’s performance.
DS22004B-page 22
CP2
100n
100,000
RS
VS
MCP6G0X
VOUT
CP1
FIGURE 4-7:
Positive Feedback Path.
Figure 2-10 shows the crosstalk (referred to input) that
results when a hostile signal is connected to the other
inputs (e.g., VINB through VIND), and the input of
interest (e.g., VINA) has RS connected to GND. A gain
of +50 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing RS
increases the crosstalk as expected. At a source
impedance of 10 MΩ, there is noticeable change in
behavior.
Most designs should use a source resistance (RS) no
larger than 10 MΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 MΩ
must be used, place a capacitor in parallel to CP1 to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk)
peaking, yet small enough to allow a reasonable signal
bandwidth.
4.6.4
SIGNAL COUPLING
The input pins of the MCP6G01/1R/1U/2/3/4 family of
SGAs are high impedance. This makes them especially
susceptible to capacitively coupled noise. Using a
ground plane helps reduce this problem.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
4.7
Unused Amplifiers
4.8.2
An unused amplifier in a quad package (MCP6G04)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. Because the VIN pin looks like an open
circuit, the GSEL voltage is automatically set at VDD/2,
and the gain is 1 V/V. The output pin provides a
buffered VDD/2 voltage and minimizes the supply
current draw of the unused amplifier.
DRIVING THE GAIN SELECT PIN
WITH A PWM SIGNAL
The circuit in Figure 4-10 uses a PWM output on a PIC
microcontroller (100 kHz clock rate) to drive the Gain
Select input (GSEL). Setting the PWM duty cycle to
0%, 50% or 100% gives a GSEL voltage of 0V, VDD/2
or VDD, respectively (G = 10, 1 or 50).
VDD
¼ MCP6G04
VIN
VDD
VDD
VIN
MCP6G0X
VOUT
4.8
PWM
Output
The circuit in Figure 4-9 uses a microcontroller GPIO
pin to drive the Gain Select input (GSEL). Setting the
GPIO pin to logic low, high-Z or logic high gives a GSEL
voltage of 0V, VDD/2 or VDD, respectively (G = 10, 1 or
50).
VDD
VIN
MCP6G0X
VOUT
GSEL
GPIO
Pin
FIGURE 4-9:
4.7 nF
Driving the GSEL Pin.
The PWM clock rate needs to be fast so it is easily
filtered and does not interfere with the desired signal,
and it needs to be slow enough for good accuracy and
low crosstalk. This filter reduces the ripple at the GSEL
pin to about 7 mVP-P at VDD = 5.0V. The 10% settling
time is about 200 µs; the filter limits how quickly the
gain can be changed. Scale the resistors and/or
capacitors for other clock rates, or for different ripple.
4.8.3
MCU
10 kΩ
4.7 nF
FIGURE 4-10:
DRIVING THE GAIN SELECT PIN
WITH A MICROCONTROLLER GPIO
PIN
VDD
10 kΩ
Unused Amplifiers.
Typical Applications
4.8.1
VOUT
PIC MCU
GSEL
FIGURE 4-8:
MCP6G0X
GSEL
GAIN RANGING
Figure 4-11 shows a circuit that measures the current
IX. The circuit’s performance benefits from changing
the gain on the SGA. Just as a hand-held multimeter
uses different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the SGA’s output
is less than at its input (by up to 34 dB).
MCP6G0X
Driving the GSEL Pin.
The microcontroller’s GPIO pin cannot produce a
leakage current of more than ±1 µA for this circuit to
function properly. In noisy environments, a capacitor
may need to be added to the GPIO pin.
IX
VOUT
RS
FIGURE 4-11:
Wide Dynamic Range
Current Measurement Circuit.
© 2006 Microchip Technology Inc.
DS22004B-page 23
MCP6G01/1R/1U/2/3/4
4.8.4
4.8.5
SHIFTED GAIN RANGE SGA
Figure 4-12 shows a circuit using a MCP6271 at a gain
of +10 in front of a MCP6G01. This shifts the overall
gain range to +10 V/V to +500 V/V (from +1 V/V to
+50 V/V).
VIN
MCP6271
ADC DRIVER
This family of SGAs is well suited for driving Analog-toDigital Converters (ADC). The gains (1, 10, and 50)
effectively increase the ADC’s input resolution by a
factor of as large as 50 (i.e., by 5.6 bits). This works
well for applications needing relative accuracy more
than absolute accuracy (e.g., power monitoring); see
Figure 4-14.
VOUT
MCP6G01
Low-pass
Filter
VIN
10.0 kΩ
1.11 kΩ
MCP6G01
FIGURE 4-14:
FIGURE 4-12:
Range.
SGA with Higher Gain
It is also easy to shift the gain range to lower gains (see
Figure 4-13). The MCP6001 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +5.0 V/V (from +1 V/V to +50 V/V).
MCP3001 3
10-bit
ADC
OUT
SGA as an ADC Driver.
The low-pass filter in the block diagram reduces the
integrated noise at the MCP6G01’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
VIN
MCP6001
10.0 kΩ
VOUT
MCP6G01
1.11 kΩ
FIGURE 4-13:
Range.
DS22004B-page 24
SGA with Lower Gain
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
5-Lead SOT-23 (MCP6G01, MCP6G01R, MCP6G01U)
Device
XXNN
Code
MCP6G01
CKNN
MCP6G01R
CLNN
MCP6G01U
CMNN
CK25
Note: Applies to 5-Lead SOT-23
8-Lead SOIC (150 mil) (MCP6G01, MCP6G02, MCP6G03)
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP (MCP6G01, MCP6G02, MCP6G03)
XXXXXX
YWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP6G01E
e3
SN^^0634
256
Example:
6G01E
634256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS22004B-page 25
MCP6G01/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6S24)
Example:
MCP6G04
e3
E/SL^^
0609256
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (4.4mm) (MCP6S24)
XXXXXXXX
0609
NNN
256
e3
*
DS22004B-page 26
6G04E/ST
YYWW
Legend: XX...X
Y
YY
WW
NNN
Note:
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
A1
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
Pitch
n
p
.038
0.95
Outside lead pitch (basic)
p1
.075
1.90
Number of Pins
Overall Height
5
MAX
5
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
.014
.018
.022
0.35
0.45
0.55
Foot Angle
L
f
Lead Thickness
c
.004
Lead Width
B
a
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
b
0
5
.006
.017
10
0
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
© 2006 Microchip Technology Inc.
DS22004B-page 27
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
ϕ
c
L1
A1
Number of Pins
Pitch
Overall Height
Molded Package
Standoff
Overall Width
Molded Package
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
Thickness
A2
A1
E
Width
E1
D
L
L1
ϕ
c
b
MIN
—
0.75
0.00
0.40
0°
0.08
0.22
MILLIMETERS
NOM
8
0.65 BSC
—
0.85
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
—
—
—
L
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
DS22004B-page 28
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2006 Microchip Technology Inc.
DS22004B-page 29
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
.052
.061
1.55
A2
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.150
.157
3.99
Overall Length
D
.337
.347
8.81
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
DS22004B-page 30
MIN
A1
MIN
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
Units
Dimension Limits
A1
A2
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
1.10
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.193
.197
.201
4.90
5.00
5.10
Foot Length
L
φ
.020
.024
.028
0.50
0.60
0.70
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.007
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
14
14
.026 BSC
0.65 BSC
4°
0°
8°
0°
.006
.008
0.09
.010
.012
0.19
4°
8°
0.15
0.20
0.25
0.30
12° REF
12° REF
12° REF
12° REF
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
© 2006 Microchip Technology Inc.
Revised: 08-17-05
DS22004B-page 31
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 32
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
APPENDIX A:
REVISION HISTORY
Revision B (December 2006)
The following is the list of modifications:
• Added SOT-23-5 package option for the single
gain blocks MCP6G01, MCP6G01R, and
MCP6G01U.
• Added a discussion on VIN range vs. G.
Revision A (September 2006)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS22004B-page 33
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 34
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Device
Temperature
Range
Package
Device:
Examples:
a)
b)
MCP6G01:
MCP6G01T:
MCP6G01RT:
MCP6G01UT:
MCP6G02:
MCP6G02T:
MCP6G03:
MCP6G03T:
MCP6G04:
MCP6G04T:
Single SGA
Single SGA
(Tape and Reel for MSOP and SOIC)
Single SGA
(Tape and Reel for SOT-23-5)
Single SGA
(Tape and Reel for SOT-23-5)
Dual SGA
Dual SGA
(Tape and Reel for MSOP and SOIC)
Single SGA
Single SGA
(Tape and Reel for MSOP and SOIC)
Quad SGA
Quad SGA
(Tape and Reel for SOIC and TSSOP)
Temperature Range:
E
= -40°C to +125°C
Package:
MS
OT
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
Plastic Small Outline Transistor (SOT-23-5), 5-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6G04)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6G04)
© 2006 Microchip Technology Inc.
c)
d)
e)
a)
MCP6G01-E/MS:
Extended Temperature,
8LD MSOP.
MCP6G01T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
MCP6G01T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
MCP6G01RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
MCP6G01UT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
b)
Extended Temperature,
8LD MSOP.
MCP6G02T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
a)
MCP6G03-E/MS:
b)
c)
MCP6G02-E/MS:
Extended Temperature,
8LD MSOP.
MCP6G03T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
MCP6G03-E/SN: Extended Temperature,
8LD SOIC.
a)
MCP6G04T-E/SL:
b)
MCP6G04T-E/ST:
c)
MCP6G04-E/ST:
Tape and Reel,
Extended Temperature,
14LD SOIC.
Tape and Reel,
Extended Temperature,
14LD TSSOP.
Extended Temperature,
14LD TSSOP.
DS22004B-page 35
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 36
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS22004B-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
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Tel: 33-1-69-53-63-20
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Tel: 81-45-471- 6166
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Fax: 82-2-558-5932 or
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
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Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
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Netherlands - Drunen
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Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
10/19/06
DS22004B-page 38
© 2006 Microchip Technology Inc.
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