Maxim MAX3748AETE Compact 155mbps to 3.2gbps limiting amplifier Datasheet

19-2717; Rev 1; 7/03
KIT
ATION
EVALU
E
L
B
AVAILA
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Features
♦ SFP Reference Design Available
♦ 16-Pin QFN Package with 3mm ✕ 3mm Footprint
♦ Single +3.3V Supply Voltage
♦ 86ps Rise and Fall Time
A received-signal-strength indicator (RSSI) is available
when the MAX3748/MAX3748A is combined with the
MAX3744 SFP transimpedance amplifier (TIA). A receiver
consisting of the MAX3744* and the MAX3748/
MAX3748A can provide up to 19dB RSSI dynamic range.
Additional features include a programmable loss-of-signal
(LOS) detect, an optional disable function (DISABLE),
and an output signal polarity reversal (OUTPOL). Output
disable can be used to implement squelch.
The combination of the MAX3748/MAX3748A and the
MAX3744 allows for the implementation of all the smallform-factor SFF-8472 digital diagnostic specifications
using a standard 4-pin TO-46 header. The MAX3748/
MAX3748A is packaged in a 3mm ✕ 3mm 16-pin QFN
package with an exposed pad.
♦ Loss of Signal with Programmable Threshold
*Future product—contact factory for availability.
*EP = Exposed pad.
♦ RSSI Interface (with MAX3744 TIA)
♦ Output Disable
♦ Polarity Select
♦ 8.5psP-P Deterministic Jitter (3.2Gbps)
Ordering Information
TEMP RANGE
PINPACKAGE
PACKAGE
CODE
MAX3748ETE
-40°C to +85°C
16 QFN-EP*
T1633-3
MAX3748AETE
-40°C to +85°C
16 QFN-EP*
T1633-3
PART
Applications
Functional Diagram and Pin Configuration appear at end of
data sheet.
Gigabit Ethernet SFF/SFP Transceiver Modules
Fibre Channel SFF/SFP Transceiver Modules
Multirate OC-3 to OC-48-FEC SFF/SFP
Transceiver Modules
Typical Operating Circuits
SFP OPTICAL RECEIVER
HOST BOARD
SUPPLY FILTER
0.1µF
4-PIN TO HEADER
HOST FILTER
VCC_RX
OUTPOL
VCC
CAZ1
CAZ2
0.1µF
IN+
MAX3744 TIA*
OUT+
50Ω
SERDES
0.1µF
OUT-
IN-
50Ω
MAX3748/
MAX3748A
RSSI
GND
TH
DISABLE
LOS
4.7kΩ TO 10kΩ
DS1858
3-INPUT DIAGNOSTIC
MONITOR
RTH
VCC_HOST
LOS
R1
3kΩ
C1
0.1µF
*FUTURE PRODUCT.
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3748/MAX3748A
General Description
The MAX3748/MAX3748A multirate limiting amplifier functions as a data quantizer for SONET, Fibre Channel, and
Gigabit Ethernet optical receivers. The amplifier accepts
a wide range of input voltages and provides constantlevel current-mode logic (CML) output voltages with controlled edge speeds.
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +6.0V
Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V)
Voltage at DISABLE, OUTPOL, RSSI,
CAZ1, CAZ2, LOS, TH............................-0.5V to (VCC + 0.5V)
Current into LOS ...................................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ...............................................-25mA to +25mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QFN (derate 17.7mW above +70°C) ....................1.4W
Operating Junction Temperature Range (TJ) ....-55°C to +150°C
Storage Ambient Temperature Range (Ts)........-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ω to VCC, CAZ = 0.1µF, typical values are at
+25°C, VCC = 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB =
0.75 ✕ 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 ✕ 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER
SYMBOL
CONDITIONS
Single-Ended Input Resistance
Single ended to VCC
Input Return Loss
Differential, f < 3GHz, DUT is powered on
Input Sensitivity
VIN-MIN
(Note 1)
Input Overload
VIN-MAX
(Note 1)
Single-Ended Output Resistance
Single ended to VCC
Output Return Loss
Differential, f < 3GHz, DUT is powered on
Differential Output Voltage
MIN
TYP
MAX
42
50
58
13
1200
Differential Output Signal when
Disabled
780
Outputs AC-coupled, VIN-MAX applied to
input (Note 2)
K28.5 pattern at 3.2Gbps
mVP-P
mVP-P
50
58
10
600
Ω
dB
5
42
UNITS
Ω
dB
1200
mVP-P
10
mVP-P
8.5
25
2 - 1 PRBS equivalent pattern at 2.7Gbps
(Note 4)
9.3
30
K28.5 pattern at 2.1Gbps
7.8
25
2 - 1 PRBS equivalent pattern at 155Mbps
25
50
Random Jitter
(Note 5)
Input = 5mVP-P
6.5
Input = 10mVP-P
3
Data Output Transition Time
20% to 80% (Note 2)
23
Deterministic Jitter
(Notes 2, 3)
DJ
23
86
Input-Referred Noise
Power-Supply Current
Power-Supply Noise Rejection
psRMS
115
185
Low-Frequency Cutoff
ICC
PSNR
CAZ = open
70
CAZ = 0.1µF
0.8
(Note 6)
32
LOS disabled
ps
µVRMS
kHz
49
37
f < 2MHz
psP-P
mA
26
dB
2.2
dB
LOSS OF SIGNAL at 2.5Gbps (Notes 2, 7)
LOS Hysteresis
10log (VDEASSERT/VASSERT)
LOS Assert/Deassert Time
(Note 8)
Low LOS Assert Level
RTH = 20kΩ
Low LOS Deassert Level
RTH = 20kΩ
Medium LOS Assert Level
RTH = 280Ω
2
1.25
2
100
2.8
4.1
10.3
15.2
6.7
_______________________________________________________________________________________
µs
mVP-P
11.6
mVP-P
mVP-P
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
(VCC = 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ω to VCC, CAZ = 0.1µF, typical values are at
+25°C, VCC = 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB =
0.75 ✕ 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 ✕ 3.2GHz for data rate of 3.2Gbps.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
25
38.6
mVP-P
Medium LOS Deassert Level
RTH = 280Ω
High LOS Assert Level
RTH = 80Ω
High LOS Deassert Level
RTH = 80Ω
65.2
10log (VDEASSERT/VASSERT)
2.1
22.8
38.3
mVP-P
99.3
mVP-P
LOSS OF SIGNAL at 155Mbps (Note 7)
LOS Hysteresis
dB
LOS Assert/Deassert Time
(Note 8)
20
µs
Low LOS Assert Level
RTH = 20kΩ
3.5
mVP-P
Low LOS Deassert Level
RTH = 20kΩ
5.6
mVP-P
Medium LOS Assert Level
RTH = 280Ω
13.3
mVP-P
Medium LOS Deassert Level
RTH = 280Ω
21.2
mVP-P
High LOS Assert Level
RTH = 80Ω
33.3
mVP-P
High LOS Deassert Level
RTH = 80Ω
55.5
mVP-P
RSSI
RSSI Current Gain (Note 9)
ARSSI
Input-Referred RSSI Current
Stability
ARSSI = IRSSI/ICM_RSSI
IRSSI/ARSSI
(Note 10)
0.03
ICM_INPUT < 6.6mA
-31
+33
ICM_INPUT > 6.6mA
-73
+90
µA
TTL/CMOS I/O
LOS Output High Voltage
VOH
RLOS = 4.7kΩ to10kΩ to VCC_host (3V)
LOS Output Low Voltage
VOL
RLOS = 4.7kΩ to10kΩ to VCC_host (3.6V)
0.4
V
RLOS = 4.7kΩ to10kΩ to VCC_host (3.3V);
IC is powered down
40
µA
LOS Output Current
DISABLE Input High
VIH
DISABLE Input Low
VIL
DISABLE Input Current
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
2.4
V
2.0
RLOS = 4.7kΩ to 10kΩ to VCC_host
V
0.8
V
10
µA
Between sensitivity and overload, all AC specifications are met.
Guaranteed by design and characterization.
The deterministic jitter caused by this filter is not included in the DJ generation specifications (input).
223 - 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The
low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs generated using K28.5 and 223 - 1 PRBS patterns.
Random jitter was measured without using a filter at the input.
The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC
(see Figure 1).
Unless otherwise specified, the pattern for all LOS detect specifications is 223 - 1 PRBS.
The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
ICM_INPUT is the input common mode. IRSSI is the current at the RSSI output.
Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.
_______________________________________________________________________________________
3
MAX3748/MAX3748A
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C and VCC = +3.3V, unless otherwise specified.)
SUPPLY CURRENT
vs. TEMPERATURE
60
50
40
30
20
10
0
600
500
400
300
8
7
6
5
4
3
2
100
1
0
0
1
2
3
4
5
6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
DIFFERENTIAL INPUT (mVP-P)
TEMPERATURE (°C)
RANDOM JITTER
vs. INPUT AMPLITUDE
BIT-ERROR RATIO vs. INPUT VOLTAGE
DETERMINISTIC JITTER vs. INPUT
COMMON-MODE VOLTAGE (VCC TO VCC - 0.8V)
7
6
5
4
3
2
800
600
400
200
20
40
30
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (mVP-P)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
14
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3748 toc09
2.7Gbps, 223 - 1 PRBS, 5mVP-P
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
100mV/div
100mV/div
50ps/div
16
MAX3748 toc08
3.2Gbps, 223 - 1 PRBS, 5mVP-P
100mV/div
18
COMMON-MODE VOLTAGE (VCC + x)
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
MAX3748 toc07
20
10
0
10
22
12
1
0
24
DETERMINISTIC JITTER (psP-P)
1000
BIT-ERROR RATIO (10-12)
8
MAX3748 toc05
1200
MAX3748 toc04
9
MAX3748 toc06
TEMPERATURE (°C)
10
4
9
200
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100
0
MAX3748 toc03
700
RANDOM JITTER (psRMS)
70
OUTPUT VOLTAGE vs. INPUT VOLTAGE
800
10
MAX3748 toc02
80
900
DIFFERENTIAL OUTPUT (mVP-P)
MAX3748 toc01
90
CURRENT (mA)
RANDOM JITTER vs. TEMPERATURE
(INPUT LEVEL 10mVP-P)
TRANSFER FUNCTION
100
RANDOM JITTER (psRMS)
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
50ps/div
100ps/div
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
OUTPUT EYE DIAGRAM AT +100°C
(MINIMUM INPUT)
ASSERT/DEASSERT LEVELS vs. RTH
MAX3748 toc11
MAX3748 toc10
100
3.2Gbps, 223 - 1 PRBS, 5mVP-P
ASSERT/DEASSERT (mVP-P)
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
100mV/div
100mV/div
MAX3748 toc12
OUTPUT EYE DIAGRAM WITH MAXIMUM INPUT
(DATA RATE OF 2.6667Gbps)
DEASSERT
10
ASSERT
1
50ps/div
50ps/div
0.1
0.01
10
1
100
RTH (kΩ)
30
30
20
GAIN (dB)
10
0
-10
0
-10
-20
-20
-30
-30
1G
10G
10
8
6
4
-6
-2
0
2
6
4
INPUT OFFSET VOLTAGE (mVP-P)
4
RTH = 80Ω
2
RTH = 280Ω
0
700
600
OUTPUT RSSI CURRENT (µA)
5
-4
RSSI CURRENT GAIN vs. INPUT TIA CURRENT
(MAX3744 AND MAX3748)
MAX3748 toc16
6
1
12
FREQUENCY (Hz)
LOS HYSTERESIS vs. TEMPERATURE
(2.667bps, 210 - 1 PRBS)
RTH = 20kΩ
14
0
1G
FREQUENCY (Hz)
3
16
2
-40
100M
10G
18
MAX3748 toc17
-40
100M
10LOG (DEASSERT/ASSERT) (dB)
GAIN (dB)
10
20
MAX3748 toc15
20
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE
(2.667Gbps, K28.5)
DETERMINISTIC JITTER (psP-P)
OUTPUT
DISABLED
MAX3748 toc14
OUTPUT RETURN GAIN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -40dBm)
MAX3748 toc13
INPUT RETURN GAIN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -40dBm)
500
400
300
200
100
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
MAX3748/MAX3748A
Typical Operating Characteristics (continued)
(TA = +25°C and VCC = +3.3V, unless otherwise specified.)
0 100 200 300 400 500 600 700 800 900 1000
INPUT TIA CURRENT (µA)
_______________________________________________________________________________________
5
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
MAX3748/MAX3748A
Pin Description
PIN
NAME
FUNCTION
1, 4, 12
VCC
2
IN+
Noninverted Input Signal, CML
3
IN-
Inverted Input Signal, CML
5
TH
Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to
VCC disables the LOS circuitry and reduces power consumption.
Supply Voltage
DISABLE
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled, CMOS. On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
7
LOS
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector (Figure 5). On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
8, 16
GND
6
9
OUTPOL
Supply Ground
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier
and connect to VCC for normal operation.
10
OUT-
11
OUT+
Inverted Data Output, CML
Noninverted Data Output, CML
13
RSSI
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor between
this pin and GND.
14
CAZ2
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. The offset
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.
15
CAZ1
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends
the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. The offset correction is disabled
when the CAZ1 and CAZ2 pins are shorted together.
EP
Exposed
paddle
Connect the exposed paddle to board ground for optimal electrical and thermal performance.
Detailed Description
The limiting amplifier consists of an input buffer, a multistage amplifier, offset correction circuitry, an output
buffer, power-detection circuitry, and signal-detect circuitry (see Functional Diagram).
VCC
IOUT (CML
OUTPUT CURRENT)
ICC (SUPPLY CURRENT)
50Ω
50Ω
Input Buffer
The input buffer is shown in Figure 3. It provides 50Ω
termination for each input signal IN+ and IN-. The
MAX3748/MAX3748A can be DC- or AC-coupled to a
TIA (TIA output offset degrades receiver performance if
DC-coupled). The CML input buffer is optimized for the
MAX3744 TIA.
MAX3748/
MAX3748A
RTH
Gain Stage
The high-bandwidth gain stage provides approximately
53dB of gain.
6
Figure 1. Power-Supply Current Measurement
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
MAX3748/MAX3748A
VIN
VCC
SIGNAL ON
1dB
MAX DEASSERT LEVEL
0.25pF
50Ω
50Ω
IN+
6dB
POWER-DETECT WINDOW
75kΩ
IN0.25pF
MIN DEASSERT LEVEL
ESD
STRUCTURES
0V
SIGNAL OFF
TIME
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum
by Receiver Sensitivity (for Selected RTH)
Figure 3. CML Input Buffer
Offset Correction Loop
The MAX3748/MAX3748A is susceptible to DC offsets
in the signal path because it has high gain. In communication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or
generated in the transimpedance amplifier appears as
an input offset and is reduced by the offset correction
loop. For Gigabit Ethernet and Fibre Channel applications, no capacitor is required. For SONET applications,
CAZ = 0.1µF is recommended. This capacitor determines the lower 3dB frequency of the data path.
CML Output Buffer
The MAX3748/MAX3748A limiting amplifier’s CML output provides high tolerance to impedance mismatches
and inductive connectors. The output current is approximately 18mA. The output is disabled by connecting the
DISABLE pin to VCC. If the LOS pin is connected to the
DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level
drops below the LOS threshold. The output buffer can
be AC- or DC-coupled to the load (Figure 4).
Power-Detect and
Loss-of-Signal Indicator
The MAX3748/MAX3748A is equipped with an LOS circuitry, which indicates when the input signal is below a
programmable threshold, set by resistor RTH at the TH
pin (see Typical Operating Characteristics for appropriate resistor sizing). An averaging peak-power detector
compares the input signal amplitude with this threshold
and feeds the signal detect information to the LOS output, which is open collector. Two control voltages,
VASSERT and VDEASSERT, define the LOS assert and
VCC
50Ω
50Ω
OUT+
OUT-
Q3
Q4
Q1
Q2
ESD
STRUCTURES
DISABLE
DATA
18mA
DISABLE
18mA
DISABLE
Figure 4. CML Output Buffer
deassert levels. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level (V DEASSERT )
(Figure 5).
Design Procedure
Program the LOS Assert Threshold
External resistor RTH programs the LOS threshold. See
the Assert/Deassert Levels vs. RTH graph in the Typical
Operating Characteristics to select the appropriate
resistor.
_______________________________________________________________________________________________________
7
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
VCC
LOS
ESD
STRUCTURE
GND
Figure 5. MAX3748 LOS Output Circuit
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN
and COUT should be selected to minimize the receiver’s
deterministic jitter. Jitter is decreased as the input lowfrequency cutoff (fIN) is decreased:
fIN = 1 / [2π(50)(CIN)]
For ATM/SONET or other applications using scrambled
NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides
fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or
other applications using 8B/10B data coding, select
(CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz.
Refer to Application Note HFAN-1.1: Choosing ACCoupling Capacitors.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC offset cancellation
loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency
cutoff (fOC) associated with the DC offset cancellation
circuit. For ATM/SONET or other applications using
scrambled NRZ data, fIN < 32kHz, so fOCMAX < 3.2kHz.
Therefore, CAZ = 0.1µF (fOC = 2kHz). For Fibre Channel
or Gigabit Ethernet applications, leave pins CAZ1 and
CAZ2 open.
The MAX3744 preamp measures the average photodiode current and provides the information to the output
common mode. The MAX3748/MAX3748A RSSI detect
block senses the common-mode DC level of input signals IN+ and IN- and provides a ground-referenced output signal (RSSI) proportional to the photodiode current.
The advantage of this implementation is that it allows the
TIA to be packaged in a low-cost conventional 4-pin TO46 header.
The MAX3748/MAX3748A RSSI output is connected to
an analog input channel of the DS1858/DS1859 SFP
controller to convert the analog information into a 16-bit
word. The DS1858/DS1859 provide the receive-power
information to the host board of the optical receiver
through a 2-wire interface. The DS1859 allows for internal
calibration of the receive-power monitor.
The MAX3744 and the MAX3748/MAX3748A have been
optimized to achieve RSSI stability of 2.5dB within the
range of 6µA to 500µA of average input photodiode
current. To achieve the best accuracy, Maxim recommends receive power calibration at the low end (6µA)
and the high end (500µA) of the required range; see
the RSSI Current Gain graph in the Typical Operating
Characteristics.
Connecting to the DS1858/DS1859
For best use of the RSSI monitor, capacitor C1 and
resistor R1 shown in the first Typical Application Circuit
need to be placed as close as possible to the Dallas
diagnostic monitor with the ground of C1 and R1 the
same as the DS1858/DS1859 ground. Capacitor C1
suppresses system noise on the RSSI signal. R1 = 3kΩ
and C1 = 0.1µF is recommended.
VCC
RSSI Implementation
LOS
The SFF-8472 Digital Diagnostic specification requires
monitoring of input receive power. The MAX3748/
MAX3748A and MAX3744 receiver chipset allows for
the monitoring of the average receive power by measuring the average DC current of the photodiode.
ESD
STRUCTURE
GND
Figure 6. MAX3748A LOS Output Circuit
8
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
SFP OPTICAL RECEIVER
VCC (+3.3V OR APD
REFERENCE VOLTAGE)
HOST BOARD
VCC (+3.3V)
SUPPLY FILTER
0.1µF
HOST FILTER
VCC_RX
5-PIN TO HEADER
OUTPOL
VCC
CAZ1
CAZ2
0.1µF
PIN OR
APD
IN+
MAX3744 TIA
OUT+
50Ω
SERDES
0.1µF
OUT-
IN-
50Ω
MAX3748/
MAX3748A
RSSI
GND
TH
DS1858
3-INPUT DIAGNOSTIC
MONITOR
DISABLE
LOS
4.7kΩ TO 10kΩ
VCC_HOST
RTH
LOS
R1
3kΩ
C1
0.1µF
SFP OPTICAL RECEIVER
HOST BOARD
VCC (+3.3V OR APD
REFERENCE VOLTAGE)
VCC (+3.3V)
HIGH-SIDE
CURRENT SENSE
SUPPLY FILTER
0.1µF
HOST FILTER
VCC_RX
5-PIN TO HEADER
OUTPOL
VCC
CAZ1
CAZ2
COUT
0.1µF
CIN
0.1µF
PIN OR
APD
IN+
OUT+
IN-
OUT-
SERDES
MAX3744 TIA
CIN
0.1µF
GND
TH
50Ω
COUT
0.1µF
MAX3748/
MAX3748A
RSSI
DS1858
3-INPUT DIAGNOSTIC
MONITOR
50Ω
DISABLE
LOS
4.7kΩ TO 10kΩ
VCC_HOST
RTH
LOS
_______________________________________________________________________________________
9
MAX3748/MAX3748A
Typical Operating Circuits (continued)
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
MAX3748/MAX3748A
Functional Diagram
CAZ
VCC
VCC
50Ω
CAZ1
50Ω
CAZ2
MAX3748/
MAX3748A
50Ω
50Ω
OFFSET
CORRECTION
OUTOUT+
IN+
IN-
18mA
DISABLE
RSSI
DETECT
RSSI
POWER
DETECT
TH
LOS
OUTPOL
Pin Configuration
GND
16
VCC
1
IN+
2
IN-
3
VCC
4
CAZ1 CAZ2
15
14
Chip Information
TRANSISTOR COUNT: 1468
PROCESS: SiGe Bipolar
RSSI
13
12 VCC
11 OUT+
MAX3748/
MAX3748A
10 OUT9
5
6
7
TH DISABLE LOS
OUTPOL
8
GND
3mm x 3mm QFN
10
______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
12x16L QFN THIN.EPS
D2
0.10 M C A B
b
D
D2/2
D/2
E/2
E2/2
CL
-A-
(NE - 1) X e
E
E2
L
-B-
k
e
CL
(ND - 1) X e
CL
CL
0.10 C
0.08 C
A
A2
A1
L
L
e
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0136
REV.
1
C
2
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0136
REV.
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX3748/MAX3748A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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