Cypress CY28416OXCT Next generation ftg for intel-r architecture Datasheet

PRELIMINARY
CY28416
Next Generation FTG for Intel® Architecture
Features
• Two 33-MHz PCI Free Running Clocks
• Low Voltage Frequency Select Input
• Supports Intel Pentium®4-Type CPUs
• I2C Support Byte/Word/Block Read/Write Capabilities
• Selectable CPU Frequencies
• Ideal Lexmark Spread Spectrum Profile for Maximum
EMI Reduction
• Two Differential CPU Clock Pairs
• Four 100-MHz Differential SRC Clock Pairs
• One CPU/SRC Selectable Differential Clock Pair
• One 96-MHz Differential Dot Clock Support
• Two 48-MHz Clocks
• Four 33-MHz PCI Clocks
• 3.3V Power Supply
• 48-pin SSOP Package
CPU
SRC
PCI
DOT
USB
REF
x2 / x3
x4 / x5
x6
x1
x2
x2
Block Diagram
XIN
XOUT
XTAL
OSC
PLL1
Pin Configuration
VDD_REF
REF
PLL Ref Freq
VDD_CPU
CPUT[0:1], CPUC[0:1],
CPU2/SRC4
VDD_SRC
SRCT[0:3], SRCC[0:3]
Divider
Network
FS_[C:A]
VTT_PWRGD#
IREF
PD
VDD_48MHz
DOT96T
DOT96C
PLL2
48MHz0
48MHz1
SDATA
SCLK
I2C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CY28416
VDD_PCI
PCI[0:3]
VDD_PCIF
PCIF[0:1]
SCLK
SDATA
XOUT
XIN
VSS_REF
REF1/FS_A
REF0/FS_C
VDD_REF
PCI0
PCI1
VDD_PCI
VSS_PCI
PCI2
PCI3
VSS_PCI
VDD_PCI
PCIF0/TESTSEL
PCIF1/ITPEN
VDD_48
48MHz0/FS_B
48MHz1
VSS_48
DOT96T
DOT96C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
VDD_SRC
VSS_SRC
SRCT3
SRCC3
VDD_SRC
SRCC2_SATA
SRCT2_SATA
SRCC1
SRCT1
VSS_SRC
SRCC0
SRCT0
VTT_PWRGD#/PD
48-PIN SSOP
Cypress Semiconductor Corporation
Document #: 38-07657 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 2, 2005
PRELIMINARY
CY28416
Pin Definition
Pin No.
Name
Type
Description
47,46,44,43
CPUT/C[0:1]
O, DIF Differential CPU clock output.
39,38
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
O, DIF Selectable Differential CPU or SRC clock output.
ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4
ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP
23,24
DOT96T, DOT96C
O, DIF Differential 96-MHz clock output
6
FS_A/REF1
I/O, SE 3.3V tolerant input for CPU frequency/REF clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
20
FS_B/48 MHz0
I/O, SE 3.3V tolerant input for CPU frequency/48 MHz clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
7
FS_C/REF0
I/O, SE 3.3V tolerant input for CPU frequency/REF clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
42
IREF
18
ITP_EN/PCIF1
I/O, SE Enable SRC4 or CPU2_ITP/PCIF clock.
(sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP
9,10,13,14
PCI
O, SE 33-MHz clock output.
21
48 MHz1
O, SE 48-MHz clock output.(Uses same control SMBus register as 48 MHz0 to control
enable/disable.)
1
SCLK
I
2
SDATA
I/O
26,27,29,30,
34,35
SRCT/C[0:3]
O, DIF Differential Serial reference clock.
31,32
SRCT2_SATA,
SRCC2_SATA
O, DIF Differential Serial reference clock. Recommended output for SATA
17
TEST_SEL/PCIF0
I/O, SE, LVTTL input for selecting HI-Z or Normal operation/33 MHz Clock
PD 0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled
19
VDD_48
PWR
3.3V power supply for outputs
45
VDD_CPU
PWR
3.3V power supply for outputs
11, 16
VDD_PCI
PWR
3.3V power supply for outputs
8
VDD_REF
PWR
3.3V power supply for outputs
33, 37
VDD_SRC
PWR
3.3V power supply for outputs
40
VDDA
PWR
3.3V power supply for PLL
22
VSS_48
GND
Ground for outputs
48
VSS_CPU
GND
Ground for outputs
12, 15
VSS_PCI
GND
Ground for outputs
5
VSS_REF
GND
Ground for outputs
28, 36
VSS_SRC
GND
Ground for outputs
41
VSSA
GND
Ground for PLL
25
VTT_PWRGD#/PD
I, PD
3.3V LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A,
FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting
VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting
power-down (active HIGH)
4
XIN
I
14.318-MHz Crystal Input
3
XOUT
O
14.318-MHz Crystal Output
Document #: 38-07657 Rev. *A
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
SMBus compatible SCLOCK.
SMBus compatible SDATA.
Page 2 of 15
PRELIMINARY
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
CY28416
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as
described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Frequency Select Table (FS_A FS_B)
FS_C
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
DOT96
USB
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
166 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
0
0
266 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
1
0
0
333 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
1
1
0
400 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
1
1
1
Reserved
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
T
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Slave address – 7 bits
Block Read Protocol
Bit
1
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 Bits
18:11
Command Code – 8 Bits
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
27:20
28
36:29
37
45:38
46
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Document #: 38-07657 Rev. *A
27:21
28
29
37:30
38
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Page 3 of 15
PRELIMINARY
CY28416
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
Description
....
Data Byte /Slave Acknowledges
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Stop
Block Read Protocol
Bit
46:39
47
55:48
Description
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
...
Stop
Table 4. Byte Read and Byte Write protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Byte Read Protocol
Bit
1
Slave address – 7 bits
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Data byte – 8 bits
20
28
Acknowledge from slave
29
Stop
27:21
Repeated start
Slave address – 7 bits
28
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
7
1
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
6
1
RESERVED
5
1
RESERVED
4
1
SRC[T/C]3
3
1
SRC[T/C]2_SATA
2
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
RESERVED
Document #: 38-07657 Rev. *A
Description
CPU[T/C]2_ITP/SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 1
RESERVED, Set = 1
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2_SATA Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 1
Page 4 of 15
PRELIMINARY
CY28416
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
RESERVED
RESERVED, Set = 1
6
1
DOT_96T/C
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5
1
48 MHz0, 48 MHz1
48 MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF0
REF Output Enable
0 = Disabled, 1 = Enabled
3
1
REF1
REF Output Enable
0 = Disabled, 1 = Enabled
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
0
0
CPUT/C
SRCT/C
PCIF
PCI
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
Description
6
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
5
1
RESERVED
RESERVED, Set = 1
4
1
RESERVED
RESERVED, Set = 1
3
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
7
0
SRC[T/C]4
6
0
RESERVED
RESERVED, Set = 0
5
0
RESERVED
RESERVED, Set = 0
4
0
SRC[T/C]3
3
0
SRC2_SATA
2
0
SRC[T/C]1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC[T/C]0
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
0
RESERVED
Document #: 38-07657 Rev. *A
Description
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC2_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
Page 5 of 15
PRELIMINARY
CY28416
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED, Set = 0
6
0
DOT96[T/C]
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
PCIF1
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
0
PCIF0
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
RESERVED
RESERVED, Set = 0
2
1
RESERVED
RESERVED, Set = 1
1
1
RESERVED
RESERVED, Set = 1
0
1
RESERVED
RESERVED, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
SRC[T/C][4:0]
Description
6
0
RESERVED
RESERVED, Set = 0
5
0
RESERVED
RESERVED, Set = 0
4
0
RESERVED
3
0
SRC[T/C][4:0]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2
0
CPU[T/C]2_ITP
CPU[T/C]2_ITP PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Tri-state when SW
PCI_STP# asserted
RESERVED, Set = 0
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
RESERVED
6
0
5
1
REF1
REF1 Output Drive Strength
0 = Low, 1 = High
4
1
REF0
REF0 Output Drive Strength
0 = Low, 1 = High
3
1
PCIF, SRC, PCI
2
Externally
selected
FS_C. Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
1
Externally
selected
FS_B. Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
0
Externally
selected
FS_A. Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
Document #: 38-07657 Rev. *A
Description
RESERVED, Set = 0
Test Clock Mode Entry Control
0 = Normal operation, 1 = Hi-Z mode
SW PCI_STP# Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will
resume in a synchronous manner with no short pulses.
Page 6 of 15
PRELIMINARY
CY28416
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
Revision Code Bit 3
6
0
Revision Code Bit 2
Revision Code Bit 2
5
0
Revision Code Bit 1
Revision Code Bit 1
4
1
Revision Code Bit 0
Revision Code Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
20 pF
Crystal Recommendations
Calculating Load Capacitors
The CY28416 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28416 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal, not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs1
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
Figure 1. Crystal Capacitive Clarification
Document #: 38-07657 Rev. *A
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be 2 times the specified
load capacitance(CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors(Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides.
Page 7 of 15
PRELIMINARY
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs.............................................. Stray capacitance (terraced)
Ci ........................................................... Internal capacitance
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal needs to be
synchronized internal to the device prior to powering down the
clock synthesizer. PD is also an asynchronous input for
powering up the system. When PD is asserted high, all clocks
need to be driven to a low value and held prior to turning off
the VCOs and the crystal oscillator.
CY28416
PD (Power-down)—Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs must be held low on their next
high to low transition and differential clocks must held high or
tri-stated (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition. When
the SMBus PD drive mode bit corresponding to the differential
(CPU, SRC, and DOT) clock output of interest is programmed
to ‘0’, the clock output must be held with “Diff clock” pin driven
high at 2 x Iref, and “Diff clock#” tristate. If the control register
PD drive mode bit corresponding to the output of interest is
programmed to “1”, then both the “Diff clock” and the “Diff
clock#” are tri-state. Note the example in Figure 3 shows
CPUT = 133 MHz and PD drive mode = ‘1’ for all differential
outputs. This diagram and description is applicable to valid
CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted high in less than 10 µs after
asserting VTT_PWRGD#.
PD Deassertion
The power-up latency needs to be less than 1.8 ms. This is the
time from the deassertion of the PD pin or the ramping of the
power supply until the time that stable clocks are output from
the clock chip. All differential outputs stopped in a tristate
condition resulting from power down must be driven high in
less than 300 µs of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are to be enabled within a few clock cycles
of each other. Figure 4 is an example showing the relationship
of clocks coming up. Unfortunately, we can not show all
possible combinations, designers need to insure that from the
first active clock output to the last takes no more than two full
PCI clock cycles.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Document #: 38-07657 Rev. *A
Page 8 of 15
PRELIMINARY
CY28416
Tstable
<1.8nS
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
Tdrive_PW RDN#
<300µS, >200mV
REF
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
Clock State
State 0
W ait for
VTT_PW RGD#
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
State 1
State 2
State 3
Off
Clock Outputs
On
On
Off
Clock VCO
Figure 5. VTT_PWRGD# Timing Diagram
S2
S1
D elay
>0.25m S
VTT_PW R G D# = Low
S am ple
Inputs straps
VDD _A = 2.0V
W ait for <1.8m s
S0
S3
P ow er O ff
VD D_A = off
N orm al
O peration
Enable O utputs
VTT_PW RG D # = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Document #: 38-07657 Rev. *A
Page 9 of 15
PRELIMINARY
CY28416
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
–0.5
4.6
V
VDD
Core Supply Voltage
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
–65
150
°C
0
70
°C
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating Ambient
Functional
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
15
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
45
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
3.3V Operating Voltage
VDD_A,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3 ± 5%
Min.
Max.
Unit
3.135
3.465
V
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
–
V
VIL_FS
FS_[A:C] Input Low Voltage
0.7
VDD + 0.5
V
VIH_FS
FS_[A:C] Input High Voltage
VSS – 0.3
0.35
V
VIL
Input Low Voltage
VSS – 0.5
0.8
V
VIH
Input High Voltage
2.0
VDD + 0.5
V
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0 < VIN < VDD
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
IOZ
High-impedance Output Current
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
3
6
pF
LIN
Pin Inductance
–
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDD3.3V
Dynamic Supply Current
At max load and freq per Table 6 and Figure 7
–
400
mA
IPD3.3V
Power-down Supply Current
PD asserted, Outputs driven
–
70
mA
IPD3.3V
Power-down Supply Current
PD asserted, Outputs Tri-stated
–
2
mA
Document #: 38-07657 Rev. *A
µA
–5
5
µA
–
0.4
V
2.4
–
V
–10
10
µA
2
5
pF
Page 10 of 15
PRELIMINARY
CY28416
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
ns
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external clock
source
TR / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-µs duration
–
500
ps
LACC
Long-term Accuracy
Over 150 ms
–
300
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz CPUT and CPUC Period
Measured at crossing point VOX
9.9970
10.003
ns
TPERIOD
133-MHz CPUT and CPUC Period
Measured at crossing point VOX
7.4978
7.5023
ns
TPERIOD
166-MHz CPUT and CPUC Period
Measured at crossing point VOX
5.9982
6.0018
ns
TPERIOD
200-MHz CPUT and CPUC Period
Measured at crossing point VOX
4.9985
5.0015
ns
TPERIOD
266-MHz CPUT and CPUC Period
Measured at crossing point VOX
3.7489
3.7511
ns
TPERIOD
333-MHz CPUT and CPUC Period
Measured at crossing point VOX
2.9991
3.0009
ns
TPERIOD
400-MHz CPUT and CPUC Period
Measured at crossing point VOX
2.4993
2.5008
ns
TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
9.9970
10.0533
ns
TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
7.4978
7.5400
ns
TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
5.9982
6.0320
ns
TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
4.9985
5.0266
ns
TPERIODSS 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
3.7489
3.7700
ns
TPERIODSS 333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
2.9991
3.0160
ns
TPERIODSS 400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
2.4993
2.5133
ns
TSKEW
Any CPUT/C to CPUT/C Clock Skew,
SSC
Measured at crossing point VOX
–
100
ps
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
85
ps
TCCJ
CPU2/SRC4 Cycle to Cycle Jitter
Measured at crossing point VOX
TR / TF
CPUT and CPUC Rise and Fall Times
Measured from VOL = 0.175 to VOH = 0.525V
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR + TF)
∆TR
Rise Time Variation
∆TF
Fall Time Variation
VHIGH
Voltage High
Math averages Figure 7
VLOW
Voltage Low
Math averages Figure 7
VOX
Crossing Point Voltage at 0.7V Swing
VOVS
Maximum Overshoot Voltage
–
125
ps
175
700
ps
–
20
%
–
125
ps
–
125
ps
660
850
mv
–150
–
mv
250
550
mv
–
VHIGH +
0.3
V
–0.3
–
V
–
0.2
V
VUDS
Minimum Undershoot Voltage
VRB
Ring Back Voltage
SRC
TDC
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz SRCT and SRCC Period
Measured at crossing point VOX
9.9970
10.003
ns
TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
See Figure 7. Measure SE
9.9970
10.0533
ns
TSKEW
Any SRCT/C to SRCT/C Clock Skew
Measured at crossing point VOX
–
100
ps
TCCJ
SRCT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
125
ps
Document #: 38-07657 Rev. *A
Page 11 of 15
PRELIMINARY
CY28416
AC Electrical Specifications (continued)
Parameter
Description
LACC
SRCT/C Long Term Accuracy
TR / TF
SRCT and SRCC Rise and Fall Times
TRFM
Rise/Fall Matching
Condition
Min.
Max.
Unit
–
300
ppm
Measured from VOL = 0.175 to VOH = 0.525V
175
700
ps
Determined as a fraction of 2*(TR – TF)/(TR + TF)
–
20
%
Measured at crossing point VOX
∆TR
Rise Time Variation
–
125
ps
∆TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math averages Figure 7
660
850
mv
VLOW
Voltage Low
Math averages Figure 7
–150
–
mv
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
VOVS
Maximum Overshoot Voltage
–
VHIGH +
0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 7. Measure SE
–
0.2
V
PCI/PCIF
TDC
PCI Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.0090
ns
TPERIOD
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.1598
ns
THIGH
PCIF and PCI high time
Measurement at 2.4V
12.0
–
ns
TLOW
PCIF and PCI low time
Measurement at 0.4V
12.0
–
ns
TR / TF
PCIF and PCI rise and fall times
Measured between 0.4V and 2.4V
0.5
2.0
ns
TSKEW
Any PCI clock to Any PCI clock Skew
Measurement at 1.5V
–
500
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
250
ps
DOT
TDC
DOT96T and DOT96C Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
DOT96T and DOT96C Period
Measured at crossing point VOX
10.4135
10.4198
ns
TCCJ
DOT96T/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
250
ps
LACC
DOT96T/C Long Term Accuracy
Measured at crossing point VOX
–
300
ppm
TR / TF
DOT96T and DOT96C Rise and Fall
Times
Measured from VOL = 0.175 to VOH = 0.525V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR + TF)
–
20
%
∆TR
Rise Time Variation
–
125
ps
∆TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
Math averages Figure 7
660
850
mv
VLOW
Voltage Low
Math averages Figure 7
–150
–
mv
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
VOVS
Maximum Overshoot Voltage
–
VHIGH +
0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
See Figure 7. Measure SE
–
0.2
V
USB
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.8271
20.8396
ns
THIGH
USB high time
Measurement at 2.4V
8.094
10.036
ns
TLOW
USB low time
Measurement at 0.4V
7.694
9.836
ns
TR / TF
Rise and Fall Times
Measured between 0.4V and 2.4V
1.0
2.0
ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
Document #: 38-07657 Rev. *A
Page 12 of 15
PRELIMINARY
CY28416
AC Electrical Specifications (continued)
Parameter
Description
Min.
Max.
Unit
Measurement at 1.5V
45
55
%
REF Period
Measurement at 1.5V
69.8203
69.8622
ns
REF Rise and Fall Times
Measured between 0.4V and 2.4V
0.5
2.0
V/ns
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
–
1.8
ms
10.0
–
ns
0
–
ns
REF
TDC
REF Duty Cycle
TPERIOD
TR / TF
TCCJ
Condition
ENABLE/DISABLE and SETUP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
TSH
Stopclock Hold Time
Table 6. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
30
pF
48M Clock
20
pF
REF Clock
30
pF
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
M e a s u re m e n t
P o in t
TPCB
33Ω
CPUT
4 9 .9 Ω
M e a s u re m e n t
P o in t
TPCB
33Ω
CPUC
2pF
4 9 .9 Ω
IR E F
2pF
475Ω
Figure 7. 0.7V Load Configuration
Output under Test
tDC
Probe
3.3V
2.4V
Load
Cap
1.5V
0.4V
0V
Tr
Tf
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY28416OXC
CY28416OXCT
48-pin SSOP
48-pin SSOP—Tape and Reel
Document #: 38-07657 Rev. *A
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Page 13 of 15
PRELIMINARY
CY28416
Package Drawings and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips.
Document #: 38-07657 Rev. *A
Page 14 of 15
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY28416
Document History Page
Document Title: CY28416 Next Generation FTG for Intel® Architecture
Document #: 38-07657 Rev. *A
REV.
ECN NO.
Issue Date
**
224420
See ECN
*A
318277
See ECN
Document #: 38-07657 Rev. *A
Orig. of
Change
Description of Change
RGL/TUJ New Data Sheet
RGL
Changed VTTPWRGD and PCIF0 pins from PU to PD
Page 15 of 15
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